1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * This file configures the internal USB PHY in AM35X.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Based on omap_phy_internal.c code from Linux by
7*4882a593Smuzhiyun * Hema HK <hemahk@ti.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <asm/arch/am35x_def.h>
15*4882a593Smuzhiyun
am35x_musb_reset(struct udevice * dev)16*4882a593Smuzhiyun void am35x_musb_reset(struct udevice *dev)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun /* Reset the musb interface */
19*4882a593Smuzhiyun clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
20*4882a593Smuzhiyun 0, USBOTGSS_SW_RST);
21*4882a593Smuzhiyun clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
22*4882a593Smuzhiyun USBOTGSS_SW_RST, 0);
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
am35x_musb_phy_power(struct udevice * dev,u8 on)25*4882a593Smuzhiyun void am35x_musb_phy_power(struct udevice *dev, u8 on)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun unsigned long start = get_timer(0);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun if (on) {
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * Start the on-chip PHY and its PLL.
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun clrsetbits_le32(&am35x_scm_general_regs->devconf2,
34*4882a593Smuzhiyun CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
35*4882a593Smuzhiyun CONF2_PHY_PLLON);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun debug("Waiting for PHY clock good...\n");
38*4882a593Smuzhiyun while (!(readl(&am35x_scm_general_regs->devconf2)
39*4882a593Smuzhiyun & CONF2_PHYCLKGD)) {
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun if (get_timer(start) > CONFIG_SYS_HZ / 10) {
42*4882a593Smuzhiyun printf("musb PHY clock good timed out\n");
43*4882a593Smuzhiyun break;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun } else {
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun * Power down the on-chip PHY.
49*4882a593Smuzhiyun */
50*4882a593Smuzhiyun clrsetbits_le32(&am35x_scm_general_regs->devconf2,
51*4882a593Smuzhiyun CONF2_PHY_PLLON,
52*4882a593Smuzhiyun CONF2_PHYPWRDN | CONF2_OTGPWRDN);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
am35x_musb_clear_irq(struct udevice * dev)56*4882a593Smuzhiyun void am35x_musb_clear_irq(struct udevice *dev)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
59*4882a593Smuzhiyun 0, USBOTGSS_INT_CLR);
60*4882a593Smuzhiyun readl(&am35x_scm_general_regs->lvl_intr_clr);
61*4882a593Smuzhiyun }
62