358 		clrsetbits_le32(&dram->cru->pll[1].con2,  in rkclk_set_dpll()
555 		clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f);  in set_ctl_address_map()
591 		clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_PBDIV_BIT9_MASK,  in phy_pll_set()
593 		clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_POSTDIV_EN_MASK,  in phy_pll_set()
596 		clrsetbits_le32(PHY_REG(phy_base, 0x52),  in phy_pll_set()
598 		clrsetbits_le32(PHY_REG(phy_base, 0x53),  in phy_pll_set()
865 	clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_lp4_vref()
870 	clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_lp4_vref()
1037 	clrsetbits_le32(PHY_REG(phy_base, 0x100), 0x1f, phy_ca_drv);  in set_ds_odt()
1038 	clrsetbits_le32(PHY_REG(phy_base, 0x101), 0x1f, phy_ca_drv);  in set_ds_odt()
1039 	clrsetbits_le32(PHY_REG(phy_base, 0x102), 0x1f, phy_clk_drv);  in set_ds_odt()
1040 	clrsetbits_le32(PHY_REG(phy_base, 0x103), 0x1f, phy_clk_drv);  in set_ds_odt()
1042 		clrsetbits_le32(PHY_REG(phy_base, 0x107), 0x1f, phy_clk_drv);  in set_ds_odt()
1043 		clrsetbits_le32(PHY_REG(phy_base, 0x108), 0x1f, phy_clk_drv);  in set_ds_odt()
1045 		clrsetbits_le32(PHY_REG(phy_base, 0x107), 0x1f, phy_ca_drv);  in set_ds_odt()
1046 		clrsetbits_le32(PHY_REG(phy_base, 0x108), 0x1f, phy_ca_drv);  in set_ds_odt()
1049 	clrsetbits_le32(PHY_REG(phy_base, 0x106), 0x1f, sr_clk);  in set_ds_odt()
1059 		clrsetbits_le32(PHY_REG(phy_base, j + 1), 0x1f, phy_odt_up);  in set_ds_odt()
1060 		clrsetbits_le32(PHY_REG(phy_base, j), 0x1f, phy_odt_dn);  in set_ds_odt()
1061 		clrsetbits_le32(PHY_REG(phy_base, j + 2), 0x1f, phy_dq_drv);  in set_ds_odt()
1062 		clrsetbits_le32(PHY_REG(phy_base, j + 3), 0x1f, phy_dq_drv);  in set_ds_odt()
1065 		clrsetbits_le32(PHY_REG(phy_base, 0x114 + i * 0x10),  in set_ds_odt()
1070 		clrsetbits_le32(PHY_REG(phy_base, 0x117 + i * 0x10),  in set_ds_odt()
1171 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1194 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1203 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1210 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1285 		clrsetbits_le32(PHY_REG(phy_base, 0x20), 0x7 << 4,  in phy_cfg()
1396 	clrsetbits_le32(PHY_REG(phy_base, 0x70), BIT(1) | BIT(6) | BIT(4),  in update_dq_rx_prebit()
1599 	clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs));  in data_training_rg()
1601 	clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1);  in data_training_rg()
1605 	clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0);  in data_training_rg()
1650 	clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2),  in data_training_wl()
1653 	clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2),  in data_training_wl()
1670 	clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2),  in data_training_wl()
1672 	clrsetbits_le32(PHY_REG(phy_base, 2), 0x3 << 6, 0 << 6);  in data_training_wl()
1734 	clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xff, trefi_1x & 0xff);  in data_training_rd()
1735 	clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x3f, (trefi_1x >> 8) & 0x3f);  in data_training_rd()
1737 	clrsetbits_le32(PHY_REG(phy_base, 0x57), 0xff, trfc_1x);  in data_training_rd()
1739 	clrsetbits_le32(PHY_REG(phy_base, 0x61), 0xf << 4, 0x8 << 4);  in data_training_rd()
1742 	clrsetbits_le32(PHY_REG(phy_base, 0x71), 0x3 << 6, (0x2 >> cs) << 6);  in data_training_rd()
1758 	clrsetbits_le32(PHY_REG(phy_base, 0x230), 0x3f, dqs_default);  in data_training_rd()
1760 	clrsetbits_le32(PHY_REG(phy_base, 0x234), 0x3f, dqs_default);  in data_training_rd()
1762 	clrsetbits_le32(PHY_REG(phy_base, 0x2b0), 0x3f, dqs_default);  in data_training_rd()
1764 	clrsetbits_le32(PHY_REG(phy_base, 0x2b4), 0x3f, dqs_default);  in data_training_rd()
1767 	clrsetbits_le32(PHY_REG(phy_base, 0x70), 0x3, 0x1);  in data_training_rd()
1769 	clrsetbits_le32(PHY_REG(phy_base, 0x70), 0x3, 0x3);  in data_training_rd()
1825 		clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, 0x8);  in data_training_wr()
1826 		clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, 0x4);  in data_training_wr()
1833 	clrsetbits_le32(PHY_REG(phy_base, 0x7b), 0xff, 0x0);  in data_training_wr()
1835 	clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x7 << 2, 0x0 << 2);  in data_training_wr()
1837 	clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x3, 0x0);  in data_training_wr()
1839 	clrsetbits_le32(PHY_REG(phy_base, 0x7d), 0xff, 0x0);  in data_training_wr()
1841 	clrsetbits_le32(PHY_REG(phy_base, 0x7e), 0xff, 0x0);  in data_training_wr()
1853 	clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xff, trefi_1x & 0xff);  in data_training_wr()
1854 	clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x3f, (trefi_1x >> 8) & 0x3f);  in data_training_wr()
1856 	clrsetbits_le32(PHY_REG(phy_base, 0x57), 0xff, trfc_1x);  in data_training_wr()
1858 	clrsetbits_le32(PHY_REG(phy_base, 0x61), 0xf << 4, 0x8 << 4);  in data_training_wr()
1861 	clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x3 << 6, (0x2 >> cs) << 6);  in data_training_wr()
1910 		clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, cl);  in data_training_wr()
1911 		clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, cwl);  in data_training_wr()
2198 	clrsetbits_le32(&dram->grf->noc_con0, 0x3 << 0, 0 << 0);  in set_ddrconfig()
2487 		clrsetbits_le32(&map_info->byte_map[0],  in modify_ddr34_bw_byte_map()
2523 		clrsetbits_le32(pctl_base + DDR_PCTL2_SCHED1, 0xff, 0x1 << 0);  in sdram_init_()
2540 	clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, 0);  in sdram_init_()
2731 			clrsetbits_le32(PHY_REG(phy_base, 0xf), PHY_DQ_WIDTH_MASK,  in dram_detect_cap()
3418 	clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, dst_fsp);  in ddr_set_rate()
3421 	clrsetbits_le32(PHY_REG(phy_base, 0xc), 0x3 << 2, dst_fsp << 2);  in ddr_set_rate()