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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dam33xx-clocks.dtsi2 * Device Tree Source for AM33xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-mult = <1>;
24 clock-div = <1>;
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
31 clock-mult = <1>;
[all …]
H A Dam43xx-clocks.dtsi2 * Device Tree Source for AM43xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
20 #clock-cells = <0>;
21 compatible = "ti,mux-clock";
28 #clock-cells = <0>;
29 compatible = "ti,mux-clock";
36 #clock-cells = <0>;
37 compatible = "fixed-factor-clock";
39 clock-mult = <1>;
[all …]
H A Domap3xxx-clocks.dtsi2 * Device Tree Source for OMAP3 clock data
12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
25 #clock-cells = <0>;
26 compatible = "ti,divider-clock";
35 #clock-cells = <0>;
36 compatible = "ti,gate-clock";
[all …]
H A Ddra7xx-clocks.dtsi2 * Device Tree Source for DRA7xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,dra7-atl-clock";
18 #clock-cells = <0>;
19 compatible = "ti,dra7-atl-clock";
24 #clock-cells = <0>;
25 compatible = "ti,dra7-atl-clock";
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
36 #clock-cells = <0>;
[all …]
H A Dkeystone-clocks.dtsi2 * Device Tree Source for Keystone 2 clock tree
17 #clock-cells = <0>;
18 compatible = "ti,keystone,pll-mux-clock";
23 clock-output-names = "mainmuxclk";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
30 clock-div = <1>;
31 clock-mult = <1>;
32 clock-output-names = "chipclk1";
36 #clock-cells = <0>;
[all …]
H A Dkeystone-k2hk-clocks.dtsi4 * Keystone 2 Kepler/Hawking SoC clock nodes
13 #clock-cells = <0>;
14 compatible = "ti,keystone,pll-clock";
16 clock-output-names = "arm-pll-clk";
22 #clock-cells = <0>;
23 compatible = "ti,keystone,main-pll-clock";
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "papllclk";
39 #clock-cells = <0>;
[all …]
H A Ddm816x-clocks.dtsi9 #clock-cells = <1>;
10 compatible = "ti,dm816-fapll-clock";
13 clock-indices = <1>, <2>, <3>, <4>, <5>,
15 clock-output-names = "main_pll_clk1",
25 #clock-cells = <1>;
26 compatible = "ti,dm816-fapll-clock";
29 clock-indices = <1>, <2>, <3>, <4>;
30 clock-output-names = "ddr_pll_clk1",
37 #clock-cells = <1>;
38 compatible = "ti,dm816-fapll-clock";
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi2 * Device Tree Source for OMAP34xx/OMAP36xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,composite-no-wait-gate-clock";
20 #clock-cells = <0>;
21 compatible = "ti,composite-divider-clock";
29 #clock-cells = <0>;
30 compatible = "ti,composite-clock";
35 #clock-cells = <0>;
36 compatible = "fixed-factor-clock";
38 clock-mult = <1>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Domap24xx-clocks.dtsi3 * Device Tree Source for OMAP24xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
31 #clock-cells = <0>;
32 compatible = "ti,composite-clock";
39 #clock-cells = <0>;
[all …]
H A Dam43xx-clocks.dtsi3 * Device Tree Source for AM43xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,mux-clock";
25 #clock-cells = <0>;
26 compatible = "ti,mux-clock";
33 #clock-cells = <0>;
34 compatible = "fixed-factor-clock";
36 clock-mult = <1>;
[all …]
H A Domap3xxx-clocks.dtsi3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
32 #clock-cells = <0>;
33 compatible = "ti,gate-clock";
[all …]
H A Dam33xx-clocks.dtsi3 * Device Tree Source for AM33xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <1>;
25 #clock-cells = <0>;
26 compatible = "fixed-factor-clock";
28 clock-mult = <1>;
[all …]
H A Domap54xx-clocks.dtsi3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <12000000>;
15 #clock-cells = <0>;
16 compatible = "ti,gate-clock";
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <32768>;
29 #clock-cells = <0>;
[all …]
H A Dkeystone-clocks.dtsi3 * Device Tree Source for Keystone 2 clock tree
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
20 clock-output-names = "mainmuxclk";
24 #clock-cells = <0>;
25 compatible = "fixed-factor-clock";
27 clock-div = <1>;
28 clock-mult = <1>;
29 clock-output-names = "chipclk1";
33 #clock-cells = <0>;
[all …]
H A Ddra7xx-clocks.dtsi3 * Device Tree Source for DRA7xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
15 #clock-cells = <0>;
16 compatible = "ti,dra7-atl-clock";
21 #clock-cells = <0>;
22 compatible = "ti,dra7-atl-clock";
27 #clock-cells = <0>;
28 compatible = "ti,dra7-atl-clock";
33 #clock-cells = <0>;
[all …]
H A Domap44xx-clocks.dtsi3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <59000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <12000000>;
21 #clock-cells = <0>;
22 compatible = "ti,gate-clock";
29 #clock-cells = <0>;
[all …]
H A Ddm814x-clocks.dtsi10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
33 #clock-cells = <1>;
34 compatible = "ti,dm814-adpll-lj-clock";
[all …]
H A Dste-nomadik-stn8815.dtsi41 clock-names = "timclk", "apb_pclk";
50 clock-names = "timclk", "apb_pclk";
199 #clock-cells = <0>;
200 compatible = "fixed-clock";
201 clock-frequency = <19200000>;
205 * The 2.4 MHz TIMCLK reference clock is active at
207 * divided by 8. This clock is used by the timers and
211 #clock-cells = <0>;
212 compatible = "fixed-factor-clock";
213 clock-div = <8>;
[all …]
H A Dkeystone-k2hk-clocks.dtsi3 * Keystone 2 Kepler/Hawking SoC clock nodes
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
27 #clock-cells = <0>;
28 compatible = "ti,keystone,pll-clock";
30 clock-output-names = "papllclk";
36 #clock-cells = <0>;
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-no-wait-gate-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-divider-clock";
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
35 clock-mult = <1>;
[all …]
H A Ddm816x-clocks.dtsi5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_clk1",
33 #clock-cells = <1>;
34 compatible = "ti,dm816-fapll-clock";
[all …]
H A Dexynos5420.dtsi14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
52 clock-latency-ns = <140000>;
57 clock-latency-ns = <140000>;
62 clock-latency-ns = <140000>;
67 clock-latency-ns = <140000>;
72 clock-latency-ns = <140000>;
77 clock-latency-ns = <140000>;
82 clock-latency-ns = <140000>;
87 clock-latency-ns = <140000>;
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dclock.c92 struct mlx5_clock *clock = container_of(cc, struct mlx5_clock, cycles); in read_internal_timer() local
93 struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, in read_internal_timer()
94 clock); in read_internal_timer()
102 struct mlx5_clock *clock = &mdev->clock; in mlx5_update_clock_info_page() local
112 clock_info->cycles = clock->tc.cycle_last; in mlx5_update_clock_info_page()
113 clock_info->mult = clock->cycles.mult; in mlx5_update_clock_info_page()
114 clock_info->nsec = clock->tc.nsec; in mlx5_update_clock_info_page()
115 clock_info->frac = clock->tc.frac; in mlx5_update_clock_info_page()
125 struct mlx5_clock *clock = container_of(pps_info, struct mlx5_clock, in mlx5_pps_out() local
127 struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, in mlx5_pps_out()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ipa/
H A Dipa_clock.c76 static int ipa_interconnect_init(struct ipa_clock *clock, struct device *dev) in ipa_interconnect_init() argument
83 clock->memory_path = path; in ipa_interconnect_init()
88 clock->imem_path = path; in ipa_interconnect_init()
93 clock->config_path = path; in ipa_interconnect_init()
98 icc_put(clock->imem_path); in ipa_interconnect_init()
100 icc_put(clock->memory_path); in ipa_interconnect_init()
106 static void ipa_interconnect_exit(struct ipa_clock *clock) in ipa_interconnect_exit() argument
108 icc_put(clock->config_path); in ipa_interconnect_exit()
109 icc_put(clock->imem_path); in ipa_interconnect_exit()
110 icc_put(clock->memory_path); in ipa_interconnect_exit()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dlpc1850-cgu.txt4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
26 containing clock control registers
27 - #clock-cells:
[all …]

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