xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/keystone-clocks.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Device Tree Source for Keystone 2 clock tree
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments, Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
7*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as
8*4882a593Smuzhiyun * published by the Free Software Foundation.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyunclocks {
12*4882a593Smuzhiyun	#address-cells = <1>;
13*4882a593Smuzhiyun	#size-cells = <1>;
14*4882a593Smuzhiyun	ranges;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	mainmuxclk: mainmuxclk@2310108 {
17*4882a593Smuzhiyun		#clock-cells = <0>;
18*4882a593Smuzhiyun		compatible = "ti,keystone,pll-mux-clock";
19*4882a593Smuzhiyun		clocks = <&mainpllclk>, <&refclksys>;
20*4882a593Smuzhiyun		reg = <0x02310108 4>;
21*4882a593Smuzhiyun		bit-shift = <23>;
22*4882a593Smuzhiyun		bit-mask = <1>;
23*4882a593Smuzhiyun		clock-output-names = "mainmuxclk";
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	chipclk1: chipclk1 {
27*4882a593Smuzhiyun		#clock-cells = <0>;
28*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
29*4882a593Smuzhiyun		clocks = <&mainmuxclk>;
30*4882a593Smuzhiyun		clock-div = <1>;
31*4882a593Smuzhiyun		clock-mult = <1>;
32*4882a593Smuzhiyun		clock-output-names = "chipclk1";
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	chipclk1rstiso: chipclk1rstiso {
36*4882a593Smuzhiyun		#clock-cells = <0>;
37*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
38*4882a593Smuzhiyun		clocks = <&mainmuxclk>;
39*4882a593Smuzhiyun		clock-div = <1>;
40*4882a593Smuzhiyun		clock-mult = <1>;
41*4882a593Smuzhiyun		clock-output-names = "chipclk1rstiso";
42*4882a593Smuzhiyun	};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun	gemtraceclk: gemtraceclk@2310120 {
45*4882a593Smuzhiyun		#clock-cells = <0>;
46*4882a593Smuzhiyun		compatible = "ti,keystone,pll-divider-clock";
47*4882a593Smuzhiyun		clocks = <&mainmuxclk>;
48*4882a593Smuzhiyun		reg = <0x02310120 4>;
49*4882a593Smuzhiyun		bit-shift = <0>;
50*4882a593Smuzhiyun		bit-mask = <8>;
51*4882a593Smuzhiyun		clock-output-names = "gemtraceclk";
52*4882a593Smuzhiyun	};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	chipstmxptclk: chipstmxptclk {
55*4882a593Smuzhiyun		#clock-cells = <0>;
56*4882a593Smuzhiyun		compatible = "ti,keystone,pll-divider-clock";
57*4882a593Smuzhiyun		clocks = <&mainmuxclk>;
58*4882a593Smuzhiyun		reg = <0x02310164 4>;
59*4882a593Smuzhiyun		bit-shift = <0>;
60*4882a593Smuzhiyun		bit-mask = <8>;
61*4882a593Smuzhiyun		clock-output-names = "chipstmxptclk";
62*4882a593Smuzhiyun	};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun	chipclk12: chipclk12 {
65*4882a593Smuzhiyun		#clock-cells = <0>;
66*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
67*4882a593Smuzhiyun		clocks = <&chipclk1>;
68*4882a593Smuzhiyun		clock-div = <2>;
69*4882a593Smuzhiyun		clock-mult = <1>;
70*4882a593Smuzhiyun		clock-output-names = "chipclk12";
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	chipclk13: chipclk13 {
74*4882a593Smuzhiyun		#clock-cells = <0>;
75*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
76*4882a593Smuzhiyun		clocks = <&chipclk1>;
77*4882a593Smuzhiyun		clock-div = <3>;
78*4882a593Smuzhiyun		clock-mult = <1>;
79*4882a593Smuzhiyun		clock-output-names = "chipclk13";
80*4882a593Smuzhiyun	};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	paclk13: paclk13 {
83*4882a593Smuzhiyun		#clock-cells = <0>;
84*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
85*4882a593Smuzhiyun		clocks = <&papllclk>;
86*4882a593Smuzhiyun		clock-div = <3>;
87*4882a593Smuzhiyun		clock-mult = <1>;
88*4882a593Smuzhiyun		clock-output-names = "paclk13";
89*4882a593Smuzhiyun	};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun	chipclk14: chipclk14 {
92*4882a593Smuzhiyun		#clock-cells = <0>;
93*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
94*4882a593Smuzhiyun		clocks = <&chipclk1>;
95*4882a593Smuzhiyun		clock-div = <4>;
96*4882a593Smuzhiyun		clock-mult = <1>;
97*4882a593Smuzhiyun		clock-output-names = "chipclk14";
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	chipclk16: chipclk16 {
101*4882a593Smuzhiyun		#clock-cells = <0>;
102*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
103*4882a593Smuzhiyun		clocks = <&chipclk1>;
104*4882a593Smuzhiyun		clock-div = <6>;
105*4882a593Smuzhiyun		clock-mult = <1>;
106*4882a593Smuzhiyun		clock-output-names = "chipclk16";
107*4882a593Smuzhiyun	};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun	chipclk112: chipclk112 {
110*4882a593Smuzhiyun		#clock-cells = <0>;
111*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
112*4882a593Smuzhiyun		clocks = <&chipclk1>;
113*4882a593Smuzhiyun		clock-div = <12>;
114*4882a593Smuzhiyun		clock-mult = <1>;
115*4882a593Smuzhiyun		clock-output-names = "chipclk112";
116*4882a593Smuzhiyun	};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun	chipclk124: chipclk124 {
119*4882a593Smuzhiyun		#clock-cells = <0>;
120*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
121*4882a593Smuzhiyun		clocks = <&chipclk1>;
122*4882a593Smuzhiyun		clock-div = <24>;
123*4882a593Smuzhiyun		clock-mult = <1>;
124*4882a593Smuzhiyun		clock-output-names = "chipclk114";
125*4882a593Smuzhiyun	};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun	chipclk1rstiso13: chipclk1rstiso13 {
128*4882a593Smuzhiyun		#clock-cells = <0>;
129*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
130*4882a593Smuzhiyun		clocks = <&chipclk1rstiso>;
131*4882a593Smuzhiyun		clock-div = <3>;
132*4882a593Smuzhiyun		clock-mult = <1>;
133*4882a593Smuzhiyun		clock-output-names = "chipclk1rstiso13";
134*4882a593Smuzhiyun	};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun	chipclk1rstiso14: chipclk1rstiso14 {
137*4882a593Smuzhiyun		#clock-cells = <0>;
138*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
139*4882a593Smuzhiyun		clocks = <&chipclk1rstiso>;
140*4882a593Smuzhiyun		clock-div = <4>;
141*4882a593Smuzhiyun		clock-mult = <1>;
142*4882a593Smuzhiyun		clock-output-names = "chipclk1rstiso14";
143*4882a593Smuzhiyun	};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun	chipclk1rstiso16: chipclk1rstiso16 {
146*4882a593Smuzhiyun		#clock-cells = <0>;
147*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
148*4882a593Smuzhiyun		clocks = <&chipclk1rstiso>;
149*4882a593Smuzhiyun		clock-div = <6>;
150*4882a593Smuzhiyun		clock-mult = <1>;
151*4882a593Smuzhiyun		clock-output-names = "chipclk1rstiso16";
152*4882a593Smuzhiyun	};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun	chipclk1rstiso112: chipclk1rstiso112 {
155*4882a593Smuzhiyun		#clock-cells = <0>;
156*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
157*4882a593Smuzhiyun		clocks = <&chipclk1rstiso>;
158*4882a593Smuzhiyun		clock-div = <12>;
159*4882a593Smuzhiyun		clock-mult = <1>;
160*4882a593Smuzhiyun		clock-output-names = "chipclk1rstiso112";
161*4882a593Smuzhiyun	};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun	clkmodrst0: clkmodrst0 {
164*4882a593Smuzhiyun		#clock-cells = <0>;
165*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
166*4882a593Smuzhiyun		clocks = <&chipclk16>;
167*4882a593Smuzhiyun		clock-output-names = "modrst0";
168*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
169*4882a593Smuzhiyun		reg-names = "control", "domain";
170*4882a593Smuzhiyun		domain-id = <0>;
171*4882a593Smuzhiyun	};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun	clkusb: clkusb {
175*4882a593Smuzhiyun		#clock-cells = <0>;
176*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
177*4882a593Smuzhiyun		clocks = <&chipclk16>;
178*4882a593Smuzhiyun		clock-output-names = "usb";
179*4882a593Smuzhiyun		reg = <0x02350008 0xb00>, <0x02350000 0x400>;
180*4882a593Smuzhiyun		reg-names = "control", "domain";
181*4882a593Smuzhiyun		domain-id = <0>;
182*4882a593Smuzhiyun	};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun	clkaemifspi: clkaemifspi {
185*4882a593Smuzhiyun		#clock-cells = <0>;
186*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
187*4882a593Smuzhiyun		clocks = <&chipclk16>;
188*4882a593Smuzhiyun		clock-output-names = "aemif-spi";
189*4882a593Smuzhiyun		reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
190*4882a593Smuzhiyun		reg-names = "control", "domain";
191*4882a593Smuzhiyun		domain-id = <0>;
192*4882a593Smuzhiyun	};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun	clkdebugsstrc: clkdebugsstrc {
196*4882a593Smuzhiyun		#clock-cells = <0>;
197*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
198*4882a593Smuzhiyun		clocks = <&chipclk13>;
199*4882a593Smuzhiyun		clock-output-names = "debugss-trc";
200*4882a593Smuzhiyun		reg = <0x02350014 0xb00>, <0x02350000 0x400>;
201*4882a593Smuzhiyun		reg-names = "control", "domain";
202*4882a593Smuzhiyun		domain-id = <1>;
203*4882a593Smuzhiyun	};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun	clktetbtrc: clktetbtrc {
206*4882a593Smuzhiyun		#clock-cells = <0>;
207*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
208*4882a593Smuzhiyun		clocks = <&chipclk13>;
209*4882a593Smuzhiyun		clock-output-names = "tetb-trc";
210*4882a593Smuzhiyun		reg = <0x02350018 0xb00>, <0x02350004 0x400>;
211*4882a593Smuzhiyun		reg-names = "control", "domain";
212*4882a593Smuzhiyun		domain-id = <1>;
213*4882a593Smuzhiyun	};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun	clkpa: clkpa {
216*4882a593Smuzhiyun		#clock-cells = <0>;
217*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
218*4882a593Smuzhiyun		clocks = <&paclk13>;
219*4882a593Smuzhiyun		clock-output-names = "pa";
220*4882a593Smuzhiyun		reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
221*4882a593Smuzhiyun		reg-names = "control", "domain";
222*4882a593Smuzhiyun		domain-id = <2>;
223*4882a593Smuzhiyun	};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun	clkcpgmac: clkcpgmac {
226*4882a593Smuzhiyun		#clock-cells = <0>;
227*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
228*4882a593Smuzhiyun		clocks = <&clkpa>;
229*4882a593Smuzhiyun		clock-output-names = "cpgmac";
230*4882a593Smuzhiyun		reg = <0x02350020 0xb00>, <0x02350008 0x400>;
231*4882a593Smuzhiyun		reg-names = "control", "domain";
232*4882a593Smuzhiyun		domain-id = <2>;
233*4882a593Smuzhiyun	};
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun	clksa: clksa {
236*4882a593Smuzhiyun		#clock-cells = <0>;
237*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
238*4882a593Smuzhiyun		clocks = <&clkpa>;
239*4882a593Smuzhiyun		clock-output-names = "sa";
240*4882a593Smuzhiyun		reg = <0x02350024 0xb00>, <0x02350008 0x400>;
241*4882a593Smuzhiyun		reg-names = "control", "domain";
242*4882a593Smuzhiyun		domain-id = <2>;
243*4882a593Smuzhiyun	};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun	clkpcie: clkpcie {
246*4882a593Smuzhiyun		#clock-cells = <0>;
247*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
248*4882a593Smuzhiyun		clocks = <&chipclk12>;
249*4882a593Smuzhiyun		clock-output-names = "pcie";
250*4882a593Smuzhiyun		reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
251*4882a593Smuzhiyun		reg-names = "control", "domain";
252*4882a593Smuzhiyun		domain-id = <3>;
253*4882a593Smuzhiyun	};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun	clksr: clksr {
256*4882a593Smuzhiyun		#clock-cells = <0>;
257*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
258*4882a593Smuzhiyun		clocks = <&chipclk1rstiso112>;
259*4882a593Smuzhiyun		clock-output-names = "sr";
260*4882a593Smuzhiyun		reg = <0x02350034 0xb00>, <0x02350018 0x400>;
261*4882a593Smuzhiyun		reg-names = "control", "domain";
262*4882a593Smuzhiyun		domain-id = <6>;
263*4882a593Smuzhiyun	};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun	clkgem0: clkgem0 {
266*4882a593Smuzhiyun		#clock-cells = <0>;
267*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
268*4882a593Smuzhiyun		clocks = <&chipclk1>;
269*4882a593Smuzhiyun		clock-output-names = "gem0";
270*4882a593Smuzhiyun		reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
271*4882a593Smuzhiyun		reg-names = "control", "domain";
272*4882a593Smuzhiyun		domain-id = <8>;
273*4882a593Smuzhiyun	};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun	clkddr30: clkddr30 {
276*4882a593Smuzhiyun		#clock-cells = <0>;
277*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
278*4882a593Smuzhiyun		clocks = <&chipclk12>;
279*4882a593Smuzhiyun		clock-output-names = "ddr3-0";
280*4882a593Smuzhiyun		reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
281*4882a593Smuzhiyun		reg-names = "control", "domain";
282*4882a593Smuzhiyun		domain-id = <16>;
283*4882a593Smuzhiyun	};
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun	clkwdtimer0: clkwdtimer0 {
286*4882a593Smuzhiyun		#clock-cells = <0>;
287*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
288*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
289*4882a593Smuzhiyun		clock-output-names = "timer0";
290*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
291*4882a593Smuzhiyun		reg-names = "control", "domain";
292*4882a593Smuzhiyun		domain-id = <0>;
293*4882a593Smuzhiyun	};
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun	clkwdtimer1: clkwdtimer1 {
296*4882a593Smuzhiyun		#clock-cells = <0>;
297*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
298*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
299*4882a593Smuzhiyun		clock-output-names = "timer1";
300*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
301*4882a593Smuzhiyun		reg-names = "control", "domain";
302*4882a593Smuzhiyun		domain-id = <0>;
303*4882a593Smuzhiyun	};
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun	clkwdtimer2: clkwdtimer2 {
306*4882a593Smuzhiyun		#clock-cells = <0>;
307*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
308*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
309*4882a593Smuzhiyun		clock-output-names = "timer2";
310*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
311*4882a593Smuzhiyun		reg-names = "control", "domain";
312*4882a593Smuzhiyun		domain-id = <0>;
313*4882a593Smuzhiyun	};
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun	clkwdtimer3: clkwdtimer3 {
316*4882a593Smuzhiyun		#clock-cells = <0>;
317*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
318*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
319*4882a593Smuzhiyun		clock-output-names = "timer3";
320*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
321*4882a593Smuzhiyun		reg-names = "control", "domain";
322*4882a593Smuzhiyun		domain-id = <0>;
323*4882a593Smuzhiyun	};
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun	clktimer15: clktimer15 {
326*4882a593Smuzhiyun		#clock-cells = <0>;
327*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
328*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
329*4882a593Smuzhiyun		clock-output-names = "timer15";
330*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
331*4882a593Smuzhiyun		reg-names = "control", "domain";
332*4882a593Smuzhiyun		domain-id = <0>;
333*4882a593Smuzhiyun	};
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun	clkuart0: clkuart0 {
336*4882a593Smuzhiyun		#clock-cells = <0>;
337*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
338*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
339*4882a593Smuzhiyun		clock-output-names = "uart0";
340*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
341*4882a593Smuzhiyun		reg-names = "control", "domain";
342*4882a593Smuzhiyun		domain-id = <0>;
343*4882a593Smuzhiyun	};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun	clkuart1: clkuart1 {
346*4882a593Smuzhiyun		#clock-cells = <0>;
347*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
348*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
349*4882a593Smuzhiyun		clock-output-names = "uart1";
350*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
351*4882a593Smuzhiyun		reg-names = "control", "domain";
352*4882a593Smuzhiyun		domain-id = <0>;
353*4882a593Smuzhiyun	};
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun	clkaemif: clkaemif {
356*4882a593Smuzhiyun		#clock-cells = <0>;
357*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
358*4882a593Smuzhiyun		clocks = <&clkaemifspi>;
359*4882a593Smuzhiyun		clock-output-names = "aemif";
360*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
361*4882a593Smuzhiyun		reg-names = "control", "domain";
362*4882a593Smuzhiyun		domain-id = <0>;
363*4882a593Smuzhiyun	};
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun	clkusim: clkusim {
366*4882a593Smuzhiyun		#clock-cells = <0>;
367*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
368*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
369*4882a593Smuzhiyun		clock-output-names = "usim";
370*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
371*4882a593Smuzhiyun		reg-names = "control", "domain";
372*4882a593Smuzhiyun		domain-id = <0>;
373*4882a593Smuzhiyun	};
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun	clki2c: clki2c {
376*4882a593Smuzhiyun		#clock-cells = <0>;
377*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
378*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
379*4882a593Smuzhiyun		clock-output-names = "i2c";
380*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
381*4882a593Smuzhiyun		reg-names = "control", "domain";
382*4882a593Smuzhiyun		domain-id = <0>;
383*4882a593Smuzhiyun	};
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun	clkspi: clkspi {
386*4882a593Smuzhiyun		#clock-cells = <0>;
387*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
388*4882a593Smuzhiyun		clocks = <&clkaemifspi>;
389*4882a593Smuzhiyun		clock-output-names = "spi";
390*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
391*4882a593Smuzhiyun		reg-names = "control", "domain";
392*4882a593Smuzhiyun		domain-id = <0>;
393*4882a593Smuzhiyun	};
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun	clkgpio: clkgpio {
396*4882a593Smuzhiyun		#clock-cells = <0>;
397*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
398*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
399*4882a593Smuzhiyun		clock-output-names = "gpio";
400*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
401*4882a593Smuzhiyun		reg-names = "control", "domain";
402*4882a593Smuzhiyun		domain-id = <0>;
403*4882a593Smuzhiyun	};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun	clkkeymgr: clkkeymgr {
406*4882a593Smuzhiyun		#clock-cells = <0>;
407*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
408*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
409*4882a593Smuzhiyun		clock-output-names = "keymgr";
410*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
411*4882a593Smuzhiyun		reg-names = "control", "domain";
412*4882a593Smuzhiyun		domain-id = <0>;
413*4882a593Smuzhiyun	};
414*4882a593Smuzhiyun};
415