xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/keystone-clocks.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for Keystone 2 clock tree
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyunclocks {
9*4882a593Smuzhiyun	#address-cells = <1>;
10*4882a593Smuzhiyun	#size-cells = <1>;
11*4882a593Smuzhiyun	ranges;
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	mainmuxclk: mainmuxclk@2310108 {
14*4882a593Smuzhiyun		#clock-cells = <0>;
15*4882a593Smuzhiyun		compatible = "ti,keystone,pll-mux-clock";
16*4882a593Smuzhiyun		clocks = <&mainpllclk>, <&refclksys>;
17*4882a593Smuzhiyun		reg = <0x02310108 4>;
18*4882a593Smuzhiyun		bit-shift = <23>;
19*4882a593Smuzhiyun		bit-mask = <1>;
20*4882a593Smuzhiyun		clock-output-names = "mainmuxclk";
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	chipclk1: chipclk1 {
24*4882a593Smuzhiyun		#clock-cells = <0>;
25*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
26*4882a593Smuzhiyun		clocks = <&mainmuxclk>;
27*4882a593Smuzhiyun		clock-div = <1>;
28*4882a593Smuzhiyun		clock-mult = <1>;
29*4882a593Smuzhiyun		clock-output-names = "chipclk1";
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	chipclk1rstiso: chipclk1rstiso {
33*4882a593Smuzhiyun		#clock-cells = <0>;
34*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
35*4882a593Smuzhiyun		clocks = <&mainmuxclk>;
36*4882a593Smuzhiyun		clock-div = <1>;
37*4882a593Smuzhiyun		clock-mult = <1>;
38*4882a593Smuzhiyun		clock-output-names = "chipclk1rstiso";
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	gemtraceclk: gemtraceclk@2310120 {
42*4882a593Smuzhiyun		#clock-cells = <0>;
43*4882a593Smuzhiyun		compatible = "ti,keystone,pll-divider-clock";
44*4882a593Smuzhiyun		clocks = <&mainmuxclk>;
45*4882a593Smuzhiyun		reg = <0x02310120 4>;
46*4882a593Smuzhiyun		bit-shift = <0>;
47*4882a593Smuzhiyun		bit-mask = <8>;
48*4882a593Smuzhiyun		clock-output-names = "gemtraceclk";
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	chipstmxptclk: chipstmxptclk@2310164 {
52*4882a593Smuzhiyun		#clock-cells = <0>;
53*4882a593Smuzhiyun		compatible = "ti,keystone,pll-divider-clock";
54*4882a593Smuzhiyun		clocks = <&mainmuxclk>;
55*4882a593Smuzhiyun		reg = <0x02310164 4>;
56*4882a593Smuzhiyun		bit-shift = <0>;
57*4882a593Smuzhiyun		bit-mask = <8>;
58*4882a593Smuzhiyun		clock-output-names = "chipstmxptclk";
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun	chipclk12: chipclk12 {
62*4882a593Smuzhiyun		#clock-cells = <0>;
63*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
64*4882a593Smuzhiyun		clocks = <&chipclk1>;
65*4882a593Smuzhiyun		clock-div = <2>;
66*4882a593Smuzhiyun		clock-mult = <1>;
67*4882a593Smuzhiyun		clock-output-names = "chipclk12";
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	chipclk13: chipclk13 {
71*4882a593Smuzhiyun		#clock-cells = <0>;
72*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
73*4882a593Smuzhiyun		clocks = <&chipclk1>;
74*4882a593Smuzhiyun		clock-div = <3>;
75*4882a593Smuzhiyun		clock-mult = <1>;
76*4882a593Smuzhiyun		clock-output-names = "chipclk13";
77*4882a593Smuzhiyun	};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	paclk13: paclk13 {
80*4882a593Smuzhiyun		#clock-cells = <0>;
81*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
82*4882a593Smuzhiyun		clocks = <&papllclk>;
83*4882a593Smuzhiyun		clock-div = <3>;
84*4882a593Smuzhiyun		clock-mult = <1>;
85*4882a593Smuzhiyun		clock-output-names = "paclk13";
86*4882a593Smuzhiyun	};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun	chipclk14: chipclk14 {
89*4882a593Smuzhiyun		#clock-cells = <0>;
90*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
91*4882a593Smuzhiyun		clocks = <&chipclk1>;
92*4882a593Smuzhiyun		clock-div = <4>;
93*4882a593Smuzhiyun		clock-mult = <1>;
94*4882a593Smuzhiyun		clock-output-names = "chipclk14";
95*4882a593Smuzhiyun	};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun	chipclk16: chipclk16 {
98*4882a593Smuzhiyun		#clock-cells = <0>;
99*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
100*4882a593Smuzhiyun		clocks = <&chipclk1>;
101*4882a593Smuzhiyun		clock-div = <6>;
102*4882a593Smuzhiyun		clock-mult = <1>;
103*4882a593Smuzhiyun		clock-output-names = "chipclk16";
104*4882a593Smuzhiyun	};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun	chipclk112: chipclk112 {
107*4882a593Smuzhiyun		#clock-cells = <0>;
108*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
109*4882a593Smuzhiyun		clocks = <&chipclk1>;
110*4882a593Smuzhiyun		clock-div = <12>;
111*4882a593Smuzhiyun		clock-mult = <1>;
112*4882a593Smuzhiyun		clock-output-names = "chipclk112";
113*4882a593Smuzhiyun	};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun	chipclk124: chipclk124 {
116*4882a593Smuzhiyun		#clock-cells = <0>;
117*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
118*4882a593Smuzhiyun		clocks = <&chipclk1>;
119*4882a593Smuzhiyun		clock-div = <24>;
120*4882a593Smuzhiyun		clock-mult = <1>;
121*4882a593Smuzhiyun		clock-output-names = "chipclk114";
122*4882a593Smuzhiyun	};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	chipclk1rstiso13: chipclk1rstiso13 {
125*4882a593Smuzhiyun		#clock-cells = <0>;
126*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
127*4882a593Smuzhiyun		clocks = <&chipclk1rstiso>;
128*4882a593Smuzhiyun		clock-div = <3>;
129*4882a593Smuzhiyun		clock-mult = <1>;
130*4882a593Smuzhiyun		clock-output-names = "chipclk1rstiso13";
131*4882a593Smuzhiyun	};
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun	chipclk1rstiso14: chipclk1rstiso14 {
134*4882a593Smuzhiyun		#clock-cells = <0>;
135*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
136*4882a593Smuzhiyun		clocks = <&chipclk1rstiso>;
137*4882a593Smuzhiyun		clock-div = <4>;
138*4882a593Smuzhiyun		clock-mult = <1>;
139*4882a593Smuzhiyun		clock-output-names = "chipclk1rstiso14";
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	chipclk1rstiso16: chipclk1rstiso16 {
143*4882a593Smuzhiyun		#clock-cells = <0>;
144*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
145*4882a593Smuzhiyun		clocks = <&chipclk1rstiso>;
146*4882a593Smuzhiyun		clock-div = <6>;
147*4882a593Smuzhiyun		clock-mult = <1>;
148*4882a593Smuzhiyun		clock-output-names = "chipclk1rstiso16";
149*4882a593Smuzhiyun	};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun	chipclk1rstiso112: chipclk1rstiso112 {
152*4882a593Smuzhiyun		#clock-cells = <0>;
153*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
154*4882a593Smuzhiyun		clocks = <&chipclk1rstiso>;
155*4882a593Smuzhiyun		clock-div = <12>;
156*4882a593Smuzhiyun		clock-mult = <1>;
157*4882a593Smuzhiyun		clock-output-names = "chipclk1rstiso112";
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun	clkmodrst0: clkmodrst0@2350000 {
161*4882a593Smuzhiyun		#clock-cells = <0>;
162*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
163*4882a593Smuzhiyun		clocks = <&chipclk16>;
164*4882a593Smuzhiyun		clock-output-names = "modrst0";
165*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
166*4882a593Smuzhiyun		reg-names = "control", "domain";
167*4882a593Smuzhiyun		domain-id = <0>;
168*4882a593Smuzhiyun	};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun	clkusb: clkusb@2350008 {
172*4882a593Smuzhiyun		#clock-cells = <0>;
173*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
174*4882a593Smuzhiyun		clocks = <&chipclk16>;
175*4882a593Smuzhiyun		clock-output-names = "usb";
176*4882a593Smuzhiyun		reg = <0x02350008 0xb00>, <0x02350000 0x400>;
177*4882a593Smuzhiyun		reg-names = "control", "domain";
178*4882a593Smuzhiyun		domain-id = <0>;
179*4882a593Smuzhiyun	};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun	clkaemifspi: clkaemifspi@235000c {
182*4882a593Smuzhiyun		#clock-cells = <0>;
183*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
184*4882a593Smuzhiyun		clocks = <&chipclk16>;
185*4882a593Smuzhiyun		clock-output-names = "aemif-spi";
186*4882a593Smuzhiyun		reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
187*4882a593Smuzhiyun		reg-names = "control", "domain";
188*4882a593Smuzhiyun		domain-id = <0>;
189*4882a593Smuzhiyun	};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun	clkdebugsstrc: clkdebugsstrc@2350014 {
193*4882a593Smuzhiyun		#clock-cells = <0>;
194*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
195*4882a593Smuzhiyun		clocks = <&chipclk13>;
196*4882a593Smuzhiyun		clock-output-names = "debugss-trc";
197*4882a593Smuzhiyun		reg = <0x02350014 0xb00>, <0x02350000 0x400>;
198*4882a593Smuzhiyun		reg-names = "control", "domain";
199*4882a593Smuzhiyun		domain-id = <1>;
200*4882a593Smuzhiyun	};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun	clktetbtrc: clktetbtrc@2350018 {
203*4882a593Smuzhiyun		#clock-cells = <0>;
204*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
205*4882a593Smuzhiyun		clocks = <&chipclk13>;
206*4882a593Smuzhiyun		clock-output-names = "tetb-trc";
207*4882a593Smuzhiyun		reg = <0x02350018 0xb00>, <0x02350004 0x400>;
208*4882a593Smuzhiyun		reg-names = "control", "domain";
209*4882a593Smuzhiyun		domain-id = <1>;
210*4882a593Smuzhiyun	};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun	clkpa: clkpa@235001c {
213*4882a593Smuzhiyun		#clock-cells = <0>;
214*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
215*4882a593Smuzhiyun		clocks = <&paclk13>;
216*4882a593Smuzhiyun		clock-output-names = "pa";
217*4882a593Smuzhiyun		reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
218*4882a593Smuzhiyun		reg-names = "control", "domain";
219*4882a593Smuzhiyun		domain-id = <2>;
220*4882a593Smuzhiyun	};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun	clkcpgmac: clkcpgmac@2350020 {
223*4882a593Smuzhiyun		#clock-cells = <0>;
224*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
225*4882a593Smuzhiyun		clocks = <&clkpa>;
226*4882a593Smuzhiyun		clock-output-names = "cpgmac";
227*4882a593Smuzhiyun		reg = <0x02350020 0xb00>, <0x02350008 0x400>;
228*4882a593Smuzhiyun		reg-names = "control", "domain";
229*4882a593Smuzhiyun		domain-id = <2>;
230*4882a593Smuzhiyun	};
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun	clksa: clksa@2350024 {
233*4882a593Smuzhiyun		#clock-cells = <0>;
234*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
235*4882a593Smuzhiyun		clocks = <&clkpa>;
236*4882a593Smuzhiyun		clock-output-names = "sa";
237*4882a593Smuzhiyun		reg = <0x02350024 0xb00>, <0x02350008 0x400>;
238*4882a593Smuzhiyun		reg-names = "control", "domain";
239*4882a593Smuzhiyun		domain-id = <2>;
240*4882a593Smuzhiyun	};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun	clkpcie: clkpcie@2350028 {
243*4882a593Smuzhiyun		#clock-cells = <0>;
244*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
245*4882a593Smuzhiyun		clocks = <&chipclk12>;
246*4882a593Smuzhiyun		clock-output-names = "pcie";
247*4882a593Smuzhiyun		reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
248*4882a593Smuzhiyun		reg-names = "control", "domain";
249*4882a593Smuzhiyun		domain-id = <3>;
250*4882a593Smuzhiyun	};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun	clksr: clksr@2350034 {
253*4882a593Smuzhiyun		#clock-cells = <0>;
254*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
255*4882a593Smuzhiyun		clocks = <&chipclk1rstiso112>;
256*4882a593Smuzhiyun		clock-output-names = "sr";
257*4882a593Smuzhiyun		reg = <0x02350034 0xb00>, <0x02350018 0x400>;
258*4882a593Smuzhiyun		reg-names = "control", "domain";
259*4882a593Smuzhiyun		domain-id = <6>;
260*4882a593Smuzhiyun	};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun	clkgem0: clkgem0@235003c {
263*4882a593Smuzhiyun		#clock-cells = <0>;
264*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
265*4882a593Smuzhiyun		clocks = <&chipclk1>;
266*4882a593Smuzhiyun		clock-output-names = "gem0";
267*4882a593Smuzhiyun		reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
268*4882a593Smuzhiyun		reg-names = "control", "domain";
269*4882a593Smuzhiyun		domain-id = <8>;
270*4882a593Smuzhiyun	};
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun	clkddr30: clkddr30@235005c {
273*4882a593Smuzhiyun		#clock-cells = <0>;
274*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
275*4882a593Smuzhiyun		clocks = <&chipclk12>;
276*4882a593Smuzhiyun		clock-output-names = "ddr3-0";
277*4882a593Smuzhiyun		reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
278*4882a593Smuzhiyun		reg-names = "control", "domain";
279*4882a593Smuzhiyun		domain-id = <16>;
280*4882a593Smuzhiyun	};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun	clkwdtimer0: clkwdtimer0@2350000 {
283*4882a593Smuzhiyun		#clock-cells = <0>;
284*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
285*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
286*4882a593Smuzhiyun		clock-output-names = "timer0";
287*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
288*4882a593Smuzhiyun		reg-names = "control", "domain";
289*4882a593Smuzhiyun		domain-id = <0>;
290*4882a593Smuzhiyun	};
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun	clkwdtimer1: clkwdtimer1@2350000 {
293*4882a593Smuzhiyun		#clock-cells = <0>;
294*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
295*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
296*4882a593Smuzhiyun		clock-output-names = "timer1";
297*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
298*4882a593Smuzhiyun		reg-names = "control", "domain";
299*4882a593Smuzhiyun		domain-id = <0>;
300*4882a593Smuzhiyun	};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun	clkwdtimer2: clkwdtimer2@2350000 {
303*4882a593Smuzhiyun		#clock-cells = <0>;
304*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
305*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
306*4882a593Smuzhiyun		clock-output-names = "timer2";
307*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
308*4882a593Smuzhiyun		reg-names = "control", "domain";
309*4882a593Smuzhiyun		domain-id = <0>;
310*4882a593Smuzhiyun	};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun	clkwdtimer3: clkwdtimer3@2350000 {
313*4882a593Smuzhiyun		#clock-cells = <0>;
314*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
315*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
316*4882a593Smuzhiyun		clock-output-names = "timer3";
317*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
318*4882a593Smuzhiyun		reg-names = "control", "domain";
319*4882a593Smuzhiyun		domain-id = <0>;
320*4882a593Smuzhiyun	};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun	clktimer15: clktimer15@2350000 {
323*4882a593Smuzhiyun		#clock-cells = <0>;
324*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
325*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
326*4882a593Smuzhiyun		clock-output-names = "timer15";
327*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
328*4882a593Smuzhiyun		reg-names = "control", "domain";
329*4882a593Smuzhiyun		domain-id = <0>;
330*4882a593Smuzhiyun	};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun	clkuart0: clkuart0@2350000 {
333*4882a593Smuzhiyun		#clock-cells = <0>;
334*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
335*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
336*4882a593Smuzhiyun		clock-output-names = "uart0";
337*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
338*4882a593Smuzhiyun		reg-names = "control", "domain";
339*4882a593Smuzhiyun		domain-id = <0>;
340*4882a593Smuzhiyun	};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun	clkuart1: clkuart1@2350000 {
343*4882a593Smuzhiyun		#clock-cells = <0>;
344*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
345*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
346*4882a593Smuzhiyun		clock-output-names = "uart1";
347*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
348*4882a593Smuzhiyun		reg-names = "control", "domain";
349*4882a593Smuzhiyun		domain-id = <0>;
350*4882a593Smuzhiyun	};
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun	clkaemif: clkaemif@2350000 {
353*4882a593Smuzhiyun		#clock-cells = <0>;
354*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
355*4882a593Smuzhiyun		clocks = <&clkaemifspi>;
356*4882a593Smuzhiyun		clock-output-names = "aemif";
357*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
358*4882a593Smuzhiyun		reg-names = "control", "domain";
359*4882a593Smuzhiyun		domain-id = <0>;
360*4882a593Smuzhiyun	};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun	clkusim: clkusim@2350000 {
363*4882a593Smuzhiyun		#clock-cells = <0>;
364*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
365*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
366*4882a593Smuzhiyun		clock-output-names = "usim";
367*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
368*4882a593Smuzhiyun		reg-names = "control", "domain";
369*4882a593Smuzhiyun		domain-id = <0>;
370*4882a593Smuzhiyun	};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun	clki2c: clki2c@2350000 {
373*4882a593Smuzhiyun		#clock-cells = <0>;
374*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
375*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
376*4882a593Smuzhiyun		clock-output-names = "i2c";
377*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
378*4882a593Smuzhiyun		reg-names = "control", "domain";
379*4882a593Smuzhiyun		domain-id = <0>;
380*4882a593Smuzhiyun	};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun	clkspi: clkspi@2350000 {
383*4882a593Smuzhiyun		#clock-cells = <0>;
384*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
385*4882a593Smuzhiyun		clocks = <&clkaemifspi>;
386*4882a593Smuzhiyun		clock-output-names = "spi";
387*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
388*4882a593Smuzhiyun		reg-names = "control", "domain";
389*4882a593Smuzhiyun		domain-id = <0>;
390*4882a593Smuzhiyun	};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun	clkgpio: clkgpio@2350000 {
393*4882a593Smuzhiyun		#clock-cells = <0>;
394*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
395*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
396*4882a593Smuzhiyun		clock-output-names = "gpio";
397*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
398*4882a593Smuzhiyun		reg-names = "control", "domain";
399*4882a593Smuzhiyun		domain-id = <0>;
400*4882a593Smuzhiyun	};
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun	clkkeymgr: clkkeymgr@2350000 {
403*4882a593Smuzhiyun		#clock-cells = <0>;
404*4882a593Smuzhiyun		compatible = "ti,keystone,psc-clock";
405*4882a593Smuzhiyun		clocks = <&clkmodrst0>;
406*4882a593Smuzhiyun		clock-output-names = "keymgr";
407*4882a593Smuzhiyun		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
408*4882a593Smuzhiyun		reg-names = "control", "domain";
409*4882a593Smuzhiyun		domain-id = <0>;
410*4882a593Smuzhiyun	};
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun	/*
413*4882a593Smuzhiyun	 * Below are set of fixed, input clocks definitions,
414*4882a593Smuzhiyun	 * for which real frequencies have to be defined in board files.
415*4882a593Smuzhiyun	 * Those clocks can be used as reference clocks for some HW modules
416*4882a593Smuzhiyun	 * (as cpts, for example) by configuring corresponding clock muxes.
417*4882a593Smuzhiyun	 */
418*4882a593Smuzhiyun	timi0: timi0 {
419*4882a593Smuzhiyun		#clock-cells = <0>;
420*4882a593Smuzhiyun		compatible = "fixed-clock";
421*4882a593Smuzhiyun		clock-frequency = <0>;
422*4882a593Smuzhiyun		clock-output-names = "timi0";
423*4882a593Smuzhiyun	};
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun	timi1: timi1 {
426*4882a593Smuzhiyun		#clock-cells = <0>;
427*4882a593Smuzhiyun		compatible = "fixed-clock";
428*4882a593Smuzhiyun		clock-frequency = <0>;
429*4882a593Smuzhiyun		clock-output-names = "timi1";
430*4882a593Smuzhiyun	};
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun	tsrefclk: tsrefclk {
433*4882a593Smuzhiyun		#clock-cells = <0>;
434*4882a593Smuzhiyun		compatible = "fixed-clock";
435*4882a593Smuzhiyun		clock-frequency = <0>;
436*4882a593Smuzhiyun		clock-output-names = "tsrefclk";
437*4882a593Smuzhiyun	};
438*4882a593Smuzhiyun};
439