| /OK3568_Linux_fs/kernel/drivers/clk/ti/ |
| H A D | clockdomain.c | 51 clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm()
57 __func__, clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm()
63 __func__, clk_hw_get_name(hw), clk->clkdm_name, ret); in omap2_clkops_enable_clkdm()
85 clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm()
91 __func__, clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm()
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| H A D | dpll3xxx.c | 69 clk_name = clk_hw_get_name(&clk->hw); in _omap3_wait_dpll_status()
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
193 clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_bypass()
223 pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_stop()
452 __func__, clk_hw_get_name(hw), in omap3_noncore_dpll_enable()
589 clk_hw_get_name(hw), rate); in omap3_noncore_dpll_set_rate()
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| H A D | clkt_dflt.c | 114 idlest_val, clk_hw_get_name(&clk->hw)); in _omap2_module_wait_ready()
221 __func__, clk_hw_get_name(hw), in omap2_dflt_clk_enable()
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| /OK3568_Linux_fs/kernel/drivers/clk/ux500/ |
| H A D | clk-prcmu.c | 45 clk_hw_get_name(hw)); in clk_prcmu_unprepare()
103 (char *)clk_hw_get_name(hw), in clk_prcmu_opp_prepare()
107 __func__, clk_hw_get_name(hw)); in clk_prcmu_opp_prepare()
116 (char *)clk_hw_get_name(hw)); in clk_prcmu_opp_prepare()
131 clk_hw_get_name(hw)); in clk_prcmu_opp_unprepare()
137 (char *)clk_hw_get_name(hw)); in clk_prcmu_opp_unprepare()
153 __func__, clk_hw_get_name(hw)); in clk_prcmu_opp_volt_prepare()
176 clk_hw_get_name(hw)); in clk_prcmu_opp_volt_unprepare()
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| /OK3568_Linux_fs/kernel/drivers/clk/zynqmp/ |
| H A D | pll.c | 52 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_get_mode()
73 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_mode()
135 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_recalc_rate()
172 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_rate()
218 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_is_enabled()
242 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_enable()
270 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_disable()
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| H A D | clk-gate-zynqmp.c | 37 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_enable()
57 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_disable()
77 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_is_enabled()
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| H A D | clk-mux-zynqmp.c | 46 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_mux_get_parent()
70 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_mux_set_parent()
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| H A D | divider.c | 82 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_recalc_rate()
168 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_round_rate()
225 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_set_rate()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 158 cru_dbg("%s rate: %ld\n", clk_hw_get_name(hw), rate); in clk_virtual_round_rate()
178 cru_dbg("%s index: %d\n", clk_hw_get_name(hw), vop2_clk->parent_index); in vop2_mux_get_parent()
188 cru_dbg("%s index: %d\n", clk_hw_get_name(hw), index); in vop2_mux_set_parent()
196 clk_hw_get_name(hw), req->rate, req->min_rate, req->max_rate); in vop2_clk_mux_determine_rate()
229 cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, parent_rate); in vop2_clk_div_recalc_rate()
249 cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, *prate); in vop2_clk_div_round_rate()
263 clk_hw_get_name(hw), parent_rate, rate, div_val); in vop2_clk_div_set_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/ |
| H A D | clk-xgene.c | 64 pr_debug("%s pll %s\n", clk_hw_get_name(hw), in xgene_clk_pll_is_enabled()
112 clk_hw_get_name(hw), fvco / nout, parent_rate, in xgene_clk_pll_recalc_rate()
454 pr_debug("%s clock enabled\n", clk_hw_get_name(hw)); in xgene_clk_enable()
462 clk_hw_get_name(hw), in xgene_clk_enable()
473 clk_hw_get_name(hw), in xgene_clk_enable()
494 pr_debug("%s clock disabled\n", clk_hw_get_name(hw)); in xgene_clk_disable()
520 pr_debug("%s clock checking\n", clk_hw_get_name(hw)); in xgene_clk_is_enabled()
523 pr_debug("%s clock is %s\n", clk_hw_get_name(hw), in xgene_clk_is_enabled()
546 clk_hw_get_name(hw), in xgene_clk_recalc_rate()
552 clk_hw_get_name(hw), parent_rate, parent_rate); in xgene_clk_recalc_rate()
[all …]
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| H A D | clk-versaclock5.c | 926 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
942 parent_names[0] = clk_hw_get_name(&vc5->clk_mul); in vc5_probe()
944 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
958 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd); in vc5_probe()
977 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw); in vc5_probe()
995 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1008 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw); in vc5_probe()
1010 parent_names[1] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1013 clk_hw_get_name(&vc5->clk_out[n - 1].hw); in vc5_probe()
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| H A D | clk-si5351.c | 438 __func__, clk_hw_get_name(hw), in si5351_pll_recalc_rate()
496 __func__, clk_hw_get_name(hw), a, b, c, in si5351_pll_round_rate()
525 __func__, clk_hw_get_name(hw), in si5351_pll_set_rate()
636 __func__, clk_hw_get_name(hw), in si5351_msynth_recalc_rate()
749 __func__, clk_hw_get_name(hw), a, b, c, divby4, in si5351_msynth_round_rate()
781 __func__, clk_hw_get_name(hw), in si5351_msynth_set_rate()
917 __func__, clk_hw_get_name(&drvdata->clkout[num].hw), in _si5351_clkout_reset_pll()
1075 __func__, clk_hw_get_name(hw), (1 << rdiv), in si5351_clkout_round_rate()
1126 __func__, clk_hw_get_name(hw), (1 << rdiv), in si5351_clkout_set_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/ |
| H A D | ccu_frac.c | 67 pr_debug("%s: Read fractional\n", clk_hw_get_name(&common->hw)); in ccu_frac_helper_read_rate()
73 clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]); in ccu_frac_helper_read_rate()
78 clk_hw_get_name(&common->hw), reg, cf->select); in ccu_frac_helper_read_rate()
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| H A D | ccu_sdm.c | 114 clk_hw_get_name(&common->hw)); in ccu_sdm_helper_read_rate()
120 clk_hw_get_name(&common->hw)); in ccu_sdm_helper_read_rate()
125 clk_hw_get_name(&common->hw), reg); in ccu_sdm_helper_read_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/st/ |
| H A D | clkgen-fsyn.c | 280 clk_hw_get_name(hw), __func__); in quadfs_pll_fs660c32_recalc_rate()
328 __func__, clk_hw_get_name(hw), in quadfs_pll_fs660c32_round_rate()
353 __func__, clk_hw_get_name(hw), in quadfs_pll_fs660c32_set_rate()
511 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); in quadfs_fsynth_enable()
536 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); in quadfs_fsynth_disable()
553 __func__, clk_hw_get_name(hw), nsb); in quadfs_fsynth_is_enabled()
747 clk_hw_get_name(hw), __func__); in quadfs_recalc_rate()
750 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); in quadfs_recalc_rate()
763 __func__, clk_hw_get_name(hw), in quadfs_round_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/qcom/ |
| H A D | clk-regmap-mux-div.c | 27 const char *name = clk_hw_get_name(&md->clkr.hw); in mux_div_set_src_div()
63 const char *name = clk_hw_get_name(&md->clkr.hw); in mux_div_get_src_div()
166 const char *name = clk_hw_get_name(hw); in mux_div_get_parent()
208 const char *name = clk_hw_get_name(hw); in mux_div_recalc_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/berlin/ |
| H A D | berlin2-pll.c | 53 pr_warn("%s has zero rfdiv\n", clk_hw_get_name(hw)); in berlin2_pll_recalc_rate()
62 clk_hw_get_name(hw), vcodivsel); in berlin2_pll_recalc_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/samsung/ |
| H A D | clk-pll.c | 215 drate, clk_hw_get_name(hw)); in samsung_pll35xx_set_rate()
327 drate, clk_hw_get_name(hw)); in samsung_pll36xx_set_rate()
446 drate, clk_hw_get_name(hw)); in samsung_pll45xx_set_rate()
498 __func__, clk_hw_get_name(hw)); in samsung_pll45xx_set_rate()
597 drate, clk_hw_get_name(hw)); in samsung_pll46xx_set_rate()
657 __func__, clk_hw_get_name(hw)); in samsung_pll46xx_set_rate()
815 drate, clk_hw_get_name(hw)); in samsung_s3c2410_pll_set_rate()
1011 drate, clk_hw_get_name(hw)); in samsung_pll2550xx_set_rate()
1111 drate, clk_hw_get_name(hw)); in samsung_pll2650x_set_rate()
1205 drate, clk_hw_get_name(hw)); in samsung_pll2650xx_set_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/imx/ |
| H A D | clk-scu.c | 163 clk_hw_get_name(hw), ret); in clk_scu_recalc_rate()
253 clk_hw_get_name(hw), ret); in clk_scu_get_parent()
325 pr_warn("%s: clk unprepare failed %d\n", clk_hw_get_name(hw), in clk_scu_unprepare()
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/ |
| H A D | clk-regmap-pll.c | 243 clk_hw_get_name(hw), *prate, drate, rate); in clk_regmap_pll_round_rate()
264 clk_hw_get_name(hw), drate, bypass); in clk_regmap_pll_set_rate()
301 dev_err(pll->dev, "%s is not lock\n", clk_hw_get_name(hw)); in clk_regmap_pll_prepare()
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| /OK3568_Linux_fs/kernel/drivers/clk/socfpga/ |
| H A D | clk-gate.c | 33 const char *name = clk_hw_get_name(hwclk); in socfpga_clk_get_parent()
59 const char *name = clk_hw_get_name(hwclk); in socfpga_clk_set_parent()
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| /OK3568_Linux_fs/kernel/drivers/clk/nxp/ |
| H A D | clk-lpc32xx.c | 517 clk_hw_get_name(hw), in clk_pll_recalc_rate()
526 clk_hw_get_name(hw), in clk_pll_recalc_rate()
590 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate); in clk_hclk_pll_round_rate()
619 clk_hw_get_name(hw), rate); in clk_hclk_pll_round_rate()
637 clk_hw_get_name(hw), rate, m, n, p); in clk_hclk_pll_round_rate()
640 clk_hw_get_name(hw), rate, m, n, p, o); in clk_hclk_pll_round_rate()
652 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate); in clk_usb_pll_round_rate()
802 pr_debug("%s: 0x%x\n", clk_hw_get_name(hw), clk->enable); in clk_usb_enable()
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| /OK3568_Linux_fs/kernel/drivers/clk/microchip/ |
| H A D | clk-core.c | 423 __func__, clk_hw_get_name(hw), req->rate); in roclk_determine_rate()
428 clk_hw_get_name(hw), req->rate, in roclk_determine_rate()
429 clk_hw_get_name(best_parent_clk), best_parent_rate, in roclk_determine_rate()
455 pr_err("%s: poll failed, clk active\n", clk_hw_get_name(hw)); in roclk_set_parent()
878 clk_hw_get_name(hw), nosc, cosc); in sclk_set_parent()
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| /OK3568_Linux_fs/kernel/drivers/clk/baikal-t1/ |
| H A D | ccu-pll.c | 113 pr_err("Can't enable '%s' with no parent", clk_hw_get_name(hw)); in ccu_pll_enable()
127 pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw)); in ccu_pll_enable()
267 pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw)); in ccu_pll_set_rate_reset()
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| /OK3568_Linux_fs/kernel/drivers/clk/sirf/ |
| H A D | clk-common.c | 300 const char *name = clk_hw_get_name(hw); in dmn_clk_get_parent()
315 const char *name = clk_hw_get_name(hw); in dmn_clk_set_parent()
358 const char *name = clk_hw_get_name(hw); in dmn_clk_round_rate()
381 const char *name = clk_hw_get_name(hw); in dmn_clk_set_rate()
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