1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2014 Marvell Technology Group Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Alexandre Belloni <alexandre.belloni@free-electrons.com>
6*4882a593Smuzhiyun * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/clk-provider.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <asm/div64.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "berlin2-div.h"
17*4882a593Smuzhiyun #include "berlin2-pll.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct berlin2_pll {
20*4882a593Smuzhiyun struct clk_hw hw;
21*4882a593Smuzhiyun void __iomem *base;
22*4882a593Smuzhiyun struct berlin2_pll_map map;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define to_berlin2_pll(hw) container_of(hw, struct berlin2_pll, hw)
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define SPLL_CTRL0 0x00
28*4882a593Smuzhiyun #define SPLL_CTRL1 0x04
29*4882a593Smuzhiyun #define SPLL_CTRL2 0x08
30*4882a593Smuzhiyun #define SPLL_CTRL3 0x0c
31*4882a593Smuzhiyun #define SPLL_CTRL4 0x10
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define FBDIV_MASK 0x1ff
34*4882a593Smuzhiyun #define RFDIV_MASK 0x1f
35*4882a593Smuzhiyun #define DIVSEL_MASK 0xf
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * The output frequency formula for the pll is:
39*4882a593Smuzhiyun * clkout = fbdiv / refdiv * parent / vcodiv
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun static unsigned long
berlin2_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)42*4882a593Smuzhiyun berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct berlin2_pll *pll = to_berlin2_pll(hw);
45*4882a593Smuzhiyun struct berlin2_pll_map *map = &pll->map;
46*4882a593Smuzhiyun u32 val, fbdiv, rfdiv, vcodivsel, vcodiv;
47*4882a593Smuzhiyun u64 rate = parent_rate;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun val = readl_relaxed(pll->base + SPLL_CTRL0);
50*4882a593Smuzhiyun fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK;
51*4882a593Smuzhiyun rfdiv = (val >> map->rfdiv_shift) & RFDIV_MASK;
52*4882a593Smuzhiyun if (rfdiv == 0) {
53*4882a593Smuzhiyun pr_warn("%s has zero rfdiv\n", clk_hw_get_name(hw));
54*4882a593Smuzhiyun rfdiv = 1;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun val = readl_relaxed(pll->base + SPLL_CTRL1);
58*4882a593Smuzhiyun vcodivsel = (val >> map->divsel_shift) & DIVSEL_MASK;
59*4882a593Smuzhiyun vcodiv = map->vcodiv[vcodivsel];
60*4882a593Smuzhiyun if (vcodiv == 0) {
61*4882a593Smuzhiyun pr_warn("%s has zero vcodiv (index %d)\n",
62*4882a593Smuzhiyun clk_hw_get_name(hw), vcodivsel);
63*4882a593Smuzhiyun vcodiv = 1;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun rate *= fbdiv * map->mult;
67*4882a593Smuzhiyun do_div(rate, rfdiv * vcodiv);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return (unsigned long)rate;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static const struct clk_ops berlin2_pll_ops = {
73*4882a593Smuzhiyun .recalc_rate = berlin2_pll_recalc_rate,
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun int __init
berlin2_pll_register(const struct berlin2_pll_map * map,void __iomem * base,const char * name,const char * parent_name,unsigned long flags)77*4882a593Smuzhiyun berlin2_pll_register(const struct berlin2_pll_map *map,
78*4882a593Smuzhiyun void __iomem *base, const char *name,
79*4882a593Smuzhiyun const char *parent_name, unsigned long flags)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun struct clk_init_data init;
82*4882a593Smuzhiyun struct berlin2_pll *pll;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun pll = kzalloc(sizeof(*pll), GFP_KERNEL);
85*4882a593Smuzhiyun if (!pll)
86*4882a593Smuzhiyun return -ENOMEM;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* copy pll_map to allow __initconst */
89*4882a593Smuzhiyun memcpy(&pll->map, map, sizeof(*map));
90*4882a593Smuzhiyun pll->base = base;
91*4882a593Smuzhiyun pll->hw.init = &init;
92*4882a593Smuzhiyun init.name = name;
93*4882a593Smuzhiyun init.ops = &berlin2_pll_ops;
94*4882a593Smuzhiyun init.parent_names = &parent_name;
95*4882a593Smuzhiyun init.num_parents = 1;
96*4882a593Smuzhiyun init.flags = flags;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return clk_hw_register(NULL, &pll->hw);
99*4882a593Smuzhiyun }
100