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Searched refs:VPLL (Results 1 – 21 of 21) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/
H A Dclock.c145 } else if (pllreg == VPLL) { in exynos_get_pll_clk()
203 case VPLL: in exynos4_get_pll_clk()
233 case VPLL: in exynos4x12_get_pll_clk()
264 case VPLL: in exynos5_get_pll_clk()
322 case VPLL: in exynos542x_get_pll_clk()
444 sclk = exynos5_get_pll_clk(VPLL); in exynos5_get_periph_rate()
657 sclk = get_pll_clk(VPLL); in exynos4_get_pwm_clk()
718 sclk = get_pll_clk(VPLL); in exynos4_get_uart_clk()
764 sclk = get_pll_clk(VPLL); in exynos4x12_get_uart_clk()
800 sclk = get_pll_clk(VPLL); in exynos4_get_mmc_clk()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dclk.h16 #define VPLL 4 macro
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3562.c49 [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3562_PLL_CON(32),
1145 rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], in rk3562_vop_get_rate()
1146 priv->cru, VPLL); in rk3562_vop_get_rate()
1205 rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru, in rk3562_vop_set_rate()
1206 VPLL, div * rate); in rk3562_vop_set_rate()
1372 rate = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], priv->cru, in rk3562_clk_get_rate()
1373 VPLL); in rk3562_clk_get_rate()
1500 ret = rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru, in rk3562_clk_set_rate()
1501 VPLL, rate); in rk3562_clk_set_rate()
1502 priv->vpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], in rk3562_clk_set_rate()
[all …]
H A Dclk_rk3568.c78 [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3568_PLL_CON(40),
1799 parent = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], in rk3568_dclk_vop_get_clk()
1800 priv->cru, VPLL); in rk3568_dclk_vop_get_clk()
1850 rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], in rk3568_dclk_vop_set_clk()
1851 priv->cru, VPLL, div * rate); in rk3568_dclk_vop_set_clk()
2532 rate = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], priv->cru, in rk3568_clk_get_rate()
2533 VPLL); in rk3568_clk_get_rate()
2719 ret = rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], priv->cru, in rk3568_clk_set_rate()
2720 VPLL, rate); in rk3568_clk_set_rate()
2721 priv->vpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], in rk3568_clk_set_rate()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/
H A Dclk.h15 #define VPLL 4 macro
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3588-vehicle-serdes-display-v21.dtsi651 022d 0023 //VPLL=75MHZS
654 //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M
867 022d 0023 //VPLL=75MHZS
870 //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M
1300 022d 0023 //VPLL=75MHZS
1303 //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M
1715 022d 0023 //VPLL=75MHZS
1718 //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h16 #define VPLL 4 macro
/OK3568_Linux_fs/kernel/drivers/regulator/
H A Dcpcap-regulator.c377 CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
453 CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
H A Dmc13892-regulator.c273 MC13892_DEFINE_REGU(VPLL, vpll, REGULATORMODE0, REGULATORSETTING0,
H A Dtps65910-regulator.c284 EXT_CONTROL_REG_BITS(VPLL, 0, 6),
/OK3568_Linux_fs/u-boot/arch/arm/mach-s5pc1xx/
H A Dclock.c94 case VPLL: in s5pc110_get_pll_clk()
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx53-qsrb.dts96 regulator-name = "VPLL";
H A Dmotorola-cpcap-mapphone.dtsi208 vpll: VPLL {
H A Domap3-n900.dts451 regulator-name = "VPLL";
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/video/
H A Dexynos-fb.txt55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3562.h26 VPLL, enumerator
H A Dcru_rk3568.h26 VPLL, enumerator
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Dmc13xxx.txt95 vpll : regulator VPLL (register 32, bit 15)
H A Dtps65910.txt39 vcc5-supply: VPLL and VDAC input.
/OK3568_Linux_fs/u-boot/board/samsung/goni/
H A Dlowlevel_init.S334 ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
/OK3568_Linux_fs/kernel/drivers/clk/ingenic/
H A Djz4780-cgu.c313 .pll = DEF_PLL(VPLL),