clk/rockchip/clk_rk3562.c

49 	[VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3562_PLL_CON(32),
1145 				rockchip_pll_get_rate(&rk3562_pll_clks[VPLL],  in rk3562_vop_get_rate()
1146 						      priv->cru, VPLL);  in rk3562_vop_get_rate()
1205 		rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru,  in rk3562_vop_set_rate()
1206 				      VPLL, div * rate);  in rk3562_vop_set_rate()
1372 		rate = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], priv->cru,  in rk3562_clk_get_rate()
1373 					     VPLL);  in rk3562_clk_get_rate()
1500 		ret = rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru,  in rk3562_clk_set_rate()
1501 					    VPLL, rate);  in rk3562_clk_set_rate()
1502 		priv->vpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL],  in rk3562_clk_set_rate()
1503 						      priv->cru, VPLL);  in rk3562_clk_set_rate()