1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * tps65910.c -- TI tps65910
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2010 Texas Instruments Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Graeme Gregory <gg@slimlogic.co.uk>
8*4882a593Smuzhiyun * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/err.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/regulator/driver.h>
18*4882a593Smuzhiyun #include <linux/regulator/machine.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/gpio.h>
21*4882a593Smuzhiyun #include <linux/mfd/tps65910.h>
22*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define TPS65910_SUPPLY_STATE_ENABLED 0x1
25*4882a593Smuzhiyun #define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \
26*4882a593Smuzhiyun TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \
27*4882a593Smuzhiyun TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \
28*4882a593Smuzhiyun TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* supported VIO voltages in microvolts */
31*4882a593Smuzhiyun static const unsigned int VIO_VSEL_table[] = {
32*4882a593Smuzhiyun 1500000, 1800000, 2500000, 3300000,
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* VSEL tables for TPS65910 specific LDOs and dcdc's */
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* supported VRTC voltages in microvolts */
38*4882a593Smuzhiyun static const unsigned int VRTC_VSEL_table[] = {
39*4882a593Smuzhiyun 1800000,
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* supported VDD3 voltages in microvolts */
43*4882a593Smuzhiyun static const unsigned int VDD3_VSEL_table[] = {
44*4882a593Smuzhiyun 5000000,
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* supported VDIG1 voltages in microvolts */
48*4882a593Smuzhiyun static const unsigned int VDIG1_VSEL_table[] = {
49*4882a593Smuzhiyun 1200000, 1500000, 1800000, 2700000,
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* supported VDIG2 voltages in microvolts */
53*4882a593Smuzhiyun static const unsigned int VDIG2_VSEL_table[] = {
54*4882a593Smuzhiyun 1000000, 1100000, 1200000, 1800000,
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* supported VPLL voltages in microvolts */
58*4882a593Smuzhiyun static const unsigned int VPLL_VSEL_table[] = {
59*4882a593Smuzhiyun 1000000, 1100000, 1800000, 2500000,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* supported VDAC voltages in microvolts */
63*4882a593Smuzhiyun static const unsigned int VDAC_VSEL_table[] = {
64*4882a593Smuzhiyun 1800000, 2600000, 2800000, 2850000,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* supported VAUX1 voltages in microvolts */
68*4882a593Smuzhiyun static const unsigned int VAUX1_VSEL_table[] = {
69*4882a593Smuzhiyun 1800000, 2500000, 2800000, 2850000,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* supported VAUX2 voltages in microvolts */
73*4882a593Smuzhiyun static const unsigned int VAUX2_VSEL_table[] = {
74*4882a593Smuzhiyun 1800000, 2800000, 2900000, 3300000,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* supported VAUX33 voltages in microvolts */
78*4882a593Smuzhiyun static const unsigned int VAUX33_VSEL_table[] = {
79*4882a593Smuzhiyun 1800000, 2000000, 2800000, 3300000,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* supported VMMC voltages in microvolts */
83*4882a593Smuzhiyun static const unsigned int VMMC_VSEL_table[] = {
84*4882a593Smuzhiyun 1800000, 2800000, 3000000, 3300000,
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* supported BBCH voltages in microvolts */
88*4882a593Smuzhiyun static const unsigned int VBB_VSEL_table[] = {
89*4882a593Smuzhiyun 3000000, 2520000, 3150000, 5000000,
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun struct tps_info {
93*4882a593Smuzhiyun const char *name;
94*4882a593Smuzhiyun const char *vin_name;
95*4882a593Smuzhiyun u8 n_voltages;
96*4882a593Smuzhiyun const unsigned int *voltage_table;
97*4882a593Smuzhiyun int enable_time_us;
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static struct tps_info tps65910_regs[] = {
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun .name = "vrtc",
103*4882a593Smuzhiyun .vin_name = "vcc7",
104*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VRTC_VSEL_table),
105*4882a593Smuzhiyun .voltage_table = VRTC_VSEL_table,
106*4882a593Smuzhiyun .enable_time_us = 2200,
107*4882a593Smuzhiyun },
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun .name = "vio",
110*4882a593Smuzhiyun .vin_name = "vccio",
111*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
112*4882a593Smuzhiyun .voltage_table = VIO_VSEL_table,
113*4882a593Smuzhiyun .enable_time_us = 350,
114*4882a593Smuzhiyun },
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun .name = "vdd1",
117*4882a593Smuzhiyun .vin_name = "vcc1",
118*4882a593Smuzhiyun .enable_time_us = 350,
119*4882a593Smuzhiyun },
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun .name = "vdd2",
122*4882a593Smuzhiyun .vin_name = "vcc2",
123*4882a593Smuzhiyun .enable_time_us = 350,
124*4882a593Smuzhiyun },
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun .name = "vdd3",
127*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VDD3_VSEL_table),
128*4882a593Smuzhiyun .voltage_table = VDD3_VSEL_table,
129*4882a593Smuzhiyun .enable_time_us = 200,
130*4882a593Smuzhiyun },
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun .name = "vdig1",
133*4882a593Smuzhiyun .vin_name = "vcc6",
134*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table),
135*4882a593Smuzhiyun .voltage_table = VDIG1_VSEL_table,
136*4882a593Smuzhiyun .enable_time_us = 100,
137*4882a593Smuzhiyun },
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun .name = "vdig2",
140*4882a593Smuzhiyun .vin_name = "vcc6",
141*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table),
142*4882a593Smuzhiyun .voltage_table = VDIG2_VSEL_table,
143*4882a593Smuzhiyun .enable_time_us = 100,
144*4882a593Smuzhiyun },
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun .name = "vpll",
147*4882a593Smuzhiyun .vin_name = "vcc5",
148*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VPLL_VSEL_table),
149*4882a593Smuzhiyun .voltage_table = VPLL_VSEL_table,
150*4882a593Smuzhiyun .enable_time_us = 100,
151*4882a593Smuzhiyun },
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun .name = "vdac",
154*4882a593Smuzhiyun .vin_name = "vcc5",
155*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VDAC_VSEL_table),
156*4882a593Smuzhiyun .voltage_table = VDAC_VSEL_table,
157*4882a593Smuzhiyun .enable_time_us = 100,
158*4882a593Smuzhiyun },
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun .name = "vaux1",
161*4882a593Smuzhiyun .vin_name = "vcc4",
162*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table),
163*4882a593Smuzhiyun .voltage_table = VAUX1_VSEL_table,
164*4882a593Smuzhiyun .enable_time_us = 100,
165*4882a593Smuzhiyun },
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun .name = "vaux2",
168*4882a593Smuzhiyun .vin_name = "vcc4",
169*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table),
170*4882a593Smuzhiyun .voltage_table = VAUX2_VSEL_table,
171*4882a593Smuzhiyun .enable_time_us = 100,
172*4882a593Smuzhiyun },
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun .name = "vaux33",
175*4882a593Smuzhiyun .vin_name = "vcc3",
176*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table),
177*4882a593Smuzhiyun .voltage_table = VAUX33_VSEL_table,
178*4882a593Smuzhiyun .enable_time_us = 100,
179*4882a593Smuzhiyun },
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun .name = "vmmc",
182*4882a593Smuzhiyun .vin_name = "vcc3",
183*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VMMC_VSEL_table),
184*4882a593Smuzhiyun .voltage_table = VMMC_VSEL_table,
185*4882a593Smuzhiyun .enable_time_us = 100,
186*4882a593Smuzhiyun },
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun .name = "vbb",
189*4882a593Smuzhiyun .vin_name = "vcc7",
190*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VBB_VSEL_table),
191*4882a593Smuzhiyun .voltage_table = VBB_VSEL_table,
192*4882a593Smuzhiyun },
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun static struct tps_info tps65911_regs[] = {
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun .name = "vrtc",
198*4882a593Smuzhiyun .vin_name = "vcc7",
199*4882a593Smuzhiyun .enable_time_us = 2200,
200*4882a593Smuzhiyun },
201*4882a593Smuzhiyun {
202*4882a593Smuzhiyun .name = "vio",
203*4882a593Smuzhiyun .vin_name = "vccio",
204*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
205*4882a593Smuzhiyun .voltage_table = VIO_VSEL_table,
206*4882a593Smuzhiyun .enable_time_us = 350,
207*4882a593Smuzhiyun },
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun .name = "vdd1",
210*4882a593Smuzhiyun .vin_name = "vcc1",
211*4882a593Smuzhiyun .n_voltages = 0x4C,
212*4882a593Smuzhiyun .enable_time_us = 350,
213*4882a593Smuzhiyun },
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun .name = "vdd2",
216*4882a593Smuzhiyun .vin_name = "vcc2",
217*4882a593Smuzhiyun .n_voltages = 0x4C,
218*4882a593Smuzhiyun .enable_time_us = 350,
219*4882a593Smuzhiyun },
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun .name = "vddctrl",
222*4882a593Smuzhiyun .n_voltages = 0x44,
223*4882a593Smuzhiyun .enable_time_us = 900,
224*4882a593Smuzhiyun },
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun .name = "ldo1",
227*4882a593Smuzhiyun .vin_name = "vcc6",
228*4882a593Smuzhiyun .n_voltages = 0x33,
229*4882a593Smuzhiyun .enable_time_us = 420,
230*4882a593Smuzhiyun },
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun .name = "ldo2",
233*4882a593Smuzhiyun .vin_name = "vcc6",
234*4882a593Smuzhiyun .n_voltages = 0x33,
235*4882a593Smuzhiyun .enable_time_us = 420,
236*4882a593Smuzhiyun },
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun .name = "ldo3",
239*4882a593Smuzhiyun .vin_name = "vcc5",
240*4882a593Smuzhiyun .n_voltages = 0x1A,
241*4882a593Smuzhiyun .enable_time_us = 230,
242*4882a593Smuzhiyun },
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun .name = "ldo4",
245*4882a593Smuzhiyun .vin_name = "vcc5",
246*4882a593Smuzhiyun .n_voltages = 0x33,
247*4882a593Smuzhiyun .enable_time_us = 230,
248*4882a593Smuzhiyun },
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun .name = "ldo5",
251*4882a593Smuzhiyun .vin_name = "vcc4",
252*4882a593Smuzhiyun .n_voltages = 0x1A,
253*4882a593Smuzhiyun .enable_time_us = 230,
254*4882a593Smuzhiyun },
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun .name = "ldo6",
257*4882a593Smuzhiyun .vin_name = "vcc3",
258*4882a593Smuzhiyun .n_voltages = 0x1A,
259*4882a593Smuzhiyun .enable_time_us = 230,
260*4882a593Smuzhiyun },
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun .name = "ldo7",
263*4882a593Smuzhiyun .vin_name = "vcc3",
264*4882a593Smuzhiyun .n_voltages = 0x1A,
265*4882a593Smuzhiyun .enable_time_us = 230,
266*4882a593Smuzhiyun },
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun .name = "ldo8",
269*4882a593Smuzhiyun .vin_name = "vcc3",
270*4882a593Smuzhiyun .n_voltages = 0x1A,
271*4882a593Smuzhiyun .enable_time_us = 230,
272*4882a593Smuzhiyun },
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun #define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits))
276*4882a593Smuzhiyun static unsigned int tps65910_ext_sleep_control[] = {
277*4882a593Smuzhiyun 0,
278*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VIO, 1, 0),
279*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VDD1, 1, 1),
280*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VDD2, 1, 2),
281*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VDD3, 1, 3),
282*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VDIG1, 0, 1),
283*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VDIG2, 0, 2),
284*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VPLL, 0, 6),
285*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VDAC, 0, 7),
286*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VAUX1, 0, 3),
287*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VAUX2, 0, 4),
288*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VAUX33, 0, 5),
289*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VMMC, 0, 0),
290*4882a593Smuzhiyun };
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun static unsigned int tps65911_ext_sleep_control[] = {
293*4882a593Smuzhiyun 0,
294*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VIO, 1, 0),
295*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VDD1, 1, 1),
296*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VDD2, 1, 2),
297*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3),
298*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(LDO1, 0, 1),
299*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(LDO2, 0, 2),
300*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(LDO3, 0, 7),
301*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(LDO4, 0, 6),
302*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(LDO5, 0, 3),
303*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(LDO6, 0, 0),
304*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(LDO7, 0, 5),
305*4882a593Smuzhiyun EXT_CONTROL_REG_BITS(LDO8, 0, 4),
306*4882a593Smuzhiyun };
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun struct tps65910_reg {
309*4882a593Smuzhiyun struct regulator_desc *desc;
310*4882a593Smuzhiyun struct tps65910 *mfd;
311*4882a593Smuzhiyun struct regulator_dev **rdev;
312*4882a593Smuzhiyun struct tps_info **info;
313*4882a593Smuzhiyun int num_regulators;
314*4882a593Smuzhiyun int mode;
315*4882a593Smuzhiyun int (*get_ctrl_reg)(int);
316*4882a593Smuzhiyun unsigned int *ext_sleep_control;
317*4882a593Smuzhiyun unsigned int board_ext_control[TPS65910_NUM_REGS];
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun
tps65910_get_ctrl_register(int id)320*4882a593Smuzhiyun static int tps65910_get_ctrl_register(int id)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun switch (id) {
323*4882a593Smuzhiyun case TPS65910_REG_VRTC:
324*4882a593Smuzhiyun return TPS65910_VRTC;
325*4882a593Smuzhiyun case TPS65910_REG_VIO:
326*4882a593Smuzhiyun return TPS65910_VIO;
327*4882a593Smuzhiyun case TPS65910_REG_VDD1:
328*4882a593Smuzhiyun return TPS65910_VDD1;
329*4882a593Smuzhiyun case TPS65910_REG_VDD2:
330*4882a593Smuzhiyun return TPS65910_VDD2;
331*4882a593Smuzhiyun case TPS65910_REG_VDD3:
332*4882a593Smuzhiyun return TPS65910_VDD3;
333*4882a593Smuzhiyun case TPS65910_REG_VDIG1:
334*4882a593Smuzhiyun return TPS65910_VDIG1;
335*4882a593Smuzhiyun case TPS65910_REG_VDIG2:
336*4882a593Smuzhiyun return TPS65910_VDIG2;
337*4882a593Smuzhiyun case TPS65910_REG_VPLL:
338*4882a593Smuzhiyun return TPS65910_VPLL;
339*4882a593Smuzhiyun case TPS65910_REG_VDAC:
340*4882a593Smuzhiyun return TPS65910_VDAC;
341*4882a593Smuzhiyun case TPS65910_REG_VAUX1:
342*4882a593Smuzhiyun return TPS65910_VAUX1;
343*4882a593Smuzhiyun case TPS65910_REG_VAUX2:
344*4882a593Smuzhiyun return TPS65910_VAUX2;
345*4882a593Smuzhiyun case TPS65910_REG_VAUX33:
346*4882a593Smuzhiyun return TPS65910_VAUX33;
347*4882a593Smuzhiyun case TPS65910_REG_VMMC:
348*4882a593Smuzhiyun return TPS65910_VMMC;
349*4882a593Smuzhiyun case TPS65910_REG_VBB:
350*4882a593Smuzhiyun return TPS65910_BBCH;
351*4882a593Smuzhiyun default:
352*4882a593Smuzhiyun return -EINVAL;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
tps65911_get_ctrl_register(int id)356*4882a593Smuzhiyun static int tps65911_get_ctrl_register(int id)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun switch (id) {
359*4882a593Smuzhiyun case TPS65910_REG_VRTC:
360*4882a593Smuzhiyun return TPS65910_VRTC;
361*4882a593Smuzhiyun case TPS65910_REG_VIO:
362*4882a593Smuzhiyun return TPS65910_VIO;
363*4882a593Smuzhiyun case TPS65910_REG_VDD1:
364*4882a593Smuzhiyun return TPS65910_VDD1;
365*4882a593Smuzhiyun case TPS65910_REG_VDD2:
366*4882a593Smuzhiyun return TPS65910_VDD2;
367*4882a593Smuzhiyun case TPS65911_REG_VDDCTRL:
368*4882a593Smuzhiyun return TPS65911_VDDCTRL;
369*4882a593Smuzhiyun case TPS65911_REG_LDO1:
370*4882a593Smuzhiyun return TPS65911_LDO1;
371*4882a593Smuzhiyun case TPS65911_REG_LDO2:
372*4882a593Smuzhiyun return TPS65911_LDO2;
373*4882a593Smuzhiyun case TPS65911_REG_LDO3:
374*4882a593Smuzhiyun return TPS65911_LDO3;
375*4882a593Smuzhiyun case TPS65911_REG_LDO4:
376*4882a593Smuzhiyun return TPS65911_LDO4;
377*4882a593Smuzhiyun case TPS65911_REG_LDO5:
378*4882a593Smuzhiyun return TPS65911_LDO5;
379*4882a593Smuzhiyun case TPS65911_REG_LDO6:
380*4882a593Smuzhiyun return TPS65911_LDO6;
381*4882a593Smuzhiyun case TPS65911_REG_LDO7:
382*4882a593Smuzhiyun return TPS65911_LDO7;
383*4882a593Smuzhiyun case TPS65911_REG_LDO8:
384*4882a593Smuzhiyun return TPS65911_LDO8;
385*4882a593Smuzhiyun default:
386*4882a593Smuzhiyun return -EINVAL;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun
tps65910_set_mode(struct regulator_dev * dev,unsigned int mode)390*4882a593Smuzhiyun static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode)
391*4882a593Smuzhiyun {
392*4882a593Smuzhiyun struct tps65910_reg *pmic = rdev_get_drvdata(dev);
393*4882a593Smuzhiyun struct regmap *regmap = rdev_get_regmap(dev);
394*4882a593Smuzhiyun int reg, id = rdev_get_id(dev);
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun reg = pmic->get_ctrl_reg(id);
397*4882a593Smuzhiyun if (reg < 0)
398*4882a593Smuzhiyun return reg;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun switch (mode) {
401*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
402*4882a593Smuzhiyun return regmap_update_bits(regmap, reg,
403*4882a593Smuzhiyun LDO_ST_MODE_BIT | LDO_ST_ON_BIT,
404*4882a593Smuzhiyun LDO_ST_ON_BIT);
405*4882a593Smuzhiyun case REGULATOR_MODE_IDLE:
406*4882a593Smuzhiyun return regmap_set_bits(regmap, reg,
407*4882a593Smuzhiyun LDO_ST_ON_BIT | LDO_ST_MODE_BIT);
408*4882a593Smuzhiyun case REGULATOR_MODE_STANDBY:
409*4882a593Smuzhiyun return regmap_clear_bits(regmap, reg, LDO_ST_ON_BIT);
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun return -EINVAL;
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun
tps65910_get_mode(struct regulator_dev * dev)415*4882a593Smuzhiyun static unsigned int tps65910_get_mode(struct regulator_dev *dev)
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun struct tps65910_reg *pmic = rdev_get_drvdata(dev);
418*4882a593Smuzhiyun struct regmap *regmap = rdev_get_regmap(dev);
419*4882a593Smuzhiyun int ret, reg, value, id = rdev_get_id(dev);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun reg = pmic->get_ctrl_reg(id);
422*4882a593Smuzhiyun if (reg < 0)
423*4882a593Smuzhiyun return reg;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun ret = regmap_read(regmap, reg, &value);
426*4882a593Smuzhiyun if (ret < 0)
427*4882a593Smuzhiyun return ret;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun if (!(value & LDO_ST_ON_BIT))
430*4882a593Smuzhiyun return REGULATOR_MODE_STANDBY;
431*4882a593Smuzhiyun else if (value & LDO_ST_MODE_BIT)
432*4882a593Smuzhiyun return REGULATOR_MODE_IDLE;
433*4882a593Smuzhiyun else
434*4882a593Smuzhiyun return REGULATOR_MODE_NORMAL;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun
tps65910_get_voltage_dcdc_sel(struct regulator_dev * dev)437*4882a593Smuzhiyun static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev)
438*4882a593Smuzhiyun {
439*4882a593Smuzhiyun struct regmap *regmap = rdev_get_regmap(dev);
440*4882a593Smuzhiyun int ret, id = rdev_get_id(dev);
441*4882a593Smuzhiyun int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun switch (id) {
444*4882a593Smuzhiyun case TPS65910_REG_VDD1:
445*4882a593Smuzhiyun ret = regmap_read(regmap, TPS65910_VDD1_OP, &opvsel);
446*4882a593Smuzhiyun if (ret < 0)
447*4882a593Smuzhiyun return ret;
448*4882a593Smuzhiyun ret = regmap_read(regmap, TPS65910_VDD1, &mult);
449*4882a593Smuzhiyun if (ret < 0)
450*4882a593Smuzhiyun return ret;
451*4882a593Smuzhiyun mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
452*4882a593Smuzhiyun ret = regmap_read(regmap, TPS65910_VDD1_SR, &srvsel);
453*4882a593Smuzhiyun if (ret < 0)
454*4882a593Smuzhiyun return ret;
455*4882a593Smuzhiyun sr = opvsel & VDD1_OP_CMD_MASK;
456*4882a593Smuzhiyun opvsel &= VDD1_OP_SEL_MASK;
457*4882a593Smuzhiyun srvsel &= VDD1_SR_SEL_MASK;
458*4882a593Smuzhiyun vselmax = 75;
459*4882a593Smuzhiyun break;
460*4882a593Smuzhiyun case TPS65910_REG_VDD2:
461*4882a593Smuzhiyun ret = regmap_read(regmap, TPS65910_VDD2_OP, &opvsel);
462*4882a593Smuzhiyun if (ret < 0)
463*4882a593Smuzhiyun return ret;
464*4882a593Smuzhiyun ret = regmap_read(regmap, TPS65910_VDD2, &mult);
465*4882a593Smuzhiyun if (ret < 0)
466*4882a593Smuzhiyun return ret;
467*4882a593Smuzhiyun mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT;
468*4882a593Smuzhiyun ret = regmap_read(regmap, TPS65910_VDD2_SR, &srvsel);
469*4882a593Smuzhiyun if (ret < 0)
470*4882a593Smuzhiyun return ret;
471*4882a593Smuzhiyun sr = opvsel & VDD2_OP_CMD_MASK;
472*4882a593Smuzhiyun opvsel &= VDD2_OP_SEL_MASK;
473*4882a593Smuzhiyun srvsel &= VDD2_SR_SEL_MASK;
474*4882a593Smuzhiyun vselmax = 75;
475*4882a593Smuzhiyun break;
476*4882a593Smuzhiyun case TPS65911_REG_VDDCTRL:
477*4882a593Smuzhiyun ret = regmap_read(regmap, TPS65911_VDDCTRL_OP, &opvsel);
478*4882a593Smuzhiyun if (ret < 0)
479*4882a593Smuzhiyun return ret;
480*4882a593Smuzhiyun ret = regmap_read(regmap, TPS65911_VDDCTRL_SR, &srvsel);
481*4882a593Smuzhiyun if (ret < 0)
482*4882a593Smuzhiyun return ret;
483*4882a593Smuzhiyun sr = opvsel & VDDCTRL_OP_CMD_MASK;
484*4882a593Smuzhiyun opvsel &= VDDCTRL_OP_SEL_MASK;
485*4882a593Smuzhiyun srvsel &= VDDCTRL_SR_SEL_MASK;
486*4882a593Smuzhiyun vselmax = 64;
487*4882a593Smuzhiyun break;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun /* multiplier 0 == 1 but 2,3 normal */
491*4882a593Smuzhiyun if (!mult)
492*4882a593Smuzhiyun mult = 1;
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun if (sr) {
495*4882a593Smuzhiyun /* normalise to valid range */
496*4882a593Smuzhiyun if (srvsel < 3)
497*4882a593Smuzhiyun srvsel = 3;
498*4882a593Smuzhiyun if (srvsel > vselmax)
499*4882a593Smuzhiyun srvsel = vselmax;
500*4882a593Smuzhiyun return srvsel - 3;
501*4882a593Smuzhiyun } else {
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun /* normalise to valid range*/
504*4882a593Smuzhiyun if (opvsel < 3)
505*4882a593Smuzhiyun opvsel = 3;
506*4882a593Smuzhiyun if (opvsel > vselmax)
507*4882a593Smuzhiyun opvsel = vselmax;
508*4882a593Smuzhiyun return opvsel - 3;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun return -EINVAL;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun
tps65910_get_voltage_sel(struct regulator_dev * dev)513*4882a593Smuzhiyun static int tps65910_get_voltage_sel(struct regulator_dev *dev)
514*4882a593Smuzhiyun {
515*4882a593Smuzhiyun struct tps65910_reg *pmic = rdev_get_drvdata(dev);
516*4882a593Smuzhiyun struct regmap *regmap = rdev_get_regmap(dev);
517*4882a593Smuzhiyun int ret, reg, value, id = rdev_get_id(dev);
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun reg = pmic->get_ctrl_reg(id);
520*4882a593Smuzhiyun if (reg < 0)
521*4882a593Smuzhiyun return reg;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun ret = regmap_read(regmap, reg, &value);
524*4882a593Smuzhiyun if (ret < 0)
525*4882a593Smuzhiyun return ret;
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun switch (id) {
528*4882a593Smuzhiyun case TPS65910_REG_VIO:
529*4882a593Smuzhiyun case TPS65910_REG_VDIG1:
530*4882a593Smuzhiyun case TPS65910_REG_VDIG2:
531*4882a593Smuzhiyun case TPS65910_REG_VPLL:
532*4882a593Smuzhiyun case TPS65910_REG_VDAC:
533*4882a593Smuzhiyun case TPS65910_REG_VAUX1:
534*4882a593Smuzhiyun case TPS65910_REG_VAUX2:
535*4882a593Smuzhiyun case TPS65910_REG_VAUX33:
536*4882a593Smuzhiyun case TPS65910_REG_VMMC:
537*4882a593Smuzhiyun value &= LDO_SEL_MASK;
538*4882a593Smuzhiyun value >>= LDO_SEL_SHIFT;
539*4882a593Smuzhiyun break;
540*4882a593Smuzhiyun case TPS65910_REG_VBB:
541*4882a593Smuzhiyun value &= BBCH_BBSEL_MASK;
542*4882a593Smuzhiyun value >>= BBCH_BBSEL_SHIFT;
543*4882a593Smuzhiyun break;
544*4882a593Smuzhiyun default:
545*4882a593Smuzhiyun return -EINVAL;
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun return value;
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun
tps65910_get_voltage_vdd3(struct regulator_dev * dev)551*4882a593Smuzhiyun static int tps65910_get_voltage_vdd3(struct regulator_dev *dev)
552*4882a593Smuzhiyun {
553*4882a593Smuzhiyun return dev->desc->volt_table[0];
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun
tps65911_get_voltage_sel(struct regulator_dev * dev)556*4882a593Smuzhiyun static int tps65911_get_voltage_sel(struct regulator_dev *dev)
557*4882a593Smuzhiyun {
558*4882a593Smuzhiyun struct tps65910_reg *pmic = rdev_get_drvdata(dev);
559*4882a593Smuzhiyun struct regmap *regmap = rdev_get_regmap(dev);
560*4882a593Smuzhiyun int ret, id = rdev_get_id(dev);
561*4882a593Smuzhiyun unsigned int value, reg;
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun reg = pmic->get_ctrl_reg(id);
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun ret = regmap_read(regmap, reg, &value);
566*4882a593Smuzhiyun if (ret < 0)
567*4882a593Smuzhiyun return ret;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun switch (id) {
570*4882a593Smuzhiyun case TPS65911_REG_LDO1:
571*4882a593Smuzhiyun case TPS65911_REG_LDO2:
572*4882a593Smuzhiyun case TPS65911_REG_LDO4:
573*4882a593Smuzhiyun value &= LDO1_SEL_MASK;
574*4882a593Smuzhiyun value >>= LDO_SEL_SHIFT;
575*4882a593Smuzhiyun break;
576*4882a593Smuzhiyun case TPS65911_REG_LDO3:
577*4882a593Smuzhiyun case TPS65911_REG_LDO5:
578*4882a593Smuzhiyun case TPS65911_REG_LDO6:
579*4882a593Smuzhiyun case TPS65911_REG_LDO7:
580*4882a593Smuzhiyun case TPS65911_REG_LDO8:
581*4882a593Smuzhiyun value &= LDO3_SEL_MASK;
582*4882a593Smuzhiyun value >>= LDO_SEL_SHIFT;
583*4882a593Smuzhiyun break;
584*4882a593Smuzhiyun case TPS65910_REG_VIO:
585*4882a593Smuzhiyun value &= LDO_SEL_MASK;
586*4882a593Smuzhiyun value >>= LDO_SEL_SHIFT;
587*4882a593Smuzhiyun break;
588*4882a593Smuzhiyun default:
589*4882a593Smuzhiyun return -EINVAL;
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun return value;
593*4882a593Smuzhiyun }
594*4882a593Smuzhiyun
tps65910_set_voltage_dcdc_sel(struct regulator_dev * dev,unsigned selector)595*4882a593Smuzhiyun static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
596*4882a593Smuzhiyun unsigned selector)
597*4882a593Smuzhiyun {
598*4882a593Smuzhiyun struct regmap *regmap = rdev_get_regmap(dev);
599*4882a593Smuzhiyun int id = rdev_get_id(dev), vsel;
600*4882a593Smuzhiyun int dcdc_mult = 0;
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun switch (id) {
603*4882a593Smuzhiyun case TPS65910_REG_VDD1:
604*4882a593Smuzhiyun dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
605*4882a593Smuzhiyun if (dcdc_mult == 1)
606*4882a593Smuzhiyun dcdc_mult--;
607*4882a593Smuzhiyun vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun regmap_update_bits(regmap, TPS65910_VDD1, VDD1_VGAIN_SEL_MASK,
610*4882a593Smuzhiyun dcdc_mult << VDD1_VGAIN_SEL_SHIFT);
611*4882a593Smuzhiyun regmap_write(regmap, TPS65910_VDD1_OP, vsel);
612*4882a593Smuzhiyun break;
613*4882a593Smuzhiyun case TPS65910_REG_VDD2:
614*4882a593Smuzhiyun dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
615*4882a593Smuzhiyun if (dcdc_mult == 1)
616*4882a593Smuzhiyun dcdc_mult--;
617*4882a593Smuzhiyun vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun regmap_update_bits(regmap, TPS65910_VDD2, VDD1_VGAIN_SEL_MASK,
620*4882a593Smuzhiyun dcdc_mult << VDD2_VGAIN_SEL_SHIFT);
621*4882a593Smuzhiyun regmap_write(regmap, TPS65910_VDD2_OP, vsel);
622*4882a593Smuzhiyun break;
623*4882a593Smuzhiyun case TPS65911_REG_VDDCTRL:
624*4882a593Smuzhiyun vsel = selector + 3;
625*4882a593Smuzhiyun regmap_write(regmap, TPS65911_VDDCTRL_OP, vsel);
626*4882a593Smuzhiyun break;
627*4882a593Smuzhiyun }
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun return 0;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun
tps65910_set_voltage_sel(struct regulator_dev * dev,unsigned selector)632*4882a593Smuzhiyun static int tps65910_set_voltage_sel(struct regulator_dev *dev,
633*4882a593Smuzhiyun unsigned selector)
634*4882a593Smuzhiyun {
635*4882a593Smuzhiyun struct tps65910_reg *pmic = rdev_get_drvdata(dev);
636*4882a593Smuzhiyun struct regmap *regmap = rdev_get_regmap(dev);
637*4882a593Smuzhiyun int reg, id = rdev_get_id(dev);
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun reg = pmic->get_ctrl_reg(id);
640*4882a593Smuzhiyun if (reg < 0)
641*4882a593Smuzhiyun return reg;
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun switch (id) {
644*4882a593Smuzhiyun case TPS65910_REG_VIO:
645*4882a593Smuzhiyun case TPS65910_REG_VDIG1:
646*4882a593Smuzhiyun case TPS65910_REG_VDIG2:
647*4882a593Smuzhiyun case TPS65910_REG_VPLL:
648*4882a593Smuzhiyun case TPS65910_REG_VDAC:
649*4882a593Smuzhiyun case TPS65910_REG_VAUX1:
650*4882a593Smuzhiyun case TPS65910_REG_VAUX2:
651*4882a593Smuzhiyun case TPS65910_REG_VAUX33:
652*4882a593Smuzhiyun case TPS65910_REG_VMMC:
653*4882a593Smuzhiyun return regmap_update_bits(regmap, reg, LDO_SEL_MASK,
654*4882a593Smuzhiyun selector << LDO_SEL_SHIFT);
655*4882a593Smuzhiyun case TPS65910_REG_VBB:
656*4882a593Smuzhiyun return regmap_update_bits(regmap, reg, BBCH_BBSEL_MASK,
657*4882a593Smuzhiyun selector << BBCH_BBSEL_SHIFT);
658*4882a593Smuzhiyun }
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun return -EINVAL;
661*4882a593Smuzhiyun }
662*4882a593Smuzhiyun
tps65911_set_voltage_sel(struct regulator_dev * dev,unsigned selector)663*4882a593Smuzhiyun static int tps65911_set_voltage_sel(struct regulator_dev *dev,
664*4882a593Smuzhiyun unsigned selector)
665*4882a593Smuzhiyun {
666*4882a593Smuzhiyun struct tps65910_reg *pmic = rdev_get_drvdata(dev);
667*4882a593Smuzhiyun struct regmap *regmap = rdev_get_regmap(dev);
668*4882a593Smuzhiyun int reg, id = rdev_get_id(dev);
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun reg = pmic->get_ctrl_reg(id);
671*4882a593Smuzhiyun if (reg < 0)
672*4882a593Smuzhiyun return reg;
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun switch (id) {
675*4882a593Smuzhiyun case TPS65911_REG_LDO1:
676*4882a593Smuzhiyun case TPS65911_REG_LDO2:
677*4882a593Smuzhiyun case TPS65911_REG_LDO4:
678*4882a593Smuzhiyun return regmap_update_bits(regmap, reg, LDO1_SEL_MASK,
679*4882a593Smuzhiyun selector << LDO_SEL_SHIFT);
680*4882a593Smuzhiyun case TPS65911_REG_LDO3:
681*4882a593Smuzhiyun case TPS65911_REG_LDO5:
682*4882a593Smuzhiyun case TPS65911_REG_LDO6:
683*4882a593Smuzhiyun case TPS65911_REG_LDO7:
684*4882a593Smuzhiyun case TPS65911_REG_LDO8:
685*4882a593Smuzhiyun return regmap_update_bits(regmap, reg, LDO3_SEL_MASK,
686*4882a593Smuzhiyun selector << LDO_SEL_SHIFT);
687*4882a593Smuzhiyun case TPS65910_REG_VIO:
688*4882a593Smuzhiyun return regmap_update_bits(regmap, reg, LDO_SEL_MASK,
689*4882a593Smuzhiyun selector << LDO_SEL_SHIFT);
690*4882a593Smuzhiyun case TPS65910_REG_VBB:
691*4882a593Smuzhiyun return regmap_update_bits(regmap, reg, BBCH_BBSEL_MASK,
692*4882a593Smuzhiyun selector << BBCH_BBSEL_SHIFT);
693*4882a593Smuzhiyun }
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun return -EINVAL;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun
tps65910_list_voltage_dcdc(struct regulator_dev * dev,unsigned selector)699*4882a593Smuzhiyun static int tps65910_list_voltage_dcdc(struct regulator_dev *dev,
700*4882a593Smuzhiyun unsigned selector)
701*4882a593Smuzhiyun {
702*4882a593Smuzhiyun int volt, mult = 1, id = rdev_get_id(dev);
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun switch (id) {
705*4882a593Smuzhiyun case TPS65910_REG_VDD1:
706*4882a593Smuzhiyun case TPS65910_REG_VDD2:
707*4882a593Smuzhiyun mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
708*4882a593Smuzhiyun volt = VDD1_2_MIN_VOLT +
709*4882a593Smuzhiyun (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET;
710*4882a593Smuzhiyun break;
711*4882a593Smuzhiyun case TPS65911_REG_VDDCTRL:
712*4882a593Smuzhiyun volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET);
713*4882a593Smuzhiyun break;
714*4882a593Smuzhiyun default:
715*4882a593Smuzhiyun BUG();
716*4882a593Smuzhiyun return -EINVAL;
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun return volt * 100 * mult;
720*4882a593Smuzhiyun }
721*4882a593Smuzhiyun
tps65911_list_voltage(struct regulator_dev * dev,unsigned selector)722*4882a593Smuzhiyun static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector)
723*4882a593Smuzhiyun {
724*4882a593Smuzhiyun struct tps65910_reg *pmic = rdev_get_drvdata(dev);
725*4882a593Smuzhiyun int step_mv = 0, id = rdev_get_id(dev);
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun switch (id) {
728*4882a593Smuzhiyun case TPS65911_REG_LDO1:
729*4882a593Smuzhiyun case TPS65911_REG_LDO2:
730*4882a593Smuzhiyun case TPS65911_REG_LDO4:
731*4882a593Smuzhiyun /* The first 5 values of the selector correspond to 1V */
732*4882a593Smuzhiyun if (selector < 5)
733*4882a593Smuzhiyun selector = 0;
734*4882a593Smuzhiyun else
735*4882a593Smuzhiyun selector -= 4;
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun step_mv = 50;
738*4882a593Smuzhiyun break;
739*4882a593Smuzhiyun case TPS65911_REG_LDO3:
740*4882a593Smuzhiyun case TPS65911_REG_LDO5:
741*4882a593Smuzhiyun case TPS65911_REG_LDO6:
742*4882a593Smuzhiyun case TPS65911_REG_LDO7:
743*4882a593Smuzhiyun case TPS65911_REG_LDO8:
744*4882a593Smuzhiyun /* The first 3 values of the selector correspond to 1V */
745*4882a593Smuzhiyun if (selector < 3)
746*4882a593Smuzhiyun selector = 0;
747*4882a593Smuzhiyun else
748*4882a593Smuzhiyun selector -= 2;
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun step_mv = 100;
751*4882a593Smuzhiyun break;
752*4882a593Smuzhiyun case TPS65910_REG_VIO:
753*4882a593Smuzhiyun return pmic->info[id]->voltage_table[selector];
754*4882a593Smuzhiyun default:
755*4882a593Smuzhiyun return -EINVAL;
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun return (LDO_MIN_VOLT + selector * step_mv) * 1000;
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun /* Regulator ops (except VRTC) */
762*4882a593Smuzhiyun static const struct regulator_ops tps65910_ops_dcdc = {
763*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
764*4882a593Smuzhiyun .enable = regulator_enable_regmap,
765*4882a593Smuzhiyun .disable = regulator_disable_regmap,
766*4882a593Smuzhiyun .set_mode = tps65910_set_mode,
767*4882a593Smuzhiyun .get_mode = tps65910_get_mode,
768*4882a593Smuzhiyun .get_voltage_sel = tps65910_get_voltage_dcdc_sel,
769*4882a593Smuzhiyun .set_voltage_sel = tps65910_set_voltage_dcdc_sel,
770*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
771*4882a593Smuzhiyun .list_voltage = tps65910_list_voltage_dcdc,
772*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_ascend,
773*4882a593Smuzhiyun };
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun static const struct regulator_ops tps65910_ops_vdd3 = {
776*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
777*4882a593Smuzhiyun .enable = regulator_enable_regmap,
778*4882a593Smuzhiyun .disable = regulator_disable_regmap,
779*4882a593Smuzhiyun .set_mode = tps65910_set_mode,
780*4882a593Smuzhiyun .get_mode = tps65910_get_mode,
781*4882a593Smuzhiyun .get_voltage = tps65910_get_voltage_vdd3,
782*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_table,
783*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_ascend,
784*4882a593Smuzhiyun };
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun static const struct regulator_ops tps65910_ops_vbb = {
787*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
788*4882a593Smuzhiyun .enable = regulator_enable_regmap,
789*4882a593Smuzhiyun .disable = regulator_disable_regmap,
790*4882a593Smuzhiyun .set_mode = tps65910_set_mode,
791*4882a593Smuzhiyun .get_mode = tps65910_get_mode,
792*4882a593Smuzhiyun .get_voltage_sel = tps65910_get_voltage_sel,
793*4882a593Smuzhiyun .set_voltage_sel = tps65910_set_voltage_sel,
794*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_table,
795*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_iterate,
796*4882a593Smuzhiyun };
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun static const struct regulator_ops tps65910_ops = {
799*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
800*4882a593Smuzhiyun .enable = regulator_enable_regmap,
801*4882a593Smuzhiyun .disable = regulator_disable_regmap,
802*4882a593Smuzhiyun .set_mode = tps65910_set_mode,
803*4882a593Smuzhiyun .get_mode = tps65910_get_mode,
804*4882a593Smuzhiyun .get_voltage_sel = tps65910_get_voltage_sel,
805*4882a593Smuzhiyun .set_voltage_sel = tps65910_set_voltage_sel,
806*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_table,
807*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_ascend,
808*4882a593Smuzhiyun };
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun static const struct regulator_ops tps65911_ops = {
811*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
812*4882a593Smuzhiyun .enable = regulator_enable_regmap,
813*4882a593Smuzhiyun .disable = regulator_disable_regmap,
814*4882a593Smuzhiyun .set_mode = tps65910_set_mode,
815*4882a593Smuzhiyun .get_mode = tps65910_get_mode,
816*4882a593Smuzhiyun .get_voltage_sel = tps65911_get_voltage_sel,
817*4882a593Smuzhiyun .set_voltage_sel = tps65911_set_voltage_sel,
818*4882a593Smuzhiyun .list_voltage = tps65911_list_voltage,
819*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_ascend,
820*4882a593Smuzhiyun };
821*4882a593Smuzhiyun
tps65910_set_ext_sleep_config(struct tps65910_reg * pmic,int id,int ext_sleep_config)822*4882a593Smuzhiyun static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
823*4882a593Smuzhiyun int id, int ext_sleep_config)
824*4882a593Smuzhiyun {
825*4882a593Smuzhiyun struct tps65910 *mfd = pmic->mfd;
826*4882a593Smuzhiyun u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF;
827*4882a593Smuzhiyun u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF);
828*4882a593Smuzhiyun int ret;
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun /*
831*4882a593Smuzhiyun * Regulator can not be control from multiple external input EN1, EN2
832*4882a593Smuzhiyun * and EN3 together.
833*4882a593Smuzhiyun */
834*4882a593Smuzhiyun if (ext_sleep_config & EXT_SLEEP_CONTROL) {
835*4882a593Smuzhiyun int en_count;
836*4882a593Smuzhiyun en_count = ((ext_sleep_config &
837*4882a593Smuzhiyun TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0);
838*4882a593Smuzhiyun en_count += ((ext_sleep_config &
839*4882a593Smuzhiyun TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0);
840*4882a593Smuzhiyun en_count += ((ext_sleep_config &
841*4882a593Smuzhiyun TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0);
842*4882a593Smuzhiyun en_count += ((ext_sleep_config &
843*4882a593Smuzhiyun TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0);
844*4882a593Smuzhiyun if (en_count > 1) {
845*4882a593Smuzhiyun dev_err(mfd->dev,
846*4882a593Smuzhiyun "External sleep control flag is not proper\n");
847*4882a593Smuzhiyun return -EINVAL;
848*4882a593Smuzhiyun }
849*4882a593Smuzhiyun }
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun pmic->board_ext_control[id] = ext_sleep_config;
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun /* External EN1 control */
854*4882a593Smuzhiyun if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1)
855*4882a593Smuzhiyun ret = regmap_set_bits(mfd->regmap,
856*4882a593Smuzhiyun TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
857*4882a593Smuzhiyun else
858*4882a593Smuzhiyun ret = regmap_clear_bits(mfd->regmap,
859*4882a593Smuzhiyun TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
860*4882a593Smuzhiyun if (ret < 0) {
861*4882a593Smuzhiyun dev_err(mfd->dev,
862*4882a593Smuzhiyun "Error in configuring external control EN1\n");
863*4882a593Smuzhiyun return ret;
864*4882a593Smuzhiyun }
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun /* External EN2 control */
867*4882a593Smuzhiyun if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2)
868*4882a593Smuzhiyun ret = regmap_set_bits(mfd->regmap,
869*4882a593Smuzhiyun TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
870*4882a593Smuzhiyun else
871*4882a593Smuzhiyun ret = regmap_clear_bits(mfd->regmap,
872*4882a593Smuzhiyun TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
873*4882a593Smuzhiyun if (ret < 0) {
874*4882a593Smuzhiyun dev_err(mfd->dev,
875*4882a593Smuzhiyun "Error in configuring external control EN2\n");
876*4882a593Smuzhiyun return ret;
877*4882a593Smuzhiyun }
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun /* External EN3 control for TPS65910 LDO only */
880*4882a593Smuzhiyun if ((tps65910_chip_id(mfd) == TPS65910) &&
881*4882a593Smuzhiyun (id >= TPS65910_REG_VDIG1)) {
882*4882a593Smuzhiyun if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3)
883*4882a593Smuzhiyun ret = regmap_set_bits(mfd->regmap,
884*4882a593Smuzhiyun TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
885*4882a593Smuzhiyun else
886*4882a593Smuzhiyun ret = regmap_clear_bits(mfd->regmap,
887*4882a593Smuzhiyun TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
888*4882a593Smuzhiyun if (ret < 0) {
889*4882a593Smuzhiyun dev_err(mfd->dev,
890*4882a593Smuzhiyun "Error in configuring external control EN3\n");
891*4882a593Smuzhiyun return ret;
892*4882a593Smuzhiyun }
893*4882a593Smuzhiyun }
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun /* Return if no external control is selected */
896*4882a593Smuzhiyun if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) {
897*4882a593Smuzhiyun /* Clear all sleep controls */
898*4882a593Smuzhiyun ret = regmap_clear_bits(mfd->regmap,
899*4882a593Smuzhiyun TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
900*4882a593Smuzhiyun if (!ret)
901*4882a593Smuzhiyun ret = regmap_clear_bits(mfd->regmap,
902*4882a593Smuzhiyun TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
903*4882a593Smuzhiyun if (ret < 0)
904*4882a593Smuzhiyun dev_err(mfd->dev,
905*4882a593Smuzhiyun "Error in configuring SLEEP register\n");
906*4882a593Smuzhiyun return ret;
907*4882a593Smuzhiyun }
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun /*
910*4882a593Smuzhiyun * For regulator that has separate operational and sleep register make
911*4882a593Smuzhiyun * sure that operational is used and clear sleep register to turn
912*4882a593Smuzhiyun * regulator off when external control is inactive
913*4882a593Smuzhiyun */
914*4882a593Smuzhiyun if ((id == TPS65910_REG_VDD1) ||
915*4882a593Smuzhiyun (id == TPS65910_REG_VDD2) ||
916*4882a593Smuzhiyun ((id == TPS65911_REG_VDDCTRL) &&
917*4882a593Smuzhiyun (tps65910_chip_id(mfd) == TPS65911))) {
918*4882a593Smuzhiyun int op_reg_add = pmic->get_ctrl_reg(id) + 1;
919*4882a593Smuzhiyun int sr_reg_add = pmic->get_ctrl_reg(id) + 2;
920*4882a593Smuzhiyun int opvsel, srvsel;
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun ret = regmap_read(mfd->regmap, op_reg_add, &opvsel);
923*4882a593Smuzhiyun if (ret < 0)
924*4882a593Smuzhiyun return ret;
925*4882a593Smuzhiyun ret = regmap_read(mfd->regmap, sr_reg_add, &srvsel);
926*4882a593Smuzhiyun if (ret < 0)
927*4882a593Smuzhiyun return ret;
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun if (opvsel & VDD1_OP_CMD_MASK) {
930*4882a593Smuzhiyun u8 reg_val = srvsel & VDD1_OP_SEL_MASK;
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun ret = regmap_write(mfd->regmap, op_reg_add, reg_val);
933*4882a593Smuzhiyun if (ret < 0) {
934*4882a593Smuzhiyun dev_err(mfd->dev,
935*4882a593Smuzhiyun "Error in configuring op register\n");
936*4882a593Smuzhiyun return ret;
937*4882a593Smuzhiyun }
938*4882a593Smuzhiyun }
939*4882a593Smuzhiyun ret = regmap_write(mfd->regmap, sr_reg_add, 0);
940*4882a593Smuzhiyun if (ret < 0) {
941*4882a593Smuzhiyun dev_err(mfd->dev, "Error in setting sr register\n");
942*4882a593Smuzhiyun return ret;
943*4882a593Smuzhiyun }
944*4882a593Smuzhiyun }
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun ret = regmap_clear_bits(mfd->regmap,
947*4882a593Smuzhiyun TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
948*4882a593Smuzhiyun if (!ret) {
949*4882a593Smuzhiyun if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
950*4882a593Smuzhiyun ret = regmap_set_bits(mfd->regmap,
951*4882a593Smuzhiyun TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
952*4882a593Smuzhiyun else
953*4882a593Smuzhiyun ret = regmap_clear_bits(mfd->regmap,
954*4882a593Smuzhiyun TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
955*4882a593Smuzhiyun }
956*4882a593Smuzhiyun if (ret < 0)
957*4882a593Smuzhiyun dev_err(mfd->dev,
958*4882a593Smuzhiyun "Error in configuring SLEEP register\n");
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun return ret;
961*4882a593Smuzhiyun }
962*4882a593Smuzhiyun
963*4882a593Smuzhiyun #ifdef CONFIG_OF
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun static struct of_regulator_match tps65910_matches[] = {
966*4882a593Smuzhiyun { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] },
967*4882a593Smuzhiyun { .name = "vio", .driver_data = (void *) &tps65910_regs[1] },
968*4882a593Smuzhiyun { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] },
969*4882a593Smuzhiyun { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] },
970*4882a593Smuzhiyun { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] },
971*4882a593Smuzhiyun { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] },
972*4882a593Smuzhiyun { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] },
973*4882a593Smuzhiyun { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] },
974*4882a593Smuzhiyun { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] },
975*4882a593Smuzhiyun { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] },
976*4882a593Smuzhiyun { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] },
977*4882a593Smuzhiyun { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] },
978*4882a593Smuzhiyun { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] },
979*4882a593Smuzhiyun { .name = "vbb", .driver_data = (void *) &tps65910_regs[13] },
980*4882a593Smuzhiyun };
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun static struct of_regulator_match tps65911_matches[] = {
983*4882a593Smuzhiyun { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] },
984*4882a593Smuzhiyun { .name = "vio", .driver_data = (void *) &tps65911_regs[1] },
985*4882a593Smuzhiyun { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] },
986*4882a593Smuzhiyun { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] },
987*4882a593Smuzhiyun { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] },
988*4882a593Smuzhiyun { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] },
989*4882a593Smuzhiyun { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] },
990*4882a593Smuzhiyun { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] },
991*4882a593Smuzhiyun { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] },
992*4882a593Smuzhiyun { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] },
993*4882a593Smuzhiyun { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] },
994*4882a593Smuzhiyun { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] },
995*4882a593Smuzhiyun { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] },
996*4882a593Smuzhiyun };
997*4882a593Smuzhiyun
tps65910_parse_dt_reg_data(struct platform_device * pdev,struct of_regulator_match ** tps65910_reg_matches)998*4882a593Smuzhiyun static struct tps65910_board *tps65910_parse_dt_reg_data(
999*4882a593Smuzhiyun struct platform_device *pdev,
1000*4882a593Smuzhiyun struct of_regulator_match **tps65910_reg_matches)
1001*4882a593Smuzhiyun {
1002*4882a593Smuzhiyun struct tps65910_board *pmic_plat_data;
1003*4882a593Smuzhiyun struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
1004*4882a593Smuzhiyun struct device_node *np, *regulators;
1005*4882a593Smuzhiyun struct of_regulator_match *matches;
1006*4882a593Smuzhiyun unsigned int prop;
1007*4882a593Smuzhiyun int idx = 0, ret, count;
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data),
1010*4882a593Smuzhiyun GFP_KERNEL);
1011*4882a593Smuzhiyun if (!pmic_plat_data)
1012*4882a593Smuzhiyun return NULL;
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun np = pdev->dev.parent->of_node;
1015*4882a593Smuzhiyun regulators = of_get_child_by_name(np, "regulators");
1016*4882a593Smuzhiyun if (!regulators) {
1017*4882a593Smuzhiyun dev_err(&pdev->dev, "regulator node not found\n");
1018*4882a593Smuzhiyun return NULL;
1019*4882a593Smuzhiyun }
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun switch (tps65910_chip_id(tps65910)) {
1022*4882a593Smuzhiyun case TPS65910:
1023*4882a593Smuzhiyun count = ARRAY_SIZE(tps65910_matches);
1024*4882a593Smuzhiyun matches = tps65910_matches;
1025*4882a593Smuzhiyun break;
1026*4882a593Smuzhiyun case TPS65911:
1027*4882a593Smuzhiyun count = ARRAY_SIZE(tps65911_matches);
1028*4882a593Smuzhiyun matches = tps65911_matches;
1029*4882a593Smuzhiyun break;
1030*4882a593Smuzhiyun default:
1031*4882a593Smuzhiyun of_node_put(regulators);
1032*4882a593Smuzhiyun dev_err(&pdev->dev, "Invalid tps chip version\n");
1033*4882a593Smuzhiyun return NULL;
1034*4882a593Smuzhiyun }
1035*4882a593Smuzhiyun
1036*4882a593Smuzhiyun ret = of_regulator_match(&pdev->dev, regulators, matches, count);
1037*4882a593Smuzhiyun of_node_put(regulators);
1038*4882a593Smuzhiyun if (ret < 0) {
1039*4882a593Smuzhiyun dev_err(&pdev->dev, "Error parsing regulator init data: %d\n",
1040*4882a593Smuzhiyun ret);
1041*4882a593Smuzhiyun return NULL;
1042*4882a593Smuzhiyun }
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun *tps65910_reg_matches = matches;
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun for (idx = 0; idx < count; idx++) {
1047*4882a593Smuzhiyun if (!matches[idx].of_node)
1048*4882a593Smuzhiyun continue;
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun pmic_plat_data->tps65910_pmic_init_data[idx] =
1051*4882a593Smuzhiyun matches[idx].init_data;
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun ret = of_property_read_u32(matches[idx].of_node,
1054*4882a593Smuzhiyun "ti,regulator-ext-sleep-control", &prop);
1055*4882a593Smuzhiyun if (!ret)
1056*4882a593Smuzhiyun pmic_plat_data->regulator_ext_sleep_control[idx] = prop;
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun }
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun return pmic_plat_data;
1061*4882a593Smuzhiyun }
1062*4882a593Smuzhiyun #else
tps65910_parse_dt_reg_data(struct platform_device * pdev,struct of_regulator_match ** tps65910_reg_matches)1063*4882a593Smuzhiyun static inline struct tps65910_board *tps65910_parse_dt_reg_data(
1064*4882a593Smuzhiyun struct platform_device *pdev,
1065*4882a593Smuzhiyun struct of_regulator_match **tps65910_reg_matches)
1066*4882a593Smuzhiyun {
1067*4882a593Smuzhiyun *tps65910_reg_matches = NULL;
1068*4882a593Smuzhiyun return NULL;
1069*4882a593Smuzhiyun }
1070*4882a593Smuzhiyun #endif
1071*4882a593Smuzhiyun
tps65910_probe(struct platform_device * pdev)1072*4882a593Smuzhiyun static int tps65910_probe(struct platform_device *pdev)
1073*4882a593Smuzhiyun {
1074*4882a593Smuzhiyun struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
1075*4882a593Smuzhiyun struct regulator_config config = { };
1076*4882a593Smuzhiyun struct tps_info *info;
1077*4882a593Smuzhiyun struct regulator_dev *rdev;
1078*4882a593Smuzhiyun struct tps65910_reg *pmic;
1079*4882a593Smuzhiyun struct tps65910_board *pmic_plat_data;
1080*4882a593Smuzhiyun struct of_regulator_match *tps65910_reg_matches = NULL;
1081*4882a593Smuzhiyun int i, err;
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun pmic_plat_data = dev_get_platdata(tps65910->dev);
1084*4882a593Smuzhiyun if (!pmic_plat_data && tps65910->dev->of_node)
1085*4882a593Smuzhiyun pmic_plat_data = tps65910_parse_dt_reg_data(pdev,
1086*4882a593Smuzhiyun &tps65910_reg_matches);
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun if (!pmic_plat_data) {
1089*4882a593Smuzhiyun dev_err(&pdev->dev, "Platform data not found\n");
1090*4882a593Smuzhiyun return -EINVAL;
1091*4882a593Smuzhiyun }
1092*4882a593Smuzhiyun
1093*4882a593Smuzhiyun pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
1094*4882a593Smuzhiyun if (!pmic)
1095*4882a593Smuzhiyun return -ENOMEM;
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun pmic->mfd = tps65910;
1098*4882a593Smuzhiyun platform_set_drvdata(pdev, pmic);
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun /* Give control of all register to control port */
1101*4882a593Smuzhiyun err = regmap_set_bits(pmic->mfd->regmap, TPS65910_DEVCTRL,
1102*4882a593Smuzhiyun DEVCTRL_SR_CTL_I2C_SEL_MASK);
1103*4882a593Smuzhiyun if (err < 0)
1104*4882a593Smuzhiyun return err;
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun switch (tps65910_chip_id(tps65910)) {
1107*4882a593Smuzhiyun case TPS65910:
1108*4882a593Smuzhiyun BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65910_regs));
1109*4882a593Smuzhiyun pmic->get_ctrl_reg = &tps65910_get_ctrl_register;
1110*4882a593Smuzhiyun pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
1111*4882a593Smuzhiyun pmic->ext_sleep_control = tps65910_ext_sleep_control;
1112*4882a593Smuzhiyun info = tps65910_regs;
1113*4882a593Smuzhiyun /* Work around silicon erratum SWCZ010: output programmed
1114*4882a593Smuzhiyun * voltage level can go higher than expected or crash
1115*4882a593Smuzhiyun * Workaround: use no synchronization of DCDC clocks
1116*4882a593Smuzhiyun */
1117*4882a593Smuzhiyun regmap_clear_bits(pmic->mfd->regmap, TPS65910_DCDCCTRL,
1118*4882a593Smuzhiyun DCDCCTRL_DCDCCKSYNC_MASK);
1119*4882a593Smuzhiyun break;
1120*4882a593Smuzhiyun case TPS65911:
1121*4882a593Smuzhiyun BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65911_regs));
1122*4882a593Smuzhiyun pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
1123*4882a593Smuzhiyun pmic->num_regulators = ARRAY_SIZE(tps65911_regs);
1124*4882a593Smuzhiyun pmic->ext_sleep_control = tps65911_ext_sleep_control;
1125*4882a593Smuzhiyun info = tps65911_regs;
1126*4882a593Smuzhiyun break;
1127*4882a593Smuzhiyun default:
1128*4882a593Smuzhiyun dev_err(&pdev->dev, "Invalid tps chip version\n");
1129*4882a593Smuzhiyun return -ENODEV;
1130*4882a593Smuzhiyun }
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun pmic->desc = devm_kcalloc(&pdev->dev,
1133*4882a593Smuzhiyun pmic->num_regulators,
1134*4882a593Smuzhiyun sizeof(struct regulator_desc),
1135*4882a593Smuzhiyun GFP_KERNEL);
1136*4882a593Smuzhiyun if (!pmic->desc)
1137*4882a593Smuzhiyun return -ENOMEM;
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun pmic->info = devm_kcalloc(&pdev->dev,
1140*4882a593Smuzhiyun pmic->num_regulators,
1141*4882a593Smuzhiyun sizeof(struct tps_info *),
1142*4882a593Smuzhiyun GFP_KERNEL);
1143*4882a593Smuzhiyun if (!pmic->info)
1144*4882a593Smuzhiyun return -ENOMEM;
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun pmic->rdev = devm_kcalloc(&pdev->dev,
1147*4882a593Smuzhiyun pmic->num_regulators,
1148*4882a593Smuzhiyun sizeof(struct regulator_dev *),
1149*4882a593Smuzhiyun GFP_KERNEL);
1150*4882a593Smuzhiyun if (!pmic->rdev)
1151*4882a593Smuzhiyun return -ENOMEM;
1152*4882a593Smuzhiyun
1153*4882a593Smuzhiyun for (i = 0; i < pmic->num_regulators; i++, info++) {
1154*4882a593Smuzhiyun /* Register the regulators */
1155*4882a593Smuzhiyun pmic->info[i] = info;
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun pmic->desc[i].name = info->name;
1158*4882a593Smuzhiyun pmic->desc[i].supply_name = info->vin_name;
1159*4882a593Smuzhiyun pmic->desc[i].id = i;
1160*4882a593Smuzhiyun pmic->desc[i].n_voltages = info->n_voltages;
1161*4882a593Smuzhiyun pmic->desc[i].enable_time = info->enable_time_us;
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) {
1164*4882a593Smuzhiyun pmic->desc[i].ops = &tps65910_ops_dcdc;
1165*4882a593Smuzhiyun pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE *
1166*4882a593Smuzhiyun VDD1_2_NUM_VOLT_COARSE;
1167*4882a593Smuzhiyun pmic->desc[i].ramp_delay = 12500;
1168*4882a593Smuzhiyun } else if (i == TPS65910_REG_VDD3) {
1169*4882a593Smuzhiyun if (tps65910_chip_id(tps65910) == TPS65910) {
1170*4882a593Smuzhiyun pmic->desc[i].ops = &tps65910_ops_vdd3;
1171*4882a593Smuzhiyun pmic->desc[i].volt_table = info->voltage_table;
1172*4882a593Smuzhiyun } else {
1173*4882a593Smuzhiyun pmic->desc[i].ops = &tps65910_ops_dcdc;
1174*4882a593Smuzhiyun pmic->desc[i].ramp_delay = 5000;
1175*4882a593Smuzhiyun }
1176*4882a593Smuzhiyun } else if (i == TPS65910_REG_VBB &&
1177*4882a593Smuzhiyun tps65910_chip_id(tps65910) == TPS65910) {
1178*4882a593Smuzhiyun pmic->desc[i].ops = &tps65910_ops_vbb;
1179*4882a593Smuzhiyun pmic->desc[i].volt_table = info->voltage_table;
1180*4882a593Smuzhiyun } else {
1181*4882a593Smuzhiyun if (tps65910_chip_id(tps65910) == TPS65910) {
1182*4882a593Smuzhiyun pmic->desc[i].ops = &tps65910_ops;
1183*4882a593Smuzhiyun pmic->desc[i].volt_table = info->voltage_table;
1184*4882a593Smuzhiyun } else {
1185*4882a593Smuzhiyun pmic->desc[i].ops = &tps65911_ops;
1186*4882a593Smuzhiyun }
1187*4882a593Smuzhiyun }
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun err = tps65910_set_ext_sleep_config(pmic, i,
1190*4882a593Smuzhiyun pmic_plat_data->regulator_ext_sleep_control[i]);
1191*4882a593Smuzhiyun /*
1192*4882a593Smuzhiyun * Failing on regulator for configuring externally control
1193*4882a593Smuzhiyun * is not a serious issue, just throw warning.
1194*4882a593Smuzhiyun */
1195*4882a593Smuzhiyun if (err < 0)
1196*4882a593Smuzhiyun dev_warn(tps65910->dev,
1197*4882a593Smuzhiyun "Failed to initialise ext control config\n");
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun pmic->desc[i].type = REGULATOR_VOLTAGE;
1200*4882a593Smuzhiyun pmic->desc[i].owner = THIS_MODULE;
1201*4882a593Smuzhiyun pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i);
1202*4882a593Smuzhiyun pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED;
1203*4882a593Smuzhiyun
1204*4882a593Smuzhiyun config.dev = tps65910->dev;
1205*4882a593Smuzhiyun config.init_data = pmic_plat_data->tps65910_pmic_init_data[i];
1206*4882a593Smuzhiyun config.driver_data = pmic;
1207*4882a593Smuzhiyun config.regmap = tps65910->regmap;
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun if (tps65910_reg_matches)
1210*4882a593Smuzhiyun config.of_node = tps65910_reg_matches[i].of_node;
1211*4882a593Smuzhiyun
1212*4882a593Smuzhiyun rdev = devm_regulator_register(&pdev->dev, &pmic->desc[i],
1213*4882a593Smuzhiyun &config);
1214*4882a593Smuzhiyun if (IS_ERR(rdev))
1215*4882a593Smuzhiyun return dev_err_probe(tps65910->dev, PTR_ERR(rdev),
1216*4882a593Smuzhiyun "failed to register %s regulator\n",
1217*4882a593Smuzhiyun pdev->name);
1218*4882a593Smuzhiyun
1219*4882a593Smuzhiyun /* Save regulator for cleanup */
1220*4882a593Smuzhiyun pmic->rdev[i] = rdev;
1221*4882a593Smuzhiyun }
1222*4882a593Smuzhiyun return 0;
1223*4882a593Smuzhiyun }
1224*4882a593Smuzhiyun
tps65910_shutdown(struct platform_device * pdev)1225*4882a593Smuzhiyun static void tps65910_shutdown(struct platform_device *pdev)
1226*4882a593Smuzhiyun {
1227*4882a593Smuzhiyun struct tps65910_reg *pmic = platform_get_drvdata(pdev);
1228*4882a593Smuzhiyun int i;
1229*4882a593Smuzhiyun
1230*4882a593Smuzhiyun /*
1231*4882a593Smuzhiyun * Before bootloader jumps to kernel, it makes sure that required
1232*4882a593Smuzhiyun * external control signals are in desired state so that given rails
1233*4882a593Smuzhiyun * can be configure accordingly.
1234*4882a593Smuzhiyun * If rails are configured to be controlled from external control
1235*4882a593Smuzhiyun * then before shutting down/rebooting the system, the external
1236*4882a593Smuzhiyun * control configuration need to be remove from the rails so that
1237*4882a593Smuzhiyun * its output will be available as per register programming even
1238*4882a593Smuzhiyun * if external controls are removed. This is require when the POR
1239*4882a593Smuzhiyun * value of the control signals are not in active state and before
1240*4882a593Smuzhiyun * bootloader initializes it, the system requires the rail output
1241*4882a593Smuzhiyun * to be active for booting.
1242*4882a593Smuzhiyun */
1243*4882a593Smuzhiyun for (i = 0; i < pmic->num_regulators; i++) {
1244*4882a593Smuzhiyun int err;
1245*4882a593Smuzhiyun if (!pmic->rdev[i])
1246*4882a593Smuzhiyun continue;
1247*4882a593Smuzhiyun
1248*4882a593Smuzhiyun err = tps65910_set_ext_sleep_config(pmic, i, 0);
1249*4882a593Smuzhiyun if (err < 0)
1250*4882a593Smuzhiyun dev_err(&pdev->dev,
1251*4882a593Smuzhiyun "Error in clearing external control\n");
1252*4882a593Smuzhiyun }
1253*4882a593Smuzhiyun }
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun static struct platform_driver tps65910_driver = {
1256*4882a593Smuzhiyun .driver = {
1257*4882a593Smuzhiyun .name = "tps65910-pmic",
1258*4882a593Smuzhiyun },
1259*4882a593Smuzhiyun .probe = tps65910_probe,
1260*4882a593Smuzhiyun .shutdown = tps65910_shutdown,
1261*4882a593Smuzhiyun };
1262*4882a593Smuzhiyun
tps65910_init(void)1263*4882a593Smuzhiyun static int __init tps65910_init(void)
1264*4882a593Smuzhiyun {
1265*4882a593Smuzhiyun return platform_driver_register(&tps65910_driver);
1266*4882a593Smuzhiyun }
1267*4882a593Smuzhiyun subsys_initcall(tps65910_init);
1268*4882a593Smuzhiyun
tps65910_cleanup(void)1269*4882a593Smuzhiyun static void __exit tps65910_cleanup(void)
1270*4882a593Smuzhiyun {
1271*4882a593Smuzhiyun platform_driver_unregister(&tps65910_driver);
1272*4882a593Smuzhiyun }
1273*4882a593Smuzhiyun module_exit(tps65910_cleanup);
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1276*4882a593Smuzhiyun MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver");
1277*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1278*4882a593Smuzhiyun MODULE_ALIAS("platform:tps65910-pmic");
1279