clk/rockchip/clk_rk3568.c

78 	[VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3568_PLL_CON(40),
1799 		parent = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL],  in rk3568_dclk_vop_get_clk()
1800 					       priv->cru, VPLL);  in rk3568_dclk_vop_get_clk()
1850 		rockchip_pll_set_rate(&rk3568_pll_clks[VPLL],  in rk3568_dclk_vop_set_clk()
1851 				      priv->cru, VPLL, div * rate);  in rk3568_dclk_vop_set_clk()
2532 		rate = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], priv->cru,  in rk3568_clk_get_rate()
2533 					     VPLL);  in rk3568_clk_get_rate()
2719 		ret = rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], priv->cru,  in rk3568_clk_set_rate()
2720 					    VPLL, rate);  in rk3568_clk_set_rate()
2721 		priv->vpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL],  in rk3568_clk_set_rate()
2723 						      VPLL);  in rk3568_clk_set_rate()