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Searched refs:MDIO_DEVAD_NONE (Results 1 – 25 of 64) sorted by relevance

123

/OK3568_Linux_fs/u-boot/drivers/net/phy/
H A Dmarvell.c111 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
113 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in m88e1011s_config()
114 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); in m88e1011s_config()
115 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in m88e1011s_config()
116 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); in m88e1011s_config()
117 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in m88e1011s_config()
119 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
134 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); in m88e1xxx_parse_status()
152 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1xxx_parse_status()
204 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); in m88e1111s_config()
[all …]
H A Drk630phy.c132 phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in rk630_phy_startup()
139 phy_write(phydev, 0, MDIO_DEVAD_NONE, in rk630_phy_s40_config_init()
140 phy_read(phydev, MDIO_DEVAD_NONE, 0) & ~BIT(13)); in rk630_phy_s40_config_init()
143 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0100); in rk630_phy_s40_config_init()
145 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE1_APS_CTRL, 0x4824); in rk630_phy_s40_config_init()
147 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0200); in rk630_phy_s40_config_init()
149 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE2_AFE_CTRL, 0x0000); in rk630_phy_s40_config_init()
151 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0600); in rk630_phy_s40_config_init()
153 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_TX_CTRL, 0x708f); in rk630_phy_s40_config_init()
155 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_RX_CTRL, 0xf000); in rk630_phy_s40_config_init()
[all …]
H A Dvitesse.c73 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in vitesse_config()
76 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1, in vitesse_config()
89 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT); in vitesse_parse_status()
125 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in cis8204_config()
131 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
135 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
149 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL); in vsc8601_add_skew()
154 return phy_write(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL, ret); in vsc8601_add_skew()
174 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8574_config()
177 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19); in vsc8574_config()
[all …]
H A Dmscc.c142 phy_write(phydev, MDIO_DEVAD_NONE, in mscc_vsc8531_vsc8541_init_scripts()
147 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
149 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
154 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
155 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
160 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
163 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
168 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
169 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
174 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
[all …]
H A Dbroadcom.c43 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm_phy_write_misc()
46 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm_phy_write_misc()
48 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); in bcm_phy_write_misc()
51 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); in bcm_phy_write_misc()
53 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); in bcm_phy_write_misc()
70 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS); in bcm54xx_parse_status()
130 return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010; in bcm5482_read_wirespeed()
138 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in bcm5482_config()
140 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in bcm5482_config()
143 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm5482_config()
[all …]
H A Datheros.c22 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in ar8021_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); in ar8021_config()
33 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
41 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
43 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
59 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); in ar8035_config()
60 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8035_config()
61 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8035_config()
62 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8035_config()
[all …]
H A Drealtek.c66 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211x_config()
71 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, in rtl8211x_config()
77 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in rtl8211x_config()
82 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); in rtl8211x_config()
85 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); in rtl8211x_config()
96 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211f_config()
98 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
100 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11); in rtl8211f_config()
109 phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg); in rtl8211f_config()
111 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
[all …]
H A Dmicrel_ksz90x1.c54 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); in ksz90xx_startup()
222 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
224 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
231 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum); in ksz9021_phy_extended_read()
232 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); in ksz9021_phy_extended_read()
270 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000); in ksz9021_config()
295 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
298 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
301 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
304 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
[all …]
H A Dphy.c49 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); in genphy_config_advert()
75 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv); in genphy_config_advert()
82 bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_config_advert()
94 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in genphy_config_advert()
113 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv); in genphy_config_advert()
143 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_setup_forced()
157 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_restart_aneg()
167 ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_restart_aneg()
196 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_config_aneg()
229 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
[all …]
H A Dnatsemi.c22 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp83630_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6); in dp83630_config()
24 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE, in dp83630_config()
27 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG, in dp83630_config()
29 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0); in dp83630_config()
58 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp838xx_config()
68 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR); in dp83865_parse_status()
121 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in dp83848_parse_status()
H A Det1011c.c31 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
37 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
47 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); in et1011c_parse_status()
58 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); in et1011c_parse_status()
60 phy_write(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG, in et1011c_parse_status()
H A Dmicrel_ksz8xxx.c37 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO); in ksz_genconfig_bcastoff()
41 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO, in ksz_genconfig_bcastoff()
70 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO); in ksz8051_config()
72 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val); in ksz8051_config()
113 phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE, in ksz8895_write_smireg()
121 MDIO_DEVAD_NONE, smireg_to_reg(smireg));
H A Ddavicom.c29 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE); in dm9161_config()
31 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR, in dm9161_config()
34 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR, in dm9161_config()
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR); in dm9161_parse_status()
H A Dti.c232 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); in dp83867_config()
233 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, in dp83867_config()
237 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, in dp83867_config()
243 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, in dp83867_config()
253 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2); in dp83867_config()
258 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, in dp83867_config()
264 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0); in dp83867_config()
H A Dxilinx_phy.c50 status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in xilinxphy_startup()
72 int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_startup()
121 temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_config()
123 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp); in xilinxphy_config()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/chelsio/cxgb3/
H A Dvsc8211.c94 return t3_phy_reset(cphy, MDIO_DEVAD_NONE, 0); in vsc8211_reset()
99 return t3_mdio_write(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_ENABLE, in vsc8211_intr_enable()
105 return t3_mdio_write(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_ENABLE, 0); in vsc8211_intr_disable()
113 return t3_mdio_read(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_STATUS, &val); in vsc8211_intr_clear()
118 return t3_mdio_change_bits(cphy, MDIO_DEVAD_NONE, MII_BMCR, in vsc8211_autoneg_enable()
125 return t3_mdio_change_bits(cphy, MDIO_DEVAD_NONE, MII_BMCR, in vsc8211_autoneg_restart()
136 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMCR, &bmcr); in vsc8211_get_link_status()
138 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMSR, &status); in vsc8211_get_link_status()
148 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMSR, in vsc8211_get_link_status()
163 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, VSC8211_AUX_CTRL_STAT, in vsc8211_get_link_status()
[all …]
/OK3568_Linux_fs/u-boot/board/spear/x600/
H A Dx600.c77 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_phy_config()
78 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_phy_config()
84 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); in board_phy_config()
111 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); in board_phy_config()
117 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); in board_phy_config()
120 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
121 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
124 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); in board_phy_config()
127 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); in board_phy_config()
130 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); in board_phy_config()
/OK3568_Linux_fs/u-boot/board/congatec/cgtqmx6eval/
H A Dcgtqmx6eval.c282 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_eth_init()
283 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_eth_init()
331 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in mx6_rgmii_rework()
332 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in mx6_rgmii_rework()
336 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
337 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4); in mx6_rgmii_rework()
338 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); in mx6_rgmii_rework()
339 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000); in mx6_rgmii_rework()
341 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
342 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5); in mx6_rgmii_rework()
[all …]
/OK3568_Linux_fs/u-boot/board/Marvell/db-mv784mp-gp/
H A Ddb-mv784mp-gp.c96 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4); in board_phy_config()
98 phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140); in board_phy_config()
100 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0); in board_phy_config()
103 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4); in board_phy_config()
105 phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg); in board_phy_config()
108 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); in board_phy_config()
109 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); in board_phy_config()
112 reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG); in board_phy_config()
114 phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg); in board_phy_config()
/OK3568_Linux_fs/u-boot/board/gdsys/a38x/
H A Dihs_phys.c32 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0004); in ihs_phy_config()
33 reg = phy_read(phydev, MDIO_DEVAD_NONE, 16); in ihs_phy_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, 16, reg); in ihs_phy_config()
41 reg = phy_read(phydev, MDIO_DEVAD_NONE, 26); in ihs_phy_config()
47 phy_write(phydev, MDIO_DEVAD_NONE, 26, reg); in ihs_phy_config()
50 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); in ihs_phy_config()
51 reg = phy_read(phydev, MDIO_DEVAD_NONE, 4); in ihs_phy_config()
53 phy_write(phydev, MDIO_DEVAD_NONE, 4, reg); in ihs_phy_config()
54 reg = phy_read(phydev, MDIO_DEVAD_NONE, 9); in ihs_phy_config()
56 phy_write(phydev, MDIO_DEVAD_NONE, 9, reg); in ihs_phy_config()
[all …]
/OK3568_Linux_fs/u-boot/board/technexion/pico-imx7d/
H A Dpico-imx7d.c193 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in board_phy_config()
194 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in board_phy_config()
195 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in board_phy_config()
197 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in board_phy_config()
200 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in board_phy_config()
203 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in board_phy_config()
204 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in board_phy_config()
206 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in board_phy_config()
/OK3568_Linux_fs/u-boot/board/compulab/cm_fx6/
H A Dcm_fx6.c414 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); in mx6_rgmii_rework()
415 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); in mx6_rgmii_rework()
416 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); in mx6_rgmii_rework()
417 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in mx6_rgmii_rework()
419 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in mx6_rgmii_rework()
422 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in mx6_rgmii_rework()
423 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in mx6_rgmii_rework()
424 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in mx6_rgmii_rework()
426 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in mx6_rgmii_rework()
429 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in mx6_rgmii_rework()
[all …]
/OK3568_Linux_fs/u-boot/board/tbs/tbs2910/
H A Dtbs2910.c367 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in ar8035_phy_fixup()
368 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8035_phy_fixup()
369 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8035_phy_fixup()
371 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8035_phy_fixup()
374 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in ar8035_phy_fixup()
377 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in ar8035_phy_fixup()
378 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in ar8035_phy_fixup()
380 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in ar8035_phy_fixup()
/OK3568_Linux_fs/u-boot/board/wandboard/
H A Dwandboard.c197 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in ar8031_phy_fixup()
198 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8031_phy_fixup()
199 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8031_phy_fixup()
201 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8031_phy_fixup()
204 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in ar8031_phy_fixup()
207 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in ar8031_phy_fixup()
208 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in ar8031_phy_fixup()
210 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in ar8031_phy_fixup()
/OK3568_Linux_fs/u-boot/include/
H A Dphy.h181 phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad); in phy_mmd_start_indirect()
184 phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum); in phy_mmd_start_indirect()
187 phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, in phy_mmd_start_indirect()
205 devad == MDIO_DEVAD_NONE || !devad) in phy_read_mmd()
212 return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA); in phy_read_mmd()
229 devad == MDIO_DEVAD_NONE || !devad) in phy_write_mmd()
236 return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val); in phy_write_mmd()

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