1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Xilinx PCS/PMA Core phy driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2015 - 2016 Xilinx, Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <config.h>
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <phy.h>
12*4882a593Smuzhiyun #include <dm.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define MII_PHY_STATUS_SPD_MASK 0x0C00
17*4882a593Smuzhiyun #define MII_PHY_STATUS_FULLDUPLEX 0x1000
18*4882a593Smuzhiyun #define MII_PHY_STATUS_1000 0x0800
19*4882a593Smuzhiyun #define MII_PHY_STATUS_100 0x0400
20*4882a593Smuzhiyun #define XPCSPMA_PHY_CTRL_ISOLATE_DISABLE 0xFBFF
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* Mask used for ID comparisons */
23*4882a593Smuzhiyun #define XILINX_PHY_ID_MASK 0xfffffff0
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Known PHY IDs */
26*4882a593Smuzhiyun #define XILINX_PHY_ID 0x01740c00
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* struct phy_device dev_flags definitions */
29*4882a593Smuzhiyun #define XAE_PHY_TYPE_MII 0
30*4882a593Smuzhiyun #define XAE_PHY_TYPE_GMII 1
31*4882a593Smuzhiyun #define XAE_PHY_TYPE_RGMII_1_3 2
32*4882a593Smuzhiyun #define XAE_PHY_TYPE_RGMII_2_0 3
33*4882a593Smuzhiyun #define XAE_PHY_TYPE_SGMII 4
34*4882a593Smuzhiyun #define XAE_PHY_TYPE_1000BASE_X 5
35*4882a593Smuzhiyun
xilinxphy_startup(struct phy_device * phydev)36*4882a593Smuzhiyun static int xilinxphy_startup(struct phy_device *phydev)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun int err;
39*4882a593Smuzhiyun int status = 0;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun debug("%s\n", __func__);
42*4882a593Smuzhiyun /* Update the link, but return if there
43*4882a593Smuzhiyun * was an error
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun err = genphy_update_link(phydev);
46*4882a593Smuzhiyun if (err)
47*4882a593Smuzhiyun return err;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (AUTONEG_ENABLE == phydev->autoneg) {
50*4882a593Smuzhiyun status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
51*4882a593Smuzhiyun status = status & MII_PHY_STATUS_SPD_MASK;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun if (status & MII_PHY_STATUS_FULLDUPLEX)
54*4882a593Smuzhiyun phydev->duplex = DUPLEX_FULL;
55*4882a593Smuzhiyun else
56*4882a593Smuzhiyun phydev->duplex = DUPLEX_HALF;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun switch (status) {
59*4882a593Smuzhiyun case MII_PHY_STATUS_1000:
60*4882a593Smuzhiyun phydev->speed = SPEED_1000;
61*4882a593Smuzhiyun break;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun case MII_PHY_STATUS_100:
64*4882a593Smuzhiyun phydev->speed = SPEED_100;
65*4882a593Smuzhiyun break;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun default:
68*4882a593Smuzhiyun phydev->speed = SPEED_10;
69*4882a593Smuzhiyun break;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun } else {
72*4882a593Smuzhiyun int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if (bmcr < 0)
75*4882a593Smuzhiyun return bmcr;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (bmcr & BMCR_FULLDPLX)
78*4882a593Smuzhiyun phydev->duplex = DUPLEX_FULL;
79*4882a593Smuzhiyun else
80*4882a593Smuzhiyun phydev->duplex = DUPLEX_HALF;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if (bmcr & BMCR_SPEED1000)
83*4882a593Smuzhiyun phydev->speed = SPEED_1000;
84*4882a593Smuzhiyun else if (bmcr & BMCR_SPEED100)
85*4882a593Smuzhiyun phydev->speed = SPEED_100;
86*4882a593Smuzhiyun else
87*4882a593Smuzhiyun phydev->speed = SPEED_10;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun * For 1000BASE-X Phy Mode the speed/duplex will always be
92*4882a593Smuzhiyun * 1000Mbps/fullduplex
93*4882a593Smuzhiyun */
94*4882a593Smuzhiyun if (phydev->flags == XAE_PHY_TYPE_1000BASE_X) {
95*4882a593Smuzhiyun phydev->duplex = DUPLEX_FULL;
96*4882a593Smuzhiyun phydev->speed = SPEED_1000;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return 0;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
xilinxphy_of_init(struct phy_device * phydev)102*4882a593Smuzhiyun static int xilinxphy_of_init(struct phy_device *phydev)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun u32 phytype;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun debug("%s\n", __func__);
107*4882a593Smuzhiyun phytype = fdtdec_get_int(gd->fdt_blob, dev_of_offset(phydev->dev),
108*4882a593Smuzhiyun "phy-type", -1);
109*4882a593Smuzhiyun if (phytype == XAE_PHY_TYPE_1000BASE_X)
110*4882a593Smuzhiyun phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun return 0;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
xilinxphy_config(struct phy_device * phydev)115*4882a593Smuzhiyun static int xilinxphy_config(struct phy_device *phydev)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun int temp;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun debug("%s\n", __func__);
120*4882a593Smuzhiyun xilinxphy_of_init(phydev);
121*4882a593Smuzhiyun temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
122*4882a593Smuzhiyun temp &= XPCSPMA_PHY_CTRL_ISOLATE_DISABLE;
123*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun return 0;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun static struct phy_driver xilinxphy_driver = {
129*4882a593Smuzhiyun .uid = XILINX_PHY_ID,
130*4882a593Smuzhiyun .mask = XILINX_PHY_ID_MASK,
131*4882a593Smuzhiyun .name = "Xilinx PCS/PMA PHY",
132*4882a593Smuzhiyun .features = PHY_GBIT_FEATURES,
133*4882a593Smuzhiyun .config = &xilinxphy_config,
134*4882a593Smuzhiyun .startup = &xilinxphy_startup,
135*4882a593Smuzhiyun .shutdown = &genphy_shutdown,
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
phy_xilinx_init(void)138*4882a593Smuzhiyun int phy_xilinx_init(void)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun debug("%s\n", __func__);
141*4882a593Smuzhiyun phy_register(&xilinxphy_driver);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun return 0;
144*4882a593Smuzhiyun }
145