1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <miiphy.h>
9*4882a593Smuzhiyun #include <netdev.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/arch/cpu.h>
12*4882a593Smuzhiyun #include <asm/arch/soc.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define ETH_PHY_CTRL_REG 0
17*4882a593Smuzhiyun #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
18*4882a593Smuzhiyun #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * Those values and defines are taken from the Marvell U-Boot version
22*4882a593Smuzhiyun * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
23*4882a593Smuzhiyun * "RD-AXP-GP rev 1.0".
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * GPPs
26*4882a593Smuzhiyun * MPP# NAME IN/OUT
27*4882a593Smuzhiyun * ----------------------------------------------
28*4882a593Smuzhiyun * 21 SW_Reset_ OUT
29*4882a593Smuzhiyun * 25 Phy_Int# IN
30*4882a593Smuzhiyun * 28 SDI_WP IN
31*4882a593Smuzhiyun * 29 SDI_Status IN
32*4882a593Smuzhiyun * 54-61 On GPP Connector ?
33*4882a593Smuzhiyun * 62 Switch Interrupt IN
34*4882a593Smuzhiyun * 63-65 Reserved from SW Board ?
35*4882a593Smuzhiyun * 66 SW_BRD connected IN
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun #define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20)))
38*4882a593Smuzhiyun #define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27)))
39*4882a593Smuzhiyun #define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0))
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20))
42*4882a593Smuzhiyun #define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
43*4882a593Smuzhiyun #define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0
44*4882a593Smuzhiyun
board_early_init_f(void)45*4882a593Smuzhiyun int board_early_init_f(void)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun /* Configure MPP */
48*4882a593Smuzhiyun writel(0x00000000, MVEBU_MPP_BASE + 0x00);
49*4882a593Smuzhiyun writel(0x00000000, MVEBU_MPP_BASE + 0x04);
50*4882a593Smuzhiyun writel(0x33000000, MVEBU_MPP_BASE + 0x08);
51*4882a593Smuzhiyun writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
52*4882a593Smuzhiyun writel(0x11111111, MVEBU_MPP_BASE + 0x10);
53*4882a593Smuzhiyun writel(0x00221100, MVEBU_MPP_BASE + 0x14);
54*4882a593Smuzhiyun writel(0x00000003, MVEBU_MPP_BASE + 0x18);
55*4882a593Smuzhiyun writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
56*4882a593Smuzhiyun writel(0x00000000, MVEBU_MPP_BASE + 0x20);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Configure GPIO */
59*4882a593Smuzhiyun writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
60*4882a593Smuzhiyun writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
61*4882a593Smuzhiyun writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
62*4882a593Smuzhiyun writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
63*4882a593Smuzhiyun writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
64*4882a593Smuzhiyun writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun return 0;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
board_init(void)69*4882a593Smuzhiyun int board_init(void)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun /* adress of boot parameters */
72*4882a593Smuzhiyun gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
checkboard(void)77*4882a593Smuzhiyun int checkboard(void)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun puts("Board: Marvell DB-MV784MP-GP\n");
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
board_eth_init(bd_t * bis)84*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun cpu_eth_init(bis); /* Built in controller(s) come first */
87*4882a593Smuzhiyun return pci_eth_init(bis);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
board_phy_config(struct phy_device * phydev)90*4882a593Smuzhiyun int board_phy_config(struct phy_device *phydev)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun u16 reg;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Enable QSGMII AN */
95*4882a593Smuzhiyun /* Set page to 4 */
96*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
97*4882a593Smuzhiyun /* Enable AN */
98*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
99*4882a593Smuzhiyun /* Set page to 0 */
100*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* Phy C_ANEG */
103*4882a593Smuzhiyun reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
104*4882a593Smuzhiyun reg |= 0x1E0;
105*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Soft-Reset */
108*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
109*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Power up the phy */
112*4882a593Smuzhiyun reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
113*4882a593Smuzhiyun reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
114*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun printf("88E1545 Initialized\n");
117*4882a593Smuzhiyun return 0;
118*4882a593Smuzhiyun }
119