1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Davicom PHY drivers
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright 2010-2011 Freescale Semiconductor, Inc.
7*4882a593Smuzhiyun * author Andy Fleming
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <phy.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define MIIM_DM9161_SCR 0x10
12*4882a593Smuzhiyun #define MIIM_DM9161_SCR_INIT 0x0610
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /* DM9161 Specified Configuration and Status Register */
15*4882a593Smuzhiyun #define MIIM_DM9161_SCSR 0x11
16*4882a593Smuzhiyun #define MIIM_DM9161_SCSR_100F 0x8000
17*4882a593Smuzhiyun #define MIIM_DM9161_SCSR_100H 0x4000
18*4882a593Smuzhiyun #define MIIM_DM9161_SCSR_10F 0x2000
19*4882a593Smuzhiyun #define MIIM_DM9161_SCSR_10H 0x1000
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* DM9161 10BT Configuration/Status */
22*4882a593Smuzhiyun #define MIIM_DM9161_10BTCSR 0x12
23*4882a593Smuzhiyun #define MIIM_DM9161_10BTCSR_INIT 0x7800
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Davicom DM9161E */
dm9161_config(struct phy_device * phydev)27*4882a593Smuzhiyun static int dm9161_config(struct phy_device *phydev)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE);
30*4882a593Smuzhiyun /* Do not bypass the scrambler/descrambler */
31*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR,
32*4882a593Smuzhiyun MIIM_DM9161_SCR_INIT);
33*4882a593Smuzhiyun /* Clear 10BTCSR to default */
34*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR,
35*4882a593Smuzhiyun MIIM_DM9161_10BTCSR_INIT);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun genphy_config_aneg(phydev);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return 0;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
dm9161_parse_status(struct phy_device * phydev)42*4882a593Smuzhiyun static int dm9161_parse_status(struct phy_device *phydev)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun int mii_reg;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
49*4882a593Smuzhiyun phydev->speed = SPEED_100;
50*4882a593Smuzhiyun else
51*4882a593Smuzhiyun phydev->speed = SPEED_10;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
54*4882a593Smuzhiyun phydev->duplex = DUPLEX_FULL;
55*4882a593Smuzhiyun else
56*4882a593Smuzhiyun phydev->duplex = DUPLEX_HALF;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return 0;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
dm9161_startup(struct phy_device * phydev)61*4882a593Smuzhiyun static int dm9161_startup(struct phy_device *phydev)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun int ret;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun ret = genphy_update_link(phydev);
66*4882a593Smuzhiyun if (ret)
67*4882a593Smuzhiyun return ret;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return dm9161_parse_status(phydev);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static struct phy_driver DM9161_driver = {
73*4882a593Smuzhiyun .name = "Davicom DM9161E",
74*4882a593Smuzhiyun .uid = 0x181b880,
75*4882a593Smuzhiyun .mask = 0xffffff0,
76*4882a593Smuzhiyun .features = PHY_BASIC_FEATURES,
77*4882a593Smuzhiyun .config = &dm9161_config,
78*4882a593Smuzhiyun .startup = &dm9161_startup,
79*4882a593Smuzhiyun .shutdown = &genphy_shutdown,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
phy_davicom_init(void)82*4882a593Smuzhiyun int phy_davicom_init(void)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun phy_register(&DM9161_driver);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return 0;
87*4882a593Smuzhiyun }
88