1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * National Semiconductor PHY drivers
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright 2010-2011 Freescale Semiconductor, Inc.
7*4882a593Smuzhiyun * author Andy Fleming
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <phy.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /* NatSemi DP83630 */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define DP83630_PHY_PAGESEL_REG 0x13
14*4882a593Smuzhiyun #define DP83630_PHY_PTP_COC_REG 0x14
15*4882a593Smuzhiyun #define DP83630_PHY_PTP_CLKOUT_EN (1<<15)
16*4882a593Smuzhiyun #define DP83630_PHY_RBR_REG 0x17
17*4882a593Smuzhiyun
dp83630_config(struct phy_device * phydev)18*4882a593Smuzhiyun static int dp83630_config(struct phy_device *phydev)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun int ptp_coc_reg;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
23*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6);
24*4882a593Smuzhiyun ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE,
25*4882a593Smuzhiyun DP83630_PHY_PTP_COC_REG);
26*4882a593Smuzhiyun ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN;
27*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG,
28*4882a593Smuzhiyun ptp_coc_reg);
29*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun genphy_config_aneg(phydev);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun return 0;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun static struct phy_driver DP83630_driver = {
37*4882a593Smuzhiyun .name = "NatSemi DP83630",
38*4882a593Smuzhiyun .uid = 0x20005ce1,
39*4882a593Smuzhiyun .mask = 0xfffffff0,
40*4882a593Smuzhiyun .features = PHY_BASIC_FEATURES,
41*4882a593Smuzhiyun .config = &dp83630_config,
42*4882a593Smuzhiyun .startup = &genphy_startup,
43*4882a593Smuzhiyun .shutdown = &genphy_shutdown,
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* DP83865 Link and Auto-Neg Status Register */
48*4882a593Smuzhiyun #define MIIM_DP83865_LANR 0x11
49*4882a593Smuzhiyun #define MIIM_DP83865_SPD_MASK 0x0018
50*4882a593Smuzhiyun #define MIIM_DP83865_SPD_1000 0x0010
51*4882a593Smuzhiyun #define MIIM_DP83865_SPD_100 0x0008
52*4882a593Smuzhiyun #define MIIM_DP83865_DPX_FULL 0x0002
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* NatSemi DP83865 */
dp838xx_config(struct phy_device * phydev)56*4882a593Smuzhiyun static int dp838xx_config(struct phy_device *phydev)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
59*4882a593Smuzhiyun genphy_config_aneg(phydev);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
dp83865_parse_status(struct phy_device * phydev)64*4882a593Smuzhiyun static int dp83865_parse_status(struct phy_device *phydev)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun int mii_reg;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun switch (mii_reg & MIIM_DP83865_SPD_MASK) {
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun case MIIM_DP83865_SPD_1000:
73*4882a593Smuzhiyun phydev->speed = SPEED_1000;
74*4882a593Smuzhiyun break;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun case MIIM_DP83865_SPD_100:
77*4882a593Smuzhiyun phydev->speed = SPEED_100;
78*4882a593Smuzhiyun break;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun default:
81*4882a593Smuzhiyun phydev->speed = SPEED_10;
82*4882a593Smuzhiyun break;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun if (mii_reg & MIIM_DP83865_DPX_FULL)
87*4882a593Smuzhiyun phydev->duplex = DUPLEX_FULL;
88*4882a593Smuzhiyun else
89*4882a593Smuzhiyun phydev->duplex = DUPLEX_HALF;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
dp83865_startup(struct phy_device * phydev)94*4882a593Smuzhiyun static int dp83865_startup(struct phy_device *phydev)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun int ret;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun ret = genphy_update_link(phydev);
99*4882a593Smuzhiyun if (ret)
100*4882a593Smuzhiyun return ret;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return dp83865_parse_status(phydev);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun static struct phy_driver DP83865_driver = {
107*4882a593Smuzhiyun .name = "NatSemi DP83865",
108*4882a593Smuzhiyun .uid = 0x20005c70,
109*4882a593Smuzhiyun .mask = 0xfffffff0,
110*4882a593Smuzhiyun .features = PHY_GBIT_FEATURES,
111*4882a593Smuzhiyun .config = &dp838xx_config,
112*4882a593Smuzhiyun .startup = &dp83865_startup,
113*4882a593Smuzhiyun .shutdown = &genphy_shutdown,
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /* NatSemi DP83848 */
dp83848_parse_status(struct phy_device * phydev)117*4882a593Smuzhiyun static int dp83848_parse_status(struct phy_device *phydev)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun int mii_reg;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun if(mii_reg & (BMSR_100FULL | BMSR_100HALF)) {
124*4882a593Smuzhiyun phydev->speed = SPEED_100;
125*4882a593Smuzhiyun } else {
126*4882a593Smuzhiyun phydev->speed = SPEED_10;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun if (mii_reg & (BMSR_10FULL | BMSR_100FULL)) {
130*4882a593Smuzhiyun phydev->duplex = DUPLEX_FULL;
131*4882a593Smuzhiyun } else {
132*4882a593Smuzhiyun phydev->duplex = DUPLEX_HALF;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
dp83848_startup(struct phy_device * phydev)138*4882a593Smuzhiyun static int dp83848_startup(struct phy_device *phydev)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun int ret;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun ret = genphy_update_link(phydev);
143*4882a593Smuzhiyun if (ret)
144*4882a593Smuzhiyun return ret;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun return dp83848_parse_status(phydev);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun static struct phy_driver DP83848_driver = {
150*4882a593Smuzhiyun .name = "NatSemi DP83848",
151*4882a593Smuzhiyun .uid = 0x20005c90,
152*4882a593Smuzhiyun .mask = 0x2000ff90,
153*4882a593Smuzhiyun .features = PHY_BASIC_FEATURES,
154*4882a593Smuzhiyun .config = &dp838xx_config,
155*4882a593Smuzhiyun .startup = &dp83848_startup,
156*4882a593Smuzhiyun .shutdown = &genphy_shutdown,
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun
phy_natsemi_init(void)159*4882a593Smuzhiyun int phy_natsemi_init(void)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun phy_register(&DP83630_driver);
162*4882a593Smuzhiyun phy_register(&DP83865_driver);
163*4882a593Smuzhiyun phy_register(&DP83848_driver);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun return 0;
166*4882a593Smuzhiyun }
167