| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 112 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3328_PLL_CON(24),
788 priv->gpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[GPLL], in rk3328_clk_get_rate()
789 priv->cru, GPLL); in rk3328_clk_get_rate()
885 ret = rockchip_pll_set_rate(&rk3328_pll_clks[GPLL], in rk3328_clk_set_rate()
886 priv->cru, GPLL, rate); in rk3328_clk_set_rate()
1286 priv->gpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[GPLL], in rkclk_init()
1287 priv->cru, GPLL); in rkclk_init()
1300 rockchip_pll_set_rate(&rk3328_pll_clks[GPLL], in rkclk_init()
1301 priv->cru, GPLL, GPLL_HZ); in rkclk_init()
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| H A D | clk_rk3128.c | 87 [GPLL] = PLL(pll_rk3036, PLL_GPLL, RK2928_PLL_CON(12),
605 ret = rockchip_pll_set_rate(&rk3128_pll_clks[GPLL], in rk3128_clk_set_rate()
606 priv->cru, GPLL, rate); in rk3128_clk_set_rate()
814 priv->gpll_hz = rockchip_pll_get_rate(&rk3128_pll_clks[GPLL], in rkclk_init()
815 priv->cru, GPLL); in rkclk_init()
818 rockchip_pll_set_rate(&rk3128_pll_clks[GPLL], in rkclk_init()
819 priv->cru, GPLL, GPLL_HZ); in rkclk_init()
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| H A D | clk_rk3368.c | 315 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
596 parent = rkclk_pll_get_rate(cru, GPLL); in rk3368_bus_get_clk()
630 src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz); in rk3368_bus_set_clk()
670 parent = rkclk_pll_get_rate(cru, GPLL); in rk3368_peri_get_clk()
704 src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz); in rk3368_peri_set_clk()
757 parent = rkclk_pll_get_rate(cru, GPLL); in rk3368_vop_get_clk()
806 lcdc_div = rkclk_pll_get_rate(cru, GPLL) / hz; in rk3368_vop_set_clk()
1277 rkclk_set_pll(cru, GPLL, &gpll_init_cfg); in rkclk_init()
1285 gpll = rkclk_pll_get_rate(cru, GPLL); in rkclk_init()
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| H A D | clk_rk322x.c | 88 [GPLL] = PLL(pll_rk3036, PLL_GPLL, RK2928_PLL_CON(9),
654 ret = rockchip_pll_set_rate(&rk322x_pll_clks[GPLL], in rk322x_clk_set_rate()
655 priv->cru, GPLL, rate); in rk322x_clk_set_rate()
961 priv->gpll_hz = rockchip_pll_get_rate(&rk322x_pll_clks[GPLL], in rkclk_init()
962 priv->cru, GPLL); in rkclk_init()
992 rockchip_pll_set_rate(&rk322x_pll_clks[GPLL], in rkclk_init()
993 priv->cru, GPLL, GPLL_HZ); in rkclk_init()
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| H A D | clk_rk1808.c | 86 [GPLL] = PLL(pll_rk3036, PLL_GPLL, RK1808_PLL_CON(24),
1015 ret = rockchip_pll_set_rate(&rk1808_pll_clks[GPLL], in rk1808_clk_set_rate()
1016 priv->cru, GPLL, rate); in rk1808_clk_set_rate()
1303 ret = rockchip_pll_set_rate(&rk1808_pll_clks[GPLL], in rk1808_clk_probe()
1304 priv->cru, GPLL, GPLL_HZ); in rk1808_clk_probe()
1310 priv->gpll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[GPLL], in rk1808_clk_probe()
1311 priv->cru, GPLL); in rk1808_clk_probe()
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| H A D | clk_rv1106.c | 45 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1106_PLL_CON(24),
1064 rate = rockchip_pll_get_rate(&rv1106_pll_clks[GPLL], priv->cru, in rv1106_clk_get_rate()
1065 GPLL); in rv1106_clk_get_rate()
1162 ret = rockchip_pll_set_rate(&rv1106_pll_clks[GPLL], priv->cru, in rv1106_clk_set_rate()
1163 GPLL, rate); in rv1106_clk_set_rate()
1285 ret = rockchip_pll_set_rate(&rv1106_pll_clks[GPLL], priv->cru, in rv1106_clk_init()
1286 GPLL, GPLL_HZ); in rv1106_clk_init()
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| H A D | clk_rk3528.c | 72 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24),
1354 rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru, in rk3528_clk_get_rate()
1355 GPLL); in rk3528_clk_get_rate()
1475 ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru, in rk3528_clk_set_rate()
1476 GPLL, rate); in rk3528_clk_set_rate()
1477 priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], in rk3528_clk_set_rate()
1478 priv->cru, GPLL); in rk3528_clk_set_rate()
1900 ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru, in rk3528_clk_init()
1901 GPLL, GPLL_HZ); in rk3528_clk_init()
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| H A D | clk_rk3562.c | 47 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3562_PLL_CON(24),
1367 rate = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL], priv->cru, in rk3562_clk_get_rate()
1368 GPLL); in rk3562_clk_get_rate()
1494 ret = rockchip_pll_set_rate(&rk3562_pll_clks[GPLL], priv->cru, in rk3562_clk_set_rate()
1495 GPLL, rate); in rk3562_clk_set_rate()
1496 priv->gpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL], in rk3562_clk_set_rate()
1497 priv->cru, GPLL); in rk3562_clk_set_rate()
1827 ret = rockchip_pll_set_rate(&rk3562_pll_clks[GPLL], priv->cru, in rk3562_clk_init()
1828 GPLL, GPLL_HZ); in rk3562_clk_init()
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| H A D | clk_rk3588.c | 61 [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3588_PLL_CON(112),
1534 rate = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_get_rate()
1535 GPLL); in rk3588_clk_get_rate()
1679 ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_set_rate()
1680 GPLL, rate); in rk3588_clk_set_rate()
1681 priv->gpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], in rk3588_clk_set_rate()
1682 priv->cru, GPLL); in rk3588_clk_set_rate()
2039 ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_init()
2040 GPLL, GPLL_HZ); in rk3588_clk_init()
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| H A D | clk_rk3568.c | 74 [GPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PLL_CON(16),
2524 rate = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL], priv->cru, in rk3568_clk_get_rate()
2525 GPLL); in rk3568_clk_get_rate()
2709 ret = rockchip_pll_set_rate(&rk3568_pll_clks[GPLL], priv->cru, in rk3568_clk_set_rate()
2710 GPLL, rate); in rk3568_clk_set_rate()
2711 priv->gpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL], in rk3568_clk_set_rate()
2712 priv->cru, GPLL); in rk3568_clk_set_rate()
3255 ret = rockchip_pll_set_rate(&rk3568_pll_clks[GPLL], priv->cru, in rk3568_clk_init()
3256 GPLL, GPLL_HZ); in rk3568_clk_init()
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| H A D | clk_rv1126.c | 68 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126_PMU_PLL_CON(0),
153 return rockchip_pll_get_rate(&rv1126_pll_clks[GPLL], in rv1126_gpll_get_pmuclk()
154 priv->pmucru, GPLL); in rv1126_gpll_get_pmuclk()
2087 if (rockchip_pll_set_rate(&rv1126_pll_clks[GPLL], in rv1126_gpll_set_rate()
2088 pmu_priv->pmucru, GPLL, rate)) in rv1126_gpll_set_rate()
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| /OK3568_Linux_fs/u-boot/board/rockchip/evb_rv1108/ |
| H A D | README | 31 APLL: 400000000 DPLL:798000000 GPLL:384000000
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3368.h | 18 GPLL, enumerator
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| H A D | cru_rk3128.h | 66 GPLL, enumerator
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| H A D | cru_rk322x.h | 63 GPLL, enumerator
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| H A D | cru_rk3328.h | 61 GPLL, enumerator
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| H A D | cru_rv1106.h | 29 GPLL, enumerator
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| H A D | cru_rk1808.h | 23 GPLL, enumerator
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| H A D | cru_rk3528.h | 24 GPLL, enumerator
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| H A D | cru_rv1126.h | 52 GPLL, enumerator
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| H A D | cru_px30.h | 31 GPLL, enumerator
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| H A D | cru_rk3562.h | 25 GPLL, enumerator
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| H A D | cru_rk3588.h | 27 GPLL, enumerator
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| H A D | cru_rk3568.h | 24 GPLL, enumerator
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3399-gru-chromebook.dtsi | 243 * off GPLL=600MHz, whereas some other RK3399 boards may not.
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