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Searched refs:DPLL_MODE_MASK (Results 1 – 15 of 15) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3188.h183 DPLL_MODE_MASK = 3, enumerator
H A Dcru_rk3066.h173 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, enumerator
H A Dcru_rk3036.h107 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, enumerator
H A Dcru_rk3288.h247 DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT, enumerator
H A Dcru_px30.h169 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, enumerator
H A Dcru_rk3308.h142 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, enumerator
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c332 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, in rkdclk_init()
351 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, in rkdclk_init()
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3066.c171 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
181 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
H A Dclk_rk3188.c169 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
179 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
H A Dclk_rk3288.c332 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
342 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
H A Dclk_rk3036.c213 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, in rkclk_pll_get_rate()
H A Dclk_px30.c98 APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK,
/OK3568_Linux_fs/kernel/drivers/gpu/drm/gma500/
H A Dpsb_intel_reg.h235 #define DPLL_MODE_MASK (3 << 26) macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_display.c12168 switch (dpll & DPLL_MODE_MASK) { in i9xx_crtc_clock_get()
12180 "mode\n", (int)(dpll & DPLL_MODE_MASK)); in i9xx_crtc_clock_get()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/
H A Di915_reg.h3441 #define DPLL_MODE_MASK (3 << 26) macro