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Searched refs:BIT_1 (Results 1 – 25 of 38) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dqla1280.h18 #define BIT_1 0x2 macro
121 #define ISP_CFG0_1020A BIT_1 /* ISP1020A */
135 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
142 #define PCI_INT BIT_1 /* PCI interrupt */
147 #define NV_SELECT BIT_1
159 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
176 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
568 #define RF_FULL BIT_1 /* Full */
966 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
H A Dqla1280.c1124 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1690 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio()
1704 #define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1708 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1832 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_start_firmware()
1842 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_start_firmware()
1909 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1923 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2143 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_config_bus()
2216 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()
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/OK3568_Linux_fs/kernel/drivers/scsi/qla2xxx/
H A Dqla_fw.h30 #define PDO_FORCE_ADISC BIT_1
45 #define PDF_HARD_ADDR BIT_1
456 #define BD_READ_DATA BIT_1
494 #define CF_READ_DATA BIT_1
536 #define TMF_READ_DATA BIT_1
965 #define TCF_TARGET_RESET BIT_1
1167 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
1237 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1245 #define GPEX_ENABLE (BIT_1|BIT_0)
1368 #define MDBS_ID_ACQUIRED BIT_1
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H A Dqla_def.h82 #define BIT_1 0x2 macro
204 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
224 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
481 #define SRB_LOGIN_COND_PLOGI BIT_1
526 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
714 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
732 #define NVR_SELECT BIT_1
989 #define MBX_DMA_OUT BIT_1
1002 #define MBX_DMA_OUT BIT_1
1124 #define FO1_AE_ALL_LIP_RESET BIT_1
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H A Dqla_target.h224 #define ATIO_EXEC_READ BIT_1
469 #define CTIO7_FLAGS_DATA_IN BIT_1 /* data to initiator */
830 TRC_DO_WORK = BIT_1,
956 #define QLA24XX_MGMT_ABORT_IO_ATTR_VALID BIT_1
H A Dqla_nvme.h60 #define CF_READ_DATA BIT_1
H A Dqla_tmpl.h61 #define CAPTURE_FLAG_PHYS_VIRT BIT_1
H A Dqla_init.c3995 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
3999 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4009 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
4010 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
4015 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); in qla2x00_update_fw_options()
4017 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4027 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
4028 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
4321 mid_init_cb->options = cpu_to_le16(BIT_1); in qla2x00_init_rings()
4744 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
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H A Dqla_mbx.c761 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1); in qla2x00_execute_fw()
768 (BIT_0 | BIT_1 | BIT_2); in qla2x00_execute_fw()
1849 mcp->mb[1] |= BIT_1; in qla2x00_init_firmware()
2349 mcp->mb[1] = BIT_1; in qla2x00_lip_reset()
2482 if (opt & BIT_1) in qla24xx_login_fabric()
2542 mb[1] |= BIT_1; in qla24xx_login_fabric()
2551 mb[10] |= BIT_1; /* Class 3. */ in qla24xx_login_fabric()
4269 rval = BIT_1; in qla2x00_send_change_request()
4272 rval = BIT_1; in qla2x00_send_change_request()
5671 mcp->mb[2] = BIT_1; in qla24xx_set_fcp_prio()
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H A Dqla_mid.c877 options |= BIT_1; in qla25xx_create_rsp_que()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/realtek/r8168/
H A Dr8168_dash.h185 #define TXS_CC3_0 (BIT_0|BIT_1|BIT_2|BIT_3)
222 #define ISRIMR_DASH_TYPE2_RDU BIT_1
H A Dr8168_n.c2929 clearmask = (BIT_0 | BIT_1); in rtl8168_set_dash_other_fun_dev_state_change()
2938 setmask = (BIT_0 | BIT_1); in rtl8168_set_dash_other_fun_dev_state_change()
2953 aspm_val &= (BIT_0 | BIT_1); in rtl8168_set_dash_other_fun_dev_aspm_clkreq()
2954 clearmask = (BIT_0 | BIT_1 | BIT_8); in rtl8168_set_dash_other_fun_dev_aspm_clkreq()
3192 if (rtl8168_mac_ocp_read(tp, 0xDC20) & BIT_1) in rtl8168_is_phy_disable_mode_enabled()
4023 csi_tmp |= BIT_1; in rtl8168_check_link_status()
4225 csi_tmp &= ~(BIT_0 | BIT_1); in rtl8168_disable_pci_offset_99()
4277 csi_tmp &= ~(BIT_0 | BIT_1); in rtl8168_enable_pci_offset_99()
4279 csi_tmp |= BIT_1; in rtl8168_enable_pci_offset_99()
4296 csi_tmp &= ~BIT_1; in rtl8168_init_pci_offset_99()
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H A Dr8168.h1391 BIT_1 = (1 << 1), enumerator
/OK3568_Linux_fs/kernel/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hw.h140 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
H A Dqlcnic_hdr.h196 #define BIT_1 0x2 macro
493 #define TA_CTL_ENABLE BIT_1
H A Dqlcnic_ctx.c1346 arg2 |= (BIT_0 | BIT_1); in qlcnic_config_switch_port()
1358 arg2 &= ~(BIT_1 | BIT_2 | BIT_3); in qlcnic_config_switch_port()
1359 if (!(esw_cfg->offload_flags & BIT_1)) in qlcnic_config_switch_port()
H A Dqlcnic.h913 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
929 #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1
1315 #define QLCNIC_SWITCH_ENABLE BIT_1
H A Dqlcnic_83xx_hw.h531 #define QLC_REGISTER_DCB_AEN BIT_1
H A Dqlcnic_hw.c819 #define QLCNIC_ENABLE_IPV6_LRO (BIT_1 | BIT_9)
1037 if (!(offload_flags & BIT_1)) in qlcnic_process_flags()
H A Dqlcnic_minidump.c24 #define QLCNIC_DUMP_RWCRB BIT_1
753 if (dma_sts & BIT_1) in qlcnic_start_pex_dma()
H A Dqlcnic_sriov_pf.c390 cmd.req.arg[1] = ((func & 0xf) << 2) | BIT_6 | BIT_1; in qlcnic_sriov_pf_cfg_eswitch()
703 cmd.req.arg[2] |= BIT_1 | BIT_3 | BIT_8; in qlcnic_sriov_set_vf_acl()
H A Dqlcnic_83xx_hw.c2023 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()
3539 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16); in qlcnic_83xx_get_stats()
3570 #define QLCNIC_83XX_ADD_PORT1 BIT_1
/OK3568_Linux_fs/kernel/drivers/scsi/qla4xxx/
H A Dql4_def.h82 #define BIT_1 0x2 macro
H A Dql4_os.c3542 sess->erl |= BIT_1; in qla4xxx_copy_from_fwddb_param()
3555 conn->tcp_timer_scale |= BIT_1; in qla4xxx_copy_from_fwddb_param()
3673 SET_BITVAL(sess->erl & BIT_1, options, BIT_1); in qla4xxx_copy_to_fwddb_param()
3682 SET_BITVAL(conn->tcp_timer_scale & BIT_1, options, BIT_2); in qla4xxx_copy_to_fwddb_param()
3683 SET_BITVAL(conn->tcp_timer_scale & BIT_0, options, BIT_1); in qla4xxx_copy_to_fwddb_param()
3779 sess->erl |= BIT_1; in qla4xxx_copy_to_sess_conn_params()
3792 conn->tcp_timer_scale |= BIT_1; in qla4xxx_copy_to_sess_conn_params()
8909 if (PCI_FUNC(ha->pdev->devfn) & BIT_1) in qla4xxx_prevent_other_port_reinit()
H A Dql4_fw.h61 #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */

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