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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx6qdl-tx6-lcd.dtsi2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
4 * This file is dual-licensed: you can use it either under the terms
48 compatible = "pwm-backlight";
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_lcd1_pwr>;
52 enable-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
53 power-supply = <&reg_3v3>;
54 turn-on-delay-ms = <35>;
59 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
70 default-brightness-level = <50>;
[all …]
H A Dimx6qdl-tx6-lvds.dtsi2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
4 * This file is dual-licensed: you can use it either under the terms
50 compatible = "pwm-backlight";
52 power-supply = <&reg_lcd0_pwr>;
53 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
64 default-brightness-level = <50>;
68 compatible = "pwm-backlight";
70 power-supply = <&reg_lcd1_pwr>;
71 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
82 default-brightness-level = <50>;
[all …]
H A Dimx53-tx53-x03x.dts2 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
4 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
43 #include "imx53-tx53.dtsi"
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/pwm/pwm.h>
49 model = "Ka-Ro electronics TX53 module (LCD)";
57 compatible = "fsl,imx-parallel-display";
58 interface-pix-fmt = "rgb24";
[all …]
H A Dimx6ul-tx6ul.dtsi2 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * This file is dual-licensed: you can use it either under the terms
42 #include <dt-bindings/gpio/gpio.h>
43 #include <dt-bindings/interrupt-controller/irq.h>
44 #include <dt-bindings/pwm/pwm.h>
56 lcdif-23bit-pins-a = &pinctrl_disp0_1;
57 lcdif-24bit-pins-a = &pinctrl_disp0_2;
59 reg-can-xcvr = &reg_can_xcvr;
70 stdout-path = &uart1;
75 reg = <0x80000000 0>; /* will be filled by U-Boot */
[all …]
H A Dimx28-tx28.dts3 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
5 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
45 #include <dt-bindings/gpio/gpio.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
49 model = "Ka-Ro electronics TX28 module";
70 reg = <0x40000000 0>; /* will be filled in by U-Boot */
74 compatible = "w1-gpio";
79 reg_usb0_vbus: regulator-usb0-vbus {
80 compatible = "regulator-fixed";
[all …]
H A Dimx53-tx53-x13x.dts2 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
4 * This file is dual-licensed: you can use it either under the terms
44 * http://www.opensource.org/licenses/gpl-license.html
48 /dts-v1/;
49 #include "imx53-tx53.dtsi"
50 #include <dt-bindings/input/input.h>
53 model = "Ka-Ro electronics TX53 module (LVDS)";
63 compatible = "pwm-backlight";
65 power-supply = <&reg_3v3>;
66 brightness-levels = <
[all …]
/OK3568_Linux_fs/kernel/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
21 # Active Time 25.422 us 15.253 ms
28 mode "640x480-60"
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
46 # Active Time 20.317 us 12.800 ms
52 mode "640x480-75"
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
67 # Active Time 17.778 us 11.093 ms
73 mode "640x480-85"
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk1808-evb-x4-second.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/display/drm_mipi_dsi.h>
8 #include "rk1808-evb.dtsi"
12 compatible = "rockchip,rk1808-evb-x4", "rockchip,rk1808";
20 power-key {
23 press-threshold-microvolt = <18000>;
27 /delete-node/ &backlight;
28 /delete-node/ &vcc1v8_dvp;
29 /delete-node/ &vdd1v5_dvp;
[all …]
H A Drk1808-evb-x4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/display/drm_mipi_dsi.h>
8 #include "rk1808-evb.dtsi"
12 compatible = "rockchip,rk1808-evb-x4", "rockchip,rk1808";
20 power-key {
23 press-threshold-microvolt = <18000>;
27 /delete-node/ &backlight;
28 /delete-node/ &vcc1v8_dvp;
29 /delete-node/ &vdd1v5_dvp;
[all …]
H A Drk3588-vehicle-maxim-serdes.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/display/media-bus-format.h>
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "pwm-backlight";
22 brightness-levels = <0 4 8 16 32 64 128 255>;
23 default-brightness-level = <6>;
27 compatible = "pwm-backlight";
30 brightness-levels = <0 4 8 16 32 64 128 255>;
[all …]
H A Drk3399-sapphire-excavator-linux-for-rk1808-cascade.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "rk3399-excavator-sapphire.dtsi"
9 #include "rk3399-linux.dtsi"
10 #include <dt-bindings/input/input.h>
14 compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399";
16 fiq_debugger: fiq-debugger {
17 compatible = "rockchip,fiq-debugger";
18 rockchip,serial-id = <2>;
19 rockchip,signal-irq = <182>;
[all …]
H A Drk3588-vehicle-maxim-serdes-display-s66.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/display/media-bus-format.h>
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "pwm-backlight";
22 brightness-levels = <0 4 8 16 32 64 128 255>;
23 default-brightness-level = <6>;
27 compatible = "pwm-backlight";
30 brightness-levels = <0 4 8 16 32 64 128 255>;
[all …]
H A Drk3588-nvr-demo.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "rk3588-nvr.dtsi"
9 #include "rk3588-rk806-single.dtsi"
12 i2s0_sound: i2s0-sound {
14 compatible = "simple-audio-card";
15 simple-audio-card,format = "i2s";
16 simple-audio-card,mclk-fs = <256>;
17 simple-audio-card,name = "rockchip,es8311";
18 simple-audio-card,dai-link@0 {
21 sound-dai = <&i2s0_8ch>;
[all …]
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/video/
H A Ddisplay-timing.txt1 display-timing bindings
4 display-timings node
5 --------------------
8 - none
11 - native-mode: The native mode for the display, in case multiple modes are
15 --------------
18 - hactive, vactive: display resolution
19 - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
21 vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
23 - clock-frequency: display clock in Hz
[all …]
H A Ddisplaymode.txt4 (from http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html)
7 - xres, yres: Display resolution
8 - left-margin, right-margin, hsync-len: Horizontal Display timing
10 - upper-margin, lower-margin, vsync-len: Vertical display timing
12 - clock: display clock in Hz
15 - width-mm, height-mm: Display dimensions in mm
16 - hsync-active-high (bool): Hsync pulse is active high
17 - vsync-active-high (bool): Vsync pulse is active high
18 - interlaced (bool): This is an interlaced mode
19 - doublescan (bool): This is a doublescan mode
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Drenesas,vin.yaml1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Video Input (VIN)
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 The R-Car Video Input (VIN) device provides video input capabilities for the
15 Renesas R-Car family of devices.
20 on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
25 - items:
26 - enum:
[all …]
H A Dallwinner,sun6i-a31-csi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun6i-a31-csi
17 - allwinner,sun8i-a83t-csi
18 - allwinner,sun8i-h3-csi
19 - allwinner,sun8i-v3s-csi
[all …]
H A Dallwinner,sun4i-a10-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
13 description: |-
20 - const: allwinner,sun4i-a10-csi1
21 - const: allwinner,sun7i-a20-csi0
22 - items:
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/i2c/
H A Dtvp7002.txt7 - compatible : Must be "ti,tvp7002"
10 - hsync-active: HSYNC Polarity configuration for the bus. Default value when
13 - vsync-active: VSYNC Polarity configuration for the bus. Default value when
16 - pclk-sample: Clock polarity of the bus. Default value when this property is
19 - sync-on-green-active: Active state of Sync-on-green signal property of the
21 0 = Normal Operation (Active Low, Default)
24 - field-even-active: Active-high Field ID output polarity control of the bus.
27 0 = Normal Operation (Active Low, Default)
31 video-interfaces.txt.
44 hsync-active = <1>;
[all …]
H A Dov7670.txt8 - compatible: should be "ovti,ov7670"
9 - clocks: reference to the xclk input clock.
10 - clock-names: should be "xclk".
13 - hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
14 - vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
17 - reset-gpios: reference to the GPIO connected to the resetb pin, if any.
18 Active is low.
19 - powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any.
20 Active is high.
21 - ov7670,pclk-hb-disable: a boolean property to suppress pixel clock output
[all …]
H A Dtvp514x.txt3 The TVP5146/TVP5146m2/TVP5147/TVP5147m1 device is high quality, single-chip
5 video formats into digital video component. The tvp514x decoder supports analog-
6 to-digital (A/D) conversion of component RGB and YPbPr signals as well as A/D
7 conversion and decoding of NTSC, PAL and SECAM composite and S-video into
11 - compatible : value should be either one among the following
17 - hsync-active: HSYNC Polarity configuration for endpoint.
19 - vsync-active: VSYNC Polarity configuration for endpoint.
21 - pclk-sample: Clock polarity of the endpoint.
24 media/video-interfaces.txt.
37 hsync-active = <1>;
[all …]
H A Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
17 - VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
18 - VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/video/
H A Drockchip_mipidsi_lcd.txt1 Device-Tree bindings for rockchip mipi dsi lcd driver
4 - rockchip,screen_init: Whether you need this screen initialization.
8 - rockchip,dsi_lane: mipi lcd data lane number.
10 - rockchip,dsi_hs_clk: mipi lcd high speed clock.
12 - rockchip,mipi_dsi_num: mipi lcd dsi number.
14 - mipi_lcd_rst:mipi_lcd_rst: Should specify pin control groups used for reset this lcd.
16 - mipi_lcd_en:mipi_lcd_en: Should specify pin control groups used for enable this lcd.
18 - rockchip,gpios: gpio pin
20 - rockchip,delay: delay the millisecond.
22 - rockchip,cmd_debug : debug the cammands.
[all …]
/OK3568_Linux_fs/kernel/include/media/i2c/
H A Dtvp7002.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
6 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
19 * struct tvp7002_config - Platform dependent data
21 * 0 - Data clocked out on rising edge of DATACLK signal
22 * 1 - Data clocked out on falling edge of DATACLK signal
24 * 0 - Active low HSYNC output, 1 - Active high HSYNC output
25 *@vs_polarity: VSYNC Polarity
26 * 0 - Active low VSYNC output, 1 - Active high VSYNC output
27 *@fid_polarity: Active-high Field ID polarity.
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
16 There're still four pins for camera control, two inputs (strobe and vsync),
18 supply, vsync input from IR camera, and fsin1/fsin2 output for the optional.
27 wakeup-source: true
32 enable-gpios:
36 richtek,ld-pulse-delay-us:
[all …]

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