1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/display/media-bus-format.h> 7 8/ { 9 aliases { 10 pinctrl0 = &pinctrl; 11 }; 12 13 backlight { 14 compatible = "simple-bus"; 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 i2c2_max96755f_backlight: backlight@0 { 19 compatible = "pwm-backlight"; 20 reg = <0>; 21 pwms = <&pwm6 0 1000000 0>; 22 brightness-levels = <0 4 8 16 32 64 128 255>; 23 default-brightness-level = <6>; 24 }; 25 26 i2c3_max96745_backlight: backlight@1 { 27 compatible = "pwm-backlight"; 28 reg = <1>; 29 pwms = <&pwm10 0 1000000 0>; 30 brightness-levels = <0 4 8 16 32 64 128 255>; 31 default-brightness-level = <6>; 32 }; 33 34 i2c5_max96745_backlight: backlight@2 { 35 compatible = "pwm-backlight"; 36 reg = <2>; 37 pwms = <&pwm12 0 1000000 0>; 38 brightness-levels = <0 4 8 16 32 64 128 255>; 39 default-brightness-level = <6>; 40 }; 41 42 i2c6_max96755f_backlight: backlight@3 { 43 compatible = "pwm-backlight"; 44 reg = <3>; 45 pwms = <&pwm13 0 1000000 0>; 46 brightness-levels = <0 4 8 16 32 64 128 255>; 47 default-brightness-level = <6>; 48 }; 49 50 i2c7_max96745_backlight: backlight@4 { 51 compatible = "pwm-backlight"; 52 reg = <4>; 53 pwms = <&pwm11 0 1000000 0>; 54 brightness-levels = <0 4 8 16 32 64 128 255>; 55 default-brightness-level = <6>; 56 }; 57 58 i2c8_max96745_backlight: backlight@5 { 59 compatible = "pwm-backlight"; 60 reg = <5>; 61 pwms = <&pwm14 0 1000000 0>; 62 brightness-levels = <0 4 8 16 32 64 128 255>; 63 default-brightness-level = <6>; 64 }; 65 }; 66}; 67 68&dp0 { 69 split-mode; 70 force-hpd; 71 status = "okay"; 72}; 73 74&dp0_in_vp0 { 75 status = "okay"; 76}; 77 78&dp0_out { 79 link-frequencies = /bits/ 64 <2700000000>; 80 remote-endpoint = <&i2c3_max96745_in>; 81}; 82 83&usbdp_phy0 { 84 rockchip,dp-lane-mux = <0 1 2 3>; 85 status = "okay"; 86}; 87 88&usbdp_phy0_dp { 89 status = "okay"; 90}; 91 92&route_dp0 { 93 connect = <&vp0_out_dp0>; 94 status = "okay"; 95}; 96 97&dp1 { 98 force-hpd; 99 status = "okay"; 100}; 101 102&dp1_out { 103 link-frequencies = /bits/ 64 <2700000000>; 104 remote-endpoint = <&i2c8_max96745_in>; 105}; 106 107&usbdp_phy1 { 108 rockchip,dp-lane-mux = <0 1 2 3>; 109 status = "okay"; 110}; 111 112&usbdp_phy1_dp { 113 status = "okay"; 114}; 115 116&dsi0 { 117 status = "okay"; 118 119 ports { 120 #address-cells = <1>; 121 #size-cells = <0>; 122 123 port@1 { 124 reg = <1>; 125 126 dsi0_out: endpoint { 127 remote-endpoint = <&i2c2_max96755f_in>; 128 }; 129 }; 130 }; 131}; 132 133&mipi_dcphy0 { 134 status = "okay"; 135}; 136 137&dsi0_in_vp2 { 138 status = "okay"; 139}; 140 141&route_dsi0 { 142 connect = <&vp2_out_dsi0>; 143 status = "okay"; 144}; 145 146&dsi1 { 147 status = "okay"; 148 149 ports { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 153 port@1 { 154 reg = <1>; 155 156 dsi1_out: endpoint { 157 remote-endpoint = <&i2c6_max96755f_in>; 158 }; 159 }; 160 }; 161}; 162 163&mipi_dcphy1 { 164 status = "okay"; 165}; 166 167&dsi1_in_vp3 { 168 status = "okay"; 169}; 170 171&route_dsi1 { 172 connect = <&vp3_out_dsi1>; 173 status = "okay"; 174}; 175 176&edp0 { 177 split-mode; 178 force-hpd; 179 status = "okay"; 180}; 181 182&edp0_out { 183 link-frequencies = /bits/ 64 <2700000000>; 184 remote-endpoint = <&i2c5_max96745_in>; 185}; 186 187&hdptxphy0 { 188 status = "okay"; 189}; 190 191&edp0_in_vp1 { 192 status = "okay"; 193}; 194 195&route_edp0 { 196 connect = <&vp1_out_edp0>; 197 status = "okay"; 198}; 199 200&edp1 { 201 force-hpd; 202 status = "okay"; 203}; 204 205&edp1_out { 206 link-frequencies = /bits/ 64 <2700000000>; 207 remote-endpoint = <&i2c7_max96745_in>; 208}; 209 210&hdptxphy1 { 211 status = "okay"; 212}; 213 214&i2c2 { 215 pinctrl-0 = <&i2c2m4_xfer>; 216 clock-frequency = <400000>; 217 status = "okay"; 218 219 max96755f@40 { 220 compatible = "maxim,max96755f"; 221 reg = <0x40>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&i2c2_serdes_pins>; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 227 pinctrl { 228 compatible = "maxim,max96755f-pinctrl"; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&i2c2_max96755f_pinctrl_hog>; 231 232 i2c2_max96755f_pinctrl_hog: hog { 233 i2c { 234 groups = "I2C"; 235 function = "I2C"; 236 }; 237 }; 238 239 i2c2_max96755f_panel_pins: panel-pins { 240 bl-pwm { 241 pins = "MFP18"; 242 function = "GPIO_TX_0"; 243 }; 244 }; 245 }; 246 247 bridge { 248 compatible = "maxim,max96755f-bridge"; 249 lock-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; 250 251 ports { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 255 port@0 { 256 reg = <0>; 257 258 i2c2_max96755f_in: endpoint { 259 remote-endpoint = <&dsi0_out>; 260 }; 261 }; 262 263 port@1 { 264 reg = <1>; 265 266 i2c2_max96755f_out: endpoint { 267 remote-endpoint = <&i2c2_max96755f_panel_in>; 268 }; 269 }; 270 }; 271 }; 272 273 gmsl@0 { 274 reg = <0>; 275 clock-frequency = <400000>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 279 panel@48 { 280 compatible = "boe,av156fht-l83"; 281 reg = <0x48>; 282 backlight = <&i2c2_max96755f_backlight>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&i2c2_max96755f_panel_pins>; 285 286 panel-timing { 287 clock-frequency = <148500000>; 288 hactive = <1920>; 289 vactive = <1080>; 290 hfront-porch = <20>; 291 hsync-len = <20>; 292 hback-porch = <20>; 293 vfront-porch = <250>; 294 vsync-len = <2>; 295 vback-porch = <8>; 296 hsync-active = <0>; 297 vsync-active = <0>; 298 de-active = <0>; 299 pixelclk-active = <0>; 300 }; 301 302 port { 303 i2c2_max96755f_panel_in: endpoint { 304 remote-endpoint = <&i2c2_max96755f_out>; 305 }; 306 }; 307 }; 308 }; 309 }; 310}; 311 312&i2c3 { 313 pinctrl-0 = <&i2c3m2_xfer>; 314 clock-frequency = <400000>; 315 status = "okay"; 316 317 max96745@42 { 318 compatible = "maxim,max96745"; 319 reg = <0x42>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&i2c3_serdes_pins>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 325 pinctrl { 326 compatible = "maxim,max96745-pinctrl"; 327 pinctrl-names = "default"; 328 pinctrl-0 = <&i2c3_max96745_pinctrl_hog>; 329 330 i2c3_max96745_pinctrl_hog: hog { 331 i2c { 332 groups = "I2C"; 333 function = "I2C"; 334 }; 335 }; 336 337 i2c3_max96745_panel_pins: panel-pins { 338 bl-pwm { 339 pins = "MFP0"; 340 function = "GPIO_TX_A_0"; 341 }; 342 }; 343 }; 344 345 bridge { 346 compatible = "maxim,max96745-bridge"; 347 lock-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; 348 349 ports { 350 #address-cells = <1>; 351 #size-cells = <0>; 352 353 port@0 { 354 reg = <0>; 355 356 i2c3_max96745_in: endpoint { 357 remote-endpoint = <&dp0_out>; 358 }; 359 }; 360 361 port@1 { 362 reg = <1>; 363 364 i2c3_max96745_out: endpoint { 365 remote-endpoint = <&i2c3_max96745_panel_in>; 366 }; 367 }; 368 }; 369 }; 370 371 gmsl@0 { 372 reg = <0>; 373 clock-frequency = <400000>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 377 panel@48 { 378 compatible = "boe,av156fht-l83"; 379 reg = <0x48>; 380 backlight = <&i2c3_max96745_backlight>; 381 pinctrl-names = "default"; 382 pinctrl-0 = <&i2c3_max96745_panel_pins>; 383 384 panel-timing { 385 clock-frequency = <148500000>; 386 hactive = <1920>; 387 vactive = <1080>; 388 hfront-porch = <20>; 389 hsync-len = <20>; 390 hback-porch = <20>; 391 vfront-porch = <250>; 392 vsync-len = <2>; 393 vback-porch = <8>; 394 hsync-active = <0>; 395 vsync-active = <0>; 396 de-active = <0>; 397 pixelclk-active = <0>; 398 }; 399 400 port { 401 i2c3_max96745_panel_in: endpoint { 402 remote-endpoint = <&i2c3_max96745_out>; 403 }; 404 }; 405 }; 406 }; 407 }; 408}; 409 410&i2c5 { 411 clock-frequency = <400000>; 412 status = "okay"; 413 414 max96745@42 { 415 compatible = "maxim,max96745"; 416 reg = <0x42>; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&i2c5_serdes_pins>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 422 pinctrl { 423 compatible = "maxim,max96745-pinctrl"; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&i2c5_max96745_pinctrl_hog>; 426 427 i2c5_max96745_pinctrl_hog: hog { 428 i2c { 429 groups = "I2C"; 430 function = "I2C"; 431 }; 432 }; 433 434 i2c5_max96745_panel_pins: panel-pins { 435 bl-pwm { 436 pins = "MFP0"; 437 function = "GPIO_TX_A_0"; 438 }; 439 }; 440 }; 441 442 bridge { 443 compatible = "maxim,max96745-bridge"; 444 lock-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; 445 446 ports { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 450 port@0 { 451 reg = <0>; 452 453 i2c5_max96745_in: endpoint { 454 remote-endpoint = <&edp0_out>; 455 }; 456 }; 457 458 port@1 { 459 reg = <1>; 460 461 i2c5_max96745_out: endpoint { 462 remote-endpoint = <&i2c5_max96745_panel_in>; 463 }; 464 }; 465 }; 466 }; 467 468 gmsl@0 { 469 reg = <0>; 470 clock-frequency = <400000>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 474 panel@48 { 475 compatible = "boe,av156fht-l83"; 476 reg = <0x48>; 477 backlight = <&i2c5_max96745_backlight>; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&i2c5_max96745_panel_pins>; 480 481 panel-timing { 482 clock-frequency = <148500000>; 483 hactive = <1920>; 484 vactive = <1080>; 485 hfront-porch = <20>; 486 hsync-len = <20>; 487 hback-porch = <20>; 488 vfront-porch = <250>; 489 vsync-len = <2>; 490 vback-porch = <8>; 491 hsync-active = <0>; 492 vsync-active = <0>; 493 de-active = <0>; 494 pixelclk-active = <0>; 495 }; 496 497 port { 498 i2c5_max96745_panel_in: endpoint { 499 remote-endpoint = <&i2c5_max96745_out>; 500 }; 501 }; 502 }; 503 }; 504 }; 505}; 506 507&i2c6 { 508 pinctrl-0 = <&i2c6m3_xfer>; 509 clock-frequency = <400000>; 510 status = "okay"; 511 512 max96755f@40 { 513 compatible = "maxim,max96755f"; 514 reg = <0x40>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&i2c6_serdes_pins>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 520 pinctrl { 521 compatible = "maxim,max96755f-pinctrl"; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&i2c6_max96755f_pinctrl_hog>; 524 525 i2c6_max96755f_pinctrl_hog: hog { 526 i2c { 527 groups = "I2C"; 528 function = "I2C"; 529 }; 530 }; 531 532 533 i2c6_max96755f_panel_pins: panel-pins { 534 bl-pwm { 535 pins = "MFP18"; 536 function = "GPIO_TX_0"; 537 }; 538 }; 539 }; 540 541 bridge { 542 compatible = "maxim,max96755f-bridge"; 543 lock-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; 544 545 ports { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 549 port@0 { 550 reg = <0>; 551 552 i2c6_max96755f_in: endpoint { 553 remote-endpoint = <&dsi1_out>; 554 }; 555 }; 556 557 port@1 { 558 reg = <1>; 559 560 i2c6_max96755f_out: endpoint { 561 remote-endpoint = <&i2c6_max96755f_panel_in>; 562 }; 563 }; 564 }; 565 }; 566 567 gmsl@0 { 568 reg = <0>; 569 clock-frequency = <400000>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 573 panel@48 { 574 compatible = "boe,av156fht-l83"; 575 reg = <0x48>; 576 backlight = <&i2c6_max96755f_backlight>; 577 pinctrl-names = "default"; 578 pinctrl-0 = <&i2c6_max96755f_panel_pins>; 579 580 panel-timing { 581 clock-frequency = <148500000>; 582 hactive = <1920>; 583 vactive = <1080>; 584 hfront-porch = <20>; 585 hsync-len = <20>; 586 hback-porch = <20>; 587 vfront-porch = <250>; 588 vsync-len = <2>; 589 vback-porch = <8>; 590 hsync-active = <0>; 591 vsync-active = <0>; 592 de-active = <0>; 593 pixelclk-active = <0>; 594 }; 595 596 port { 597 i2c6_max96755f_panel_in: endpoint { 598 remote-endpoint = <&i2c6_max96755f_out>; 599 }; 600 }; 601 }; 602 }; 603 }; 604}; 605 606&i2c7 { 607 pinctrl-0 = <&i2c7m3_xfer>; 608 clock-frequency = <400000>; 609 status = "okay"; 610 611 max96745@42 { 612 compatible = "maxim,max96745"; 613 reg = <0x42>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&i2c7_serdes_pins>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 619 pinctrl { 620 compatible = "maxim,max96745-pinctrl"; 621 pinctrl-names = "default"; 622 pinctrl-0 = <&i2c7_max96745_pinctrl_hog>; 623 624 i2c7_max96745_pinctrl_hog: hog { 625 i2c { 626 groups = "I2C"; 627 function = "I2C"; 628 }; 629 }; 630 631 i2c7_max96745_panel_pins: panel-pins { 632 bl-pwm { 633 pins = "MFP0"; 634 function = "GPIO_TX_A_0"; 635 }; 636 }; 637 }; 638 639 bridge { 640 compatible = "maxim,max96745-bridge"; 641 lock-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; 642 643 ports { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 647 port@0 { 648 reg = <0>; 649 650 i2c7_max96745_in: endpoint { 651 remote-endpoint = <&edp1_out>; 652 }; 653 }; 654 655 port@1 { 656 reg = <1>; 657 658 i2c7_max96745_out: endpoint { 659 remote-endpoint = <&i2c7_max96745_panel_in>; 660 }; 661 }; 662 }; 663 }; 664 665 gmsl@0 { 666 reg = <0>; 667 clock-frequency = <400000>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 671 panel@48 { 672 compatible = "boe,av156fht-l83"; 673 reg = <0x48>; 674 backlight = <&i2c7_max96745_backlight>; 675 pinctrl-names = "default"; 676 pinctrl-0 = <&i2c7_max96745_panel_pins>; 677 678 panel-timing { 679 clock-frequency = <148500000>; 680 hactive = <1920>; 681 vactive = <1080>; 682 hfront-porch = <20>; 683 hsync-len = <20>; 684 hback-porch = <20>; 685 vfront-porch = <250>; 686 vsync-len = <2>; 687 vback-porch = <8>; 688 hsync-active = <0>; 689 vsync-active = <0>; 690 de-active = <0>; 691 pixelclk-active = <0>; 692 }; 693 694 port { 695 i2c7_max96745_panel_in: endpoint { 696 remote-endpoint = <&i2c7_max96745_out>; 697 }; 698 }; 699 }; 700 }; 701 }; 702}; 703 704&i2c8 { 705 pinctrl-0 = <&i2c8m2_xfer>; 706 clock-frequency = <400000>; 707 status = "okay"; 708 709 max96745@42 { 710 compatible = "maxim,max96745"; 711 reg = <0x42>; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&i2c8_serdes_pins>; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 717 pinctrl { 718 compatible = "maxim,max96745-pinctrl"; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&i2c8_max96745_pinctrl_hog>; 721 722 i2c8_max96745_pinctrl_hog: hog { 723 i2c { 724 groups = "I2C"; 725 function = "I2C"; 726 }; 727 }; 728 729 i2c8_max96745_panel_pins: panel-pins { 730 bl-pwm { 731 pins = "MFP0"; 732 function = "GPIO_TX_A_0"; 733 }; 734 }; 735 }; 736 737 bridge { 738 compatible = "maxim,max96745-bridge"; 739 lock-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; 740 741 ports { 742 #address-cells = <1>; 743 #size-cells = <0>; 744 745 port@0 { 746 reg = <0>; 747 748 i2c8_max96745_in: endpoint { 749 remote-endpoint = <&dp1_out>; 750 }; 751 }; 752 753 port@1 { 754 reg = <1>; 755 756 i2c8_max96745_out: endpoint { 757 remote-endpoint = <&i2c8_max96745_panel_in>; 758 }; 759 }; 760 }; 761 }; 762 763 gmsl@0 { 764 reg = <0>; 765 clock-frequency = <400000>; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 769 panel@48 { 770 compatible = "boe,av156fht-l83"; 771 reg = <0x48>; 772 backlight = <&i2c8_max96745_backlight>; 773 pinctrl-names = "default"; 774 pinctrl-0 = <&i2c8_max96745_panel_pins>; 775 776 panel-timing { 777 clock-frequency = <148500000>; 778 hactive = <1920>; 779 vactive = <1080>; 780 hfront-porch = <20>; 781 hsync-len = <20>; 782 hback-porch = <20>; 783 vfront-porch = <250>; 784 vsync-len = <2>; 785 vback-porch = <8>; 786 hsync-active = <0>; 787 vsync-active = <0>; 788 de-active = <0>; 789 pixelclk-active = <0>; 790 }; 791 792 port { 793 i2c8_max96745_panel_in: endpoint { 794 remote-endpoint = <&i2c8_max96745_out>; 795 }; 796 }; 797 }; 798 }; 799 }; 800}; 801 802&pinctrl { 803 serdes { 804 i2c2_serdes_pins: i2c2-serdes-pins { 805 rockchip,pins = 806 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 807 }; 808 809 i2c3_serdes_pins: i2c3-serdes-pins { 810 rockchip,pins = 811 <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 812 }; 813 814 i2c5_serdes_pins: i2c5-serdes-pins { 815 rockchip,pins = 816 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; 817 }; 818 819 i2c6_serdes_pins: i2c6-serdes-pins { 820 rockchip,pins = 821 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 822 }; 823 824 i2c7_serdes_pins: i2c7-serdes-pins { 825 rockchip,pins = 826 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 827 }; 828 829 i2c8_serdes_pins: i2c8-serdes-pins { 830 rockchip,pins = 831 <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; 832 }; 833 }; 834}; 835 836&pwm6 { 837 pinctrl-0 = <&pwm6m1_pins>; 838 status = "okay"; 839}; 840 841&pwm10 { 842 pinctrl-0 = <&pwm10m2_pins>; 843 status = "okay"; 844}; 845 846&pwm11 { 847 pinctrl-0 = <&pwm11m3_pins>; 848 status = "okay"; 849}; 850 851&pwm12 { 852 pinctrl-0 = <&pwm12m1_pins>; 853 status = "okay"; 854}; 855 856&pwm13 { 857 pinctrl-0 = <&pwm13m1_pins>; 858 status = "okay"; 859}; 860 861&pwm14 { 862 pinctrl-0 = <&pwm14m0_pins>; 863 status = "okay"; 864}; 865