xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-serdes-display-s66.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/display/media-bus-format.h>
7
8/ {
9	aliases {
10		pinctrl0 = &pinctrl;
11	};
12
13	backlight {
14		compatible = "simple-bus";
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		i2c8_max96755f_backlight: backlight@0 {
19			compatible = "pwm-backlight";
20			reg = <0>;
21			pwms = <&pwm0 0 1000000 0>;
22			brightness-levels = <0 4 8 16 32 64 128 255>;
23			default-brightness-level = <6>;
24		};
25
26		i2c8_max96745_1_backlight: backlight@1 {
27			compatible = "pwm-backlight";
28			reg = <0>;
29			pwms = <&pwm1 0 1000000 0>;
30			brightness-levels = <0 4 8 16 32 64 128 255>;
31			default-brightness-level = <6>;
32		};
33
34		i2c8_max96745_2_backlight: backlight@2 {
35			compatible = "pwm-backlight";
36			reg = <0>;
37			pwms = <&pwm7 0 1000000 0>;
38			brightness-levels = <0 4 8 16 32 64 128 255>;
39			default-brightness-level = <6>;
40		};
41	};
42};
43
44&dp0 {
45	//split-mode;
46	force-hpd;
47	status = "disabled";
48};
49
50&dp0_in_vp0 {
51	status = "okay";
52};
53
54&usbdp_phy0 {
55	rockchip,dp-lane-mux = <0 1 2 3>;
56	status = "okay";
57};
58
59&usbdp_phy0_dp {
60	status = "okay";
61};
62
63&route_dp0 {
64	connect = <&vp0_out_dp0>;
65	status = "disabled";
66};
67
68&dp1 {
69	force-hpd;
70	status = "disabled";
71};
72
73&usbdp_phy1 {
74	//rockchip,dp-lane-mux = <0 1 2 3>;
75	status = "disabled";
76};
77
78&usbdp_phy1_dp {
79	status = "disabled";
80};
81
82&dsi0 {
83	status = "okay";
84
85	ports {
86		#address-cells = <1>;
87		#size-cells = <0>;
88
89		port@1 {
90			reg = <1>;
91
92			dsi0_out: endpoint {
93				remote-endpoint = <&i2c8_max96755f_in>;
94			};
95		};
96	};
97};
98
99&mipi_dcphy0 {
100	status = "okay";
101};
102
103&dsi0_in_vp2 {
104	status = "okay";
105};
106
107&route_dsi0 {
108	connect = <&vp2_out_dsi0>;
109	status = "disabled";
110};
111
112&dsi1 {
113	status = "disabled";
114
115	ports {
116		#address-cells = <1>;
117		#size-cells = <0>;
118
119		port@1 {
120			reg = <1>;
121
122			dsi1_out: endpoint {
123				//remote-endpoint = <&i2c6_max96755f_in>;
124			};
125		};
126	};
127};
128
129&mipi_dcphy1 {
130	status = "okay";
131};
132
133&dsi1_in_vp3 {
134	status = "okay";
135};
136
137&route_dsi1 {
138	connect = <&vp3_out_dsi1>;
139	status = "disabled";
140};
141
142&edp0 {
143	split-mode;
144	force-hpd;
145	status = "disabled";
146};
147
148&edp0_out {
149	link-frequencies = /bits/ 64 <2700000000>;
150	remote-endpoint = <&i2c8_max96745_1_in>;
151};
152
153&hdptxphy0 {
154	status = "okay";
155};
156
157&edp0_in_vp1 {
158	status = "okay";
159};
160
161&route_edp0 {
162	connect = <&vp1_out_edp0>;
163	status = "disabled";
164};
165
166&edp1 {
167	force-hpd;
168	status = "disabled";
169};
170
171&edp1_out {
172	link-frequencies = /bits/ 64 <2700000000>;
173	remote-endpoint = <&i2c8_max96745_2_in>;
174};
175
176&hdptxphy1 {
177	status = "okay";
178};
179
180&hdmi0 {
181	status = "disabled";
182};
183
184&hdmi1 {
185	status = "disabled";
186};
187
188&hdptxphy_hdmi0 {
189	status = "disabled";
190};
191
192&hdptxphy_hdmi1 {
193	status = "disabled";
194};
195
196&i2c8 {
197	pinctrl-0 = <&i2c8m4_xfer>;
198	clock-frequency = <400000>;
199	status = "okay";
200
201	max96755f@62 {
202		compatible = "maxim,max96755f";
203		reg = <0x62>;
204		pinctrl-names = "default";
205		pinctrl-0 = <&i2c8_ser1_lock_pins>, <&i2c8_ser1_pwdnb_pins>;
206		#address-cells = <1>;
207		#size-cells = <0>;
208
209		pinctrl {
210			compatible = "maxim,max96755f-pinctrl";
211			pinctrl-names = "default";
212			pinctrl-0 = <&i2c8_max96755f_pinctrl_hog>;
213
214			i2c8_max96755f_pinctrl_hog: hog {
215				i2c {
216					groups = "I2C";
217					function = "I2C";
218				};
219			};
220
221			i2c8_max96755f_panel_pins: panel-pins {
222				bl-pwm {
223					pins = "MFP7";
224					function = "GPIO_TX_0";
225				};
226
227				tp-int {
228					pins = "MFP8";
229					function = "GPIO_RX_2";
230				};
231			};
232		};
233
234		bridge {
235			compatible = "maxim,max96755f-bridge";
236			lock-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
237			bridge_dual_link;
238
239			ports {
240				#address-cells = <1>;
241				#size-cells = <0>;
242
243				port@0 {
244					reg = <0>;
245
246					i2c8_max96755f_in: endpoint {
247						remote-endpoint = <&dsi0_out>;
248					};
249				};
250
251				port@1 {
252					reg = <1>;
253
254					i2c8_max96755f_out: endpoint {
255						remote-endpoint = <&i2c8_max96755f_panel_in>;
256					};
257				};
258			};
259		};
260
261		gmsl@0 {
262			reg = <0>;
263			clock-frequency = <400000>;
264			#address-cells = <1>;
265			#size-cells = <0>;
266
267			ts@30 {
268				compatible = "gac,gac_ts";
269				reg = <0x30>;
270				pinctrl-names = "pmx_ts_active","pmx_ts_suspend";
271				pinctrl-0 = <&touch_pin>;
272				pinctrl-1 = <&touch_pin>;
273				interrupt-parent = <&gpio1>;
274				interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
275				gac,max_x = <2560>;
276				gac,max_y = <1440>;
277			};
278
279			panel@48 {
280				compatible = "boe,ae146m1t-l10";
281				reg = <0x48>;
282				backlight = <&i2c8_max96755f_backlight>;
283				pinctrl-names = "default";
284				pinctrl-0 = <&i2c8_max96755f_panel_pins>;
285				panel_dual_link;
286
287				panel-timing {
288					clock-frequency = <303000000>;
289					hactive = <2560>;
290					vactive = <1440>;
291					hfront-porch = <122>;
292					hsync-len = <60>;
293					hback-porch = <60>;
294					vfront-porch = <340>;
295					vsync-len = <2>;
296					vback-porch = <20>;
297					hsync-active = <0>;
298					vsync-active = <0>;
299					de-active = <0>;
300					pixelclk-active = <0>;
301				};
302
303				port {
304					i2c8_max96755f_panel_in: endpoint {
305						remote-endpoint = <&i2c8_max96755f_out>;
306					};
307				};
308			};
309		};
310	};
311};
312
313&i2c8 {
314	status = "okay";
315
316	max96745@42 {
317		compatible = "maxim,max96745";
318		reg = <0x42>;
319		pinctrl-names = "default";
320		pinctrl-0 = <&i2c8_ser2_lock_pins>;
321		#address-cells = <1>;
322		#size-cells = <0>;
323
324		pinctrl {
325			compatible = "maxim,max96745-pinctrl";
326			pinctrl-names = "default";
327			pinctrl-0 = <&i2c8_max96745_1_pinctrl_hog>;
328
329			i2c8_max96745_1_pinctrl_hog: hog {
330				i2c {
331					groups = "I2C";
332					function = "I2C";
333				};
334			};
335
336			i2c8_max96745_1_panel_pins: panel-pins {
337				bl-pwm {
338					pins = "MFP11";
339					function = "GPIO_TX_A_0";
340				};
341			};
342		};
343
344		bridge {
345			compatible = "maxim,max96745-bridge";
346			lock-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
347
348			ports {
349				#address-cells = <1>;
350				#size-cells = <0>;
351
352				port@0 {
353					reg = <0>;
354
355					i2c8_max96745_1_in: endpoint {
356						remote-endpoint = <&edp0_out>;
357					};
358				};
359
360				port@1 {
361					reg = <1>;
362
363					i2c8_max96745_1_out: endpoint {
364						remote-endpoint = <&i2c8_max96745_1_panel_in>;
365					};
366				};
367			};
368		};
369
370		gmsl@0 {
371			reg = <0>;
372			clock-frequency = <400000>;
373			#address-cells = <1>;
374			#size-cells = <0>;
375
376			panel@48 {
377				compatible = "boe,av156fht-l83";
378				reg = <0x48>;
379				backlight = <&i2c8_max96745_1_backlight>;
380				pinctrl-names = "default";
381				pinctrl-0 = <&i2c8_max96745_1_panel_pins>;
382
383				panel-timing {
384					clock-frequency = <148500000>;
385					hactive = <1920>;
386					vactive = <1080>;
387					hfront-porch = <20>;
388					hsync-len = <20>;
389					hback-porch = <20>;
390					vfront-porch = <250>;
391					vsync-len = <2>;
392					vback-porch = <8>;
393					hsync-active = <0>;
394					vsync-active = <0>;
395					de-active = <0>;
396					pixelclk-active = <0>;
397				};
398
399				port {
400					i2c8_max96745_1_panel_in: endpoint {
401						remote-endpoint = <&i2c8_max96745_1_out>;
402					};
403				};
404			};
405		};
406	};
407};
408
409&i2c8 {
410	status = "okay";
411
412	max96745@60 {
413		compatible = "maxim,max96745";
414		reg = <0x60>;
415		pinctrl-names = "default";
416		pinctrl-0 = <&i2c8_ser3_lock_pins>;
417		#address-cells = <1>;
418		#size-cells = <0>;
419
420		pinctrl {
421			compatible = "maxim,max96745-pinctrl";
422			pinctrl-names = "default";
423			pinctrl-0 = <&i2c8_max96745_2_pinctrl_hog>;
424
425			i2c8_max96745_2_pinctrl_hog: hog {
426				i2c {
427					groups = "I2C";
428					function = "I2C";
429				};
430			};
431
432			i2c8_max96745_2_panel_pins: panel-pins {
433				bl-pwm {
434					pins = "MFP11";
435					function = "GPIO_TX_A_0";
436				};
437			};
438		};
439
440		bridge {
441			compatible = "maxim,max96745-bridge";
442			lock-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
443
444			ports {
445				#address-cells = <1>;
446				#size-cells = <0>;
447
448				port@0 {
449					reg = <0>;
450
451					i2c8_max96745_2_in: endpoint {
452						remote-endpoint = <&edp1_out>;
453					};
454				};
455
456				port@1 {
457					reg = <1>;
458
459					i2c8_max96745_2_out: endpoint {
460						remote-endpoint = <&i2c8_max96745_2_panel_in>;
461					};
462				};
463			};
464		};
465
466		gmsl@0 {
467			reg = <0>;
468			clock-frequency = <400000>;
469			#address-cells = <1>;
470			#size-cells = <0>;
471
472			panel@48 {
473				compatible = "boe,av156fht-l83";
474				reg = <0x48>;
475				backlight = <&i2c8_max96745_2_backlight>;
476				pinctrl-names = "default";
477				pinctrl-0 = <&i2c8_max96745_2_panel_pins>;
478
479				panel-timing {
480					clock-frequency = <148500000>;
481					hactive = <1920>;
482					vactive = <1080>;
483					hfront-porch = <20>;
484					hsync-len = <20>;
485					hback-porch = <20>;
486					vfront-porch = <250>;
487					vsync-len = <2>;
488					vback-porch = <8>;
489					hsync-active = <0>;
490					vsync-active = <0>;
491					de-active = <0>;
492					pixelclk-active = <0>;
493				};
494
495				port {
496					i2c8_max96745_2_panel_in: endpoint {
497						remote-endpoint = <&i2c8_max96745_2_out>;
498					};
499				};
500			};
501		};
502	};
503};
504
505&pinctrl {
506	serdes {
507		i2c8_ser1_lock_pins: i2c8-ser1-lock-pins {
508			rockchip,pins =
509				<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
510		};
511
512		i2c8_ser2_lock_pins: i2c8-ser2-lock-pins {
513			rockchip,pins =
514				<3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
515		};
516
517		i2c8_ser3_lock_pins: i2c8-ser3-lock-pins {
518			rockchip,pins =
519				<4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
520		};
521
522		i2c8_ser1_errb_pins: i2c8-ser1-errb-pins {
523			rockchip,pins =
524				<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
525		};
526
527		i2c8_ser2_errb_pins: i2c8-ser2-errb-pins {
528			rockchip,pins =
529				<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
530		};
531
532		i2c8_ser3_errb_pins: i2c8-ser3-errb-pins {
533			rockchip,pins =
534				<4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
535		};
536
537		i2c8_ser1_pwdnb_pins: i2c8-ser1-pwdnb-pins {
538			rockchip,pins =
539				<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
540		};
541	};
542
543	touch {
544		touch_pin: touch-pin {
545			rockchip,pins =
546				<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
547		};
548	};
549};
550
551&pwm0 {
552	pinctrl-0 = <&pwm0m2_pins>;
553	status = "okay";
554};
555
556&pwm1 {
557	pinctrl-0 = <&pwm1m1_pins>;
558	status = "okay";
559};
560
561&pwm7 {
562	pinctrl-0 = <&pwm7m3_pins>;
563	status = "okay";
564};
565