1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
4 */
5
6/dts-v1/;
7
8#include "rk3399-excavator-sapphire.dtsi"
9#include "rk3399-linux.dtsi"
10#include <dt-bindings/input/input.h>
11
12/ {
13	model = "Rockchip RK3399 Excavator Board (Linux Opensource)";
14	compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399";
15
16	fiq_debugger: fiq-debugger {
17		compatible = "rockchip,fiq-debugger";
18		rockchip,serial-id = <2>;
19		rockchip,signal-irq = <182>;
20		rockchip,wake-irq = <0>;
21		rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
22		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
23		pinctrl-names = "default";
24		pinctrl-0 = <&uart2c_xfer>;
25	};
26
27	edp_panel: edp-panel {
28		compatible = "lg,lp079qx1-sp0v", "panel-simple";
29		backlight = <&backlight>;
30		power-supply = <&vcc3v3_s0>;
31		enable-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
32		pinctrl-names = "default";
33		pinctrl-0 = <&lcd_panel_reset>;
34
35		ports {
36			panel_in_edp: endpoint {
37				remote-endpoint = <&edp_out_panel>;
38			};
39		};
40	};
41
42	hdmi_sound: hdmi-sound {
43		status = "okay";
44	};
45
46	gpio-keys {
47		compatible = "gpio-keys";
48		#address-cells = <1>;
49		#size-cells = <0>;
50		autorepeat;
51
52		pinctrl-names = "default";
53		pinctrl-0 = <&pwrbtn>;
54
55		button@0 {
56			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
57			linux,code = <KEY_POWER>;
58			label = "GPIO Key Power";
59			linux,input-type = <1>;
60			gpio-key,wakeup = <1>;
61			debounce-interval = <100>;
62		};
63	};
64
65	vccadc_ref: vccadc-ref {
66		compatible = "regulator-fixed";
67		regulator-name = "vcc1v8_sys";
68		regulator-always-on;
69		regulator-boot-on;
70		regulator-min-microvolt = <1800000>;
71		regulator-max-microvolt = <1800000>;
72	};
73
74	ext_cam_clk: external-camera-clock {
75		compatible = "fixed-clock";
76		clock-frequency = <27000000>;
77		clock-output-names = "CLK_CAMERA_27MHZ";
78		#clock-cells = <0>;
79	};
80
81	adc-keys {
82		compatible = "adc-keys";
83		io-channels = <&saradc 1>;
84		io-channel-names = "buttons";
85		poll-interval = <100>;
86		keyup-threshold-microvolt = <1800000>;
87
88		button-up {
89			label = "Volume Up";
90			linux,code = <KEY_VOLUMEUP>;
91			press-threshold-microvolt = <100000>;
92		};
93
94		button-down {
95			label = "Volume Down";
96			linux,code = <KEY_VOLUMEDOWN>;
97			press-threshold-microvolt = <300000>;
98		};
99
100		back {
101			label = "Back";
102			linux,code = <KEY_BACK>;
103			press-threshold-microvolt = <985000>;
104		};
105
106		menu {
107			label = "Menu";
108			linux,code = <KEY_MENU>;
109			press-threshold-microvolt = <1314000>;
110		};
111	};
112};
113
114&rkisp1_0 {
115	status = "okay";
116
117	port {
118		#address-cells = <1>;
119		#size-cells = <0>;
120
121		isp0_mipi_in: endpoint@0 {
122			reg = <0>;
123			remote-endpoint = <&dphy_rx0_out>;
124		};
125	};
126};
127
128&mipi_dphy_rx0 {
129	status = "okay";
130
131	ports {
132		#address-cells = <1>;
133		#size-cells = <0>;
134
135		port@0 {
136			reg = <0>;
137			#address-cells = <1>;
138			#size-cells = <0>;
139
140			mipi_in_ucam0: endpoint@1 {
141				reg = <1>;
142				remote-endpoint = <&ucam_out0>;
143				data-lanes = <1 2>;
144			};
145		};
146
147		port@1 {
148			reg = <1>;
149			#address-cells = <1>;
150			#size-cells = <0>;
151
152			dphy_rx0_out: endpoint@0 {
153				reg = <0>;
154				remote-endpoint = <&isp0_mipi_in>;
155			};
156		};
157	};
158};
159
160&isp0_mmu {
161	status = "okay";
162};
163
164&rkisp1_1 {
165	status = "okay";
166
167	port {
168		#address-cells = <1>;
169		#size-cells = <0>;
170
171		isp1_mipi_in: endpoint@0 {
172			reg = <0>;
173			remote-endpoint = <&dphy_tx1rx1_out>;
174		};
175	};
176};
177
178&mipi_dphy_tx1rx1 {
179	status = "okay";
180
181	ports {
182		#address-cells = <1>;
183		#size-cells = <0>;
184
185		port@0 {
186			reg = <0>;
187			#address-cells = <1>;
188			#size-cells = <0>;
189
190			mipi_in_ucam1: endpoint@1 {
191				reg = <1>;
192				/* Unlinked camera */
193				//remote-endpoint = <&ucam_out1>;
194				data-lanes = <1 2>;
195			};
196		};
197
198		port@1 {
199			reg = <1>;
200			#address-cells = <1>;
201			#size-cells = <0>;
202
203			dphy_tx1rx1_out: endpoint@0 {
204				reg = <0>;
205				remote-endpoint = <&isp1_mipi_in>;
206			};
207		};
208	};
209};
210
211&isp1_mmu {
212	status = "okay";
213};
214
215&saradc {
216	vref-supply = <&vccadc_ref>;
217};
218
219&backlight {
220	status = "okay";
221	enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
222};
223
224&cdn_dp {
225	status = "disabled";
226};
227
228&display_subsystem {
229	status = "okay";
230};
231
232&dsi_in_vopl {
233	status = "okay";
234};
235
236&dsi_in_vopb {
237	status = "disabled";
238};
239
240&dsi {
241	status = "okay";
242
243	panel@0 {
244		compatible ="simple-panel-dsi";
245		reg = <0>;
246
247		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>;
248		dsi,format = <MIPI_DSI_FMT_RGB888>;
249		dsi,lanes = <4>;
250
251		display-timings {
252			native-mode = <&timing0_720p_30hz>;
253
254			timing0_720p_30hz: timing0-720p-30hz {
255				clock-frequency = <96000000>;
256				hactive = <1280>;
257				vactive = <720>;
258				hback-porch = <200>;
259				hfront-porch = <1000>;
260				vback-porch = <100>;
261				vfront-porch = <200>;
262				hsync-len = <200>;
263				vsync-len = <200>;
264				hsync-active = <0>;
265				vsync-active = <0>;
266				de-active = <0>;
267				pixelclk-active = <0>;
268			};
269
270			timing1_1080p_30hz: timing0-1080p-30hz {
271				clock-frequency = <76000000>;
272				hactive = <1920>;
273				vactive = <1080>;
274				hback-porch = <100>;
275				hfront-porch = <200>;
276				vback-porch = <10>;
277				vfront-porch = <10>;
278				hsync-len = <20>;
279				vsync-len = <20>;
280				hsync-active = <0>;
281				vsync-active = <0>;
282				de-active = <0>;
283				pixelclk-active = <0>;
284			};
285
286			timing2_1080p_87hz: timing1-1080p-87hz {
287				clock-frequency = <220000000>;
288				hactive = <1920>;
289				vactive = <1080>;
290				hback-porch = <200>;
291				hfront-porch = <120>;
292				vback-porch = <20>;
293				vfront-porch = <2>;
294				hsync-len = <20>;
295				vsync-len = <10>;
296				hsync-active = <0>;
297				vsync-active = <0>;
298				de-active = <0>;
299				pixelclk-active = <0>;
300			};
301		};
302
303		ports {
304			#address-cells = <1>;
305			#size-cells = <0>;
306
307			port@0 {
308				reg = <0>;
309				panel_in_dsi: endpoint {
310					remote-endpoint = <&dsi_out_panel>;
311				};
312			};
313		};
314	};
315
316	ports {
317		#address-cells = <1>;
318		#size-cells = <0>;
319
320		port@1 {
321			reg = <1>;
322			dsi_out_panel: endpoint {
323				remote-endpoint = <&panel_in_dsi>;
324			};
325		};
326	};
327};
328
329&edp_in_vopl {
330	status = "disabled";
331};
332
333&edp_in_vopb {
334	status = "okay";
335};
336
337&route_edp {
338	status = "okay";
339};
340
341&edp {
342	force-hpd;
343	status = "okay";
344
345	ports {
346		edp_out: port@1 {
347			reg = <1>;
348			#address-cells = <1>;
349			#size-cells = <0>;
350
351			edp_out_panel: endpoint@0 {
352				reg = <0>;
353				remote-endpoint = <&panel_in_edp>;
354			};
355		};
356	};
357};
358
359&hdmi {
360	/* remove the hdmi_cec, reused by edp_hpd */
361	pinctrl-0 = <&hdmi_i2c_xfer>;
362	#address-cells = <1>;
363	#size-cells = <0>;
364	#sound-dai-cells = <0>;
365	status = "okay";
366};
367
368&i2c1 {
369	status = "okay";
370
371	gsl3673: gsl3673@40 {
372		compatible = "GSL,GSL3673";
373		reg = <0x40>;
374		screen_max_x = <1536>;
375		screen_max_y = <2048>;
376		irq_gpio_number = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
377		rst_gpio_number = <&gpio4 22 GPIO_ACTIVE_HIGH>;
378	};
379
380	tc358749x: tc358749x@f {
381		compatible = "toshiba,tc358749";
382		reg = <0xf>;
383		clocks = <&ext_cam_clk>;
384		clock-names = "refclk";
385		reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
386		interrupt-parent = <&gpio2>;
387		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
388		pinctrl-names = "default";
389		pinctrl-0 = <&hdmiin_gpios>;
390		status = "disabled";
391		port {
392			hdmiin_out0: endpoint {
393				/* Unlinked mipi dphy rx0 */
394				//remote-endpoint = <&mipi_in_ucam0>;
395				data-lanes = <1 2 3 4>;
396				clock-noncontinuous;
397				link-frequencies =
398					/bits/ 64 <297000000>;
399			};
400		};
401	};
402
403	vm149c: vm149c@0c {
404		compatible = "silicon touch,vm149c";
405		status = "okay";
406		reg = <0x0c>;
407		rockchip,camera-module-index = <0>;
408		rockchip,camera-module-facing = "back";
409	};
410
411	ov13850: ov13850@10 {
412		compatible = "ovti,ov13850";
413		status = "okay";
414		reg = <0x10>;
415		clocks = <&cru SCLK_CIF_OUT>;
416		clock-names = "xvclk";
417
418		/* conflict with csi-ctl-gpios */
419		reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
420		pwdn-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
421		pinctrl-names = "rockchip,camera_default";
422		pinctrl-0 = <&cif_clkout>;
423		lens-focus = <&vm149c>;
424
425		port {
426			ucam_out0: endpoint {
427				remote-endpoint = <&mipi_in_ucam0>;
428				data-lanes = <1 2>;
429			};
430		};
431	};
432};
433
434&i2c4 {
435	status = "okay";
436};
437
438&pcie_phy {
439	status = "okay";
440};
441
442&pcie0 {
443	status = "okay";
444};
445
446&pinctrl {
447	buttons {
448		pwrbtn: pwrbtn {
449			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
450		};
451	};
452
453	lcd-panel {
454		lcd_panel_reset: lcd-panel-reset {
455			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
456		};
457	};
458
459	hdmiin {
460		hdmiin_gpios: hdmiin-gpios {
461			rockchip,pins =
462				<2 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>,
463				<2 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>,
464				<2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>,
465				<2 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>,
466				<2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>,
467				<2 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>,
468				<2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
469		};
470	};
471};
472
473&vopb {
474	status = "okay";
475};
476
477&vopb_mmu {
478	status = "okay";
479};
480
481&vopl {
482	status = "okay";
483};
484
485&vopl_mmu {
486	status = "okay";
487};
488