1Device-Tree bindings for rockchip mipi dsi lcd driver 2 3Required properties: 4 - rockchip,screen_init: Whether you need this screen initialization. 5 <0>: Don't need to be initialized. 6 <1>: Do need to be initialized. 7 8 - rockchip,dsi_lane: mipi lcd data lane number. 9 10 - rockchip,dsi_hs_clk: mipi lcd high speed clock. 11 12 - rockchip,mipi_dsi_num: mipi lcd dsi number. 13 14 - mipi_lcd_rst:mipi_lcd_rst: Should specify pin control groups used for reset this lcd. 15 16 - mipi_lcd_en:mipi_lcd_en: Should specify pin control groups used for enable this lcd. 17 18 - rockchip,gpios: gpio pin 19 20 - rockchip,delay: delay the millisecond. 21 22 - rockchip,cmd_debug : debug the cammands. 23 <0>: close the debug; 24 <1>: open the debug; 25 26 - rockchip,on-cmds1: write cammand to mipi lcd. 27 28- rockchip,cmd_type: 29 <LPDT>: close the debug; 30 <HSDT>: open the debug; 31 32 - rockchip,dsi_id: write cammand to mipi lcd(left and right). 33 <0>: left dsi; 34 <1>: right dsi; 35 <2>: left and right dsis; 36 37 - rockchip,cmd: cammand context. 38 The first parameter was data type; 39 The second parameter was index(register); 40 The third and ... parameter are cammand context; 41 42 - rockchip,cmd_delay: delay the millisecond. 43 44 - screen-type: mipi lcd type. 45 <SCREEN_DUAL_MIPI>: Dual channel mipi lcd. 46 <SCREEN_MIPI>: single channel mipi lcd. 47 48 - lvds-format:No relationship. 49 50 - out-face: DPI color coding as follows: 51 <OUT_P888>:24bit 52 <OUT_P666>:18bit 53 <OUT_P565>:16bit 54 55 - hactive, vactive: display resolution 56 - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters 57 in pixels 58 vfront-porch, vback-porch, vsync-len: vertical display timing parameters in 59 lines 60 - clock-frequency: display clock in Hz 61 62 - swap-rb :exchange of red and blue. 63 - swap-rg :exchange of red and green. 64 - swap-gb :exchange of green and blue. 65 66 - hsync-active: hsync pulse is active low/high/ignored 67 - vsync-active: vsync pulse is active low/high/ignored 68 - de-active: data-enable pulse is active low/high/ignored 69 - pixelclk-active: with 70 - active high = drive pixel data on rising edge/ 71 sample data on falling edge 72 - active low = drive pixel data on falling edge/ 73 sample data on rising edge 74 - ignored = ignored 75 - interlaced (bool): boolean to enable interlaced mode 76 - doublescan (bool): boolean to enable doublescan mode 77 78All the optional properties that are not bool follow the following logic: 79 <1>: high active 80 <0>: low active 81 omitted: not used on hardware 82 83There are different ways of describing the capabilities of a display. The 84devicetree representation corresponds to the one commonly found in datasheets 85for displays. If a display supports multiple signal timings, the native-mode 86can be specified. 87 88The parameters are defined as: 89 90 +----------+-------------------------------------+----------+-------+ 91 | | �� | | | 92 | | |vback_porch | | | 93 | | �� | | | 94 +----------#######################################----------+-------+ 95 | # �� # | | 96 | # | # | | 97 | hback # | # hfront | hsync | 98 | porch # | hactive # porch | len | 99 |<-------->#<-------+--------------------------->#<-------->|<----->| 100 | # | # | | 101 | # |vactive # | | 102 | # | # | | 103 | # �� # | | 104 +----------#######################################----------+-------+ 105 | | �� | | | 106 | | |vfront_porch | | | 107 | | �� | | | 108 +----------+-------------------------------------+----------+-------+ 109 | | �� | | | 110 | | |vsync_len | | | 111 | | �� | | | 112 +----------+-------------------------------------+----------+-------+ 113 114 115Example: 116 117{ 118 /* about mipi */ 119 disp_mipi_init: mipi_dsi_init{ 120 rockchip,screen_init = <1>; 121 rockchip,dsi_lane = <4>; 122 rockchip,dsi_hs_clk = <1020>; 123 rockchip,mipi_dsi_num = <2>; 124 }; 125 disp_mipi_power_ctr: mipi_power_ctr { 126 mipi_lcd_rst:mipi_lcd_rst{ 127 rockchip,gpios = <&gpio7 GPIO_B2 GPIO_ACTIVE_HIGH>; 128 rockchip,delay = <10>; 129 }; 130 /*mipi_lcd_en:mipi_lcd_en { 131 rockchip,gpios = <&gpio6 GPIO_A7 GPIO_ACTIVE_HIGH>; 132 rockchip,delay = <10>; 133 };*/ 134 }; 135 disp_mipi_init_cmds: screen-on-cmds { 136 rockchip,cmd_debug = <0>; 137 rockchip,on-cmds1 { 138 rockchip,cmd_type = <LPDT>; 139 rockchip,dsi_id = <2>; 140 rockchip,cmd = <0x05 0x01>; //set soft reset 141 rockchip,cmd_delay = <10>; 142 }; 143 }; 144 145 disp_timings: display-timings { 146 native-mode = <&timing0>; 147 timing0: timing0 { 148 screen-type = <SCREEN_DUAL_MIPI>; 149 lvds-format = <LVDS_8BIT_2>; 150 out-face = <OUT_P888>; 151 clock-frequency = <285000000>; 152 hactive = <2560>; 153 vactive = <1600>; 154 155 hsync-len = <38>;//19 156 hback-porch = <80>;//40 157 hfront-porch = <246>;//123 158 159 vsync-len = <4>; 160 vback-porch = <4>; 161 vfront-porch = <12>; 162 163 hsync-active = <0>; 164 vsync-active = <0>; 165 de-active = <0>; 166 pixelclk-active = <0>; 167 swap-rb = <0>; 168 swap-rg = <0>; 169 swap-gb = <0>; 170 }; 171 }; 172}; 173 174