Searched +full:srom +full:- +full:timing (Results 1 – 25 of 37) sorted by relevance
12
1 // SPDX-License-Identifier: GPL-2.06 // Exynos - SROM Controller support17 #include "exynos-srom.h"20 /* SROM side */29 * struct exynos_srom_reg_dump: register dump of SROM Controller registers.30 * @offset: srom register offset from the controller base address.39 * struct exynos_srom: platform data for exynos srom controller driver.41 * @reg_base: srom base address67 static int exynos_srom_configure_bank(struct exynos_srom *srom, in exynos_srom_configure_bank() argument71 u32 timing[6]; in exynos_srom_configure_bank() local[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Samsung Exynos SoC SROM Controller driver10 - Krzysztof Kozlowski <krzk@kernel.org>13 The SROM controller can be used to attach external peripherals. In this case19 - const: samsung,exynos4210-srom24 "#address-cells":27 "#size-cells":[all …]
1 // SPDX-License-Identifier: GPL-2.09 /dts-v1/;11 #include <dt-bindings/interrupt-controller/irq.h>22 stdout-path = "serial2:115200n8";26 compatible = "fixed-clock";27 clock-frequency = <24000000>;28 clock-output-names = "fin_pll";29 #clock-cells = <0>;32 pmic_ap_clk: pmic-ap-clk {34 compatible = "fixed-clock";[all …]
1 .. SPDX-License-Identifier: GPL-2.010 - DE425 TP/COAX EISA11 - DE434 TP PCI12 - DE435 TP/COAX/AUI PCI13 - DE450 TP/COAX/AUI PCI14 - DE500 10/100 PCI Fasternet17 Digital Semiconductor SROM Specification. The driver currently20 - DC21040 (no SROM)21 - DC21041[A]22 - DC21140[A][all …]
5 * SPDX-License-Identifier: GPL-2.0+14 #define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/15 /* 1-> Byte base address*/19 #define SROMC_BC_TACS(x) (x << 28) /* address set-up */20 #define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */50 u8 bank; /* srom bank number */52 unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */ member
5 * SPDX-License-Identifier: GPL-2.0+28 #include <dwc3-uboot.h>81 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); in board_init()83 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { in board_init()85 return -1; in board_init()93 gd->ram_size -= size; in board_init()94 gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; in board_init()106 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); in dram_init()120 gd->bd->bi_dram[i].start = addr; in dram_init_banksize()121 gd->bd->bi_dram[i].size = size; in dram_init_banksize()[all …]
48 * Usage example, e.g. a three-bit field (bits 4-6):52 * regval = R_REG(osh, ®s->regfoo);55 * W_REG(osh, ®s->regfoo, regval);58 (((unsigned)1 << (width)) - 1)67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */92 #define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */145 ((uint)((wlc)->band->bandunit ? BAND_2G_INDEX : BAND_5G_INDEX))152 * gmode_user: user config gmode, operating band->gmode is different.[all …]
3 * Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de>50 /* n-mode support capability */82 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)133 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */167 #define BRCMS_PLCP_AUTO -1172 #define BRCMS_PROTECTION_AUTO -1199 /* MSC in use,indicates b0-6 holds an mcs */361 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK] in brcms_basic_rate()363 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK]; in brcms_basic_rate()376 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME : in get_sifs()[all …]
12 /dts-v1/;14 #include <dt-bindings/interrupt-controller/irq.h>45 srom-timing = <1 9 12 1 6 1 1>;50 phy-mode = "mii";55 samsung,codec-type = "wm8994";65 compatible = "wolfson,wm8994-codec";77 samsung,min-temp = <25>;78 samsung,max-temp = <125>;79 samsung,start-warning = <95>;80 samsung,start-tripping = <105>;[all …]
41 Digital Semiconductor SROM Specification. The driver currently44 DC21040 (no SROM)56 SMC9332 (w/new SROM)72 measurement. Their error is +/-20k on a quiet (private) network and also118 3) compile de4x5.c, but include -DMODULE in the command line to ensure140 I've changed the timing routines to use the kernel timer and scheduling150 The SMC9332 card has a non-compliant SROM which needs fixing - I have151 patched this driver to detect it because the SROM format used complies152 to a previous DEC-STD format.159 I have added SROM decoding routines to make this driver work with any[all …]
16 #define DE4X5_BMR iobase+(0x000 << lp->bus) /* Bus Mode Register */17 #define DE4X5_TPD iobase+(0x008 << lp->bus) /* Transmit Poll Demand Reg */18 #define DE4X5_RPD iobase+(0x010 << lp->bus) /* Receive Poll Demand Reg */19 #define DE4X5_RRBA iobase+(0x018 << lp->bus) /* RX Ring Base Address Reg */20 #define DE4X5_TRBA iobase+(0x020 << lp->bus) /* TX Ring Base Address Reg */21 #define DE4X5_STS iobase+(0x028 << lp->bus) /* Status Register */22 #define DE4X5_OMR iobase+(0x030 << lp->bus) /* Operation Mode Register */23 #define DE4X5_IMR iobase+(0x038 << lp->bus) /* Interrupt Mask Register */24 #define DE4X5_MFC iobase+(0x040 << lp->bus) /* Missed Frame Counter */25 #define DE4X5_APROM iobase+(0x048 << lp->bus) /* Ethernet Address PROM */[all …]
1 // SPDX-License-Identifier: GPL-2.023 #include <asm/mach-types.h>28 #include "regs-gpio.h"29 #include "gpio-samsung.h"32 #include <linux/soc/samsung/s3c-adc.h>36 #include <linux/platform_data/mtd-nand-s3c2410.h>37 #include <linux/platform_data/touchscreen-s3c2410.h>43 #include "regs-modem-s3c64xx.h"44 #include "regs-srom-s3c64xx.h"96 .id = -1,[all …]
1 // SPDX-License-Identifier: GPL-2.022 #include <asm/mach-types.h>27 #include "regs-gpio.h"28 #include "gpio-samsung.h"30 #include <linux/soc/samsung/s3c-adc.h>34 #include <linux/platform_data/mtd-nand-s3c2410.h>35 #include <linux/platform_data/mmc-sdhci-s3c.h>37 #include <linux/platform_data/touchscreen-s3c2410.h>44 #include "regs-modem-s3c64xx.h"45 #include "regs-srom-s3c64xx.h"[all …]
1 // SPDX-License-Identifier: GPL-2.029 #include <linux/platform_data/s3c-hsotg.h>52 #include <asm/mach-types.h>54 #include "regs-gpio.h"55 #include "gpio-samsung.h"56 #include <linux/platform_data/ata-samsung_cf.h>57 #include <linux/platform_data/i2c-s3c2410.h>59 #include "gpio-cfg.h"63 #include <linux/soc/samsung/s3c-adc.h>64 #include <linux/platform_data/touchscreen-s3c2410.h>[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */96 #define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */127 #define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */237 #define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)238 #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)239 #define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)240 #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)256 return -ENOTSUPP; in bcma_core_pci_pcibios_map_irq()260 return -ENOTSUPP; in bcma_core_pci_plat_dev_init()
1 /* SPDX-License-Identifier: GPL-2.0 */5 * Copyright (C) 1999-2017, Broadcom Corporation26 * <<Broadcom-WL-IPTag/Open:>>28 * $Id: pcie_core.h 673814 2016-12-05 06:10:24Z $101 #define IFRM_FR_PER_VECREG_MASK ((0x1 << IFRM_FR_PER_VECREG_SHIFT) - 1)204 /* 0x400 - 0x7FF, PCIE Cfg Space, note: not used anymore in PcieGen2 */212 uint32 PAD[3]; /* 0x134-0x138-0x13c */214 pcie_doorbell_t dbls[PCIEDEV_MAX_DMAS]; /* 0x140 - 0x17F */232 uint32 PAD[7]; /* 0x1C4 - 0x1DF */236 uint32 PAD[5]; /* 0x1EC - 0x1FF */[all …]
... d dbm, %d mW Override is %s -o -d -q -m Error: Missing ...
6 * Copyright (C) 1999-2017, Broadcom Corporation27 * <<Broadcom-WL-IPTag/Open:>>29 * $Id: pcie_core.h 698652 2017-05-10 10:39:24Z $103 #define IFRM_FR_PER_VECREG_MASK ((0x1 << IFRM_FR_PER_VECREG_SHIFT) - 1)226 /* 0x400 - 0x7FF, PCIE Cfg Space, note: not used anymore in PcieGen2 */234 uint32 PAD[3]; /* 0x134-0x138-0x13c */236 pcie_doorbell_t dbls[PCIEDEV_MAX_DMAS]; /* 0x140 - 0x17F */257 uint32 PAD[4]; /* 0x1D0 - 0x1DF */261 uint32 PAD[5]; /* 0x1EC - 0x1FF */262 pcie_devdmaregs_t h2d0_dmaregs; /* 0x200 - 0x23c */[all …]
11 * Copyright (C) 1999-2017, Broadcom Corporation32 * <<Broadcom-WL-IPTag/Open:>>61 * BCME_.. error codes are extended by various features - e.g. FTM, NAN, SAE etc.68 * The error codes -4096 ... -5119 are reserved for firmware signing.70 * Next available (inclusive) range: [-6*1024 + 1, -5*1024]75 /* 11ax trigger frame format - versioning info */122 (sizeof(wl_dfs_forced_t) + (((n) < 1) ? (0) : (((n) - 1)* sizeof(chanspec_t))))138 #define DFS_SCAN_S_IDLE -1253 * will see OBSS, [means that, we false detected that OBSS-is-gone353 * Per-BSS information structure.[all …]
2 # (C) Copyright 2000 - 20135 # SPDX-License-Identifier: GPL-2.0+11 This directory contains the source code for U-Boot, a boot loader for17 The development of U-Boot is closely related to Linux: some parts of39 scattered throughout the U-Boot source identifying the people or43 actual U-Boot source tree; however, it can be created dynamically53 U-Boot, you should send a message to the U-Boot mailing list at54 <u-boot@lists.denx.de>. There is also an archive of previous traffic55 on the mailing list - please search the archive before asking FAQ's.56 Please see http://lists.denx.de/pipermail/u-boot and[all …]
21 * <<Broadcom-WL-IPTag/Dual:>>133 #define IFRM_FR_PER_VECREG_MASK ((0x1 << IFRM_FR_PER_VECREG_SHIFT) - 1)261 /* 0x400 - 0x7FF, PCIE Cfg Space, note: not used anymore in PcieGen2 */269 uint32 PAD[3]; /* 0x134-0x138-0x13c */271 pcie_doorbell_t dbls[PCIEDEV_MAX_DMAS]; /* 0x140 - 0x17F */292 uint32 PAD[4]; /* 0x1D0 - 0x1DF */297 uint32 PAD[4]; /* 0x1F0 - 0x1FF */298 pcie_devdmaregs_t h2d0_dmaregs; /* 0x200 - 0x23c */299 pcie_devdmaregs_t d2h0_dmaregs; /* 0x240 - 0x27c */300 pcie_devdmaregs_t h2d1_dmaregs; /* 0x280 - 0x2bc */[all …]