1 /* 2 * BCM43XX PCIE core hardware definitions. 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 #ifndef _PCIE_CORE_H 24 #define _PCIE_CORE_H 25 26 #include <sbhnddma.h> 27 #include <siutils.h> 28 29 #define REV_GE_73(rev) (PCIECOREREV((rev)) >= 73) 30 #define REV_GE_69(rev) (PCIECOREREV((rev)) >= 69) 31 #define REV_GE_68(rev) (PCIECOREREV((rev)) >= 68) 32 #define REV_GE_64(rev) (PCIECOREREV((rev)) >= 64) 33 #define REV_GE_15(rev) (PCIECOREREV((rev)) >= 15) 34 35 /* cpp contortions to concatenate w/arg prescan */ 36 #ifndef PAD 37 #define _PADLINE(line) pad ## line 38 #define _XSTR(line) _PADLINE(line) 39 #define PAD _XSTR(__LINE__) 40 #endif 41 42 /* PCIE Enumeration space offsets */ 43 #define PCIE_CORE_CONFIG_OFFSET 0x0 44 #define PCIE_FUNC0_CONFIG_OFFSET 0x400 45 #define PCIE_FUNC1_CONFIG_OFFSET 0x500 46 #define PCIE_FUNC2_CONFIG_OFFSET 0x600 47 #define PCIE_FUNC3_CONFIG_OFFSET 0x700 48 #define PCIE_SPROM_SHADOW_OFFSET 0x800 49 #define PCIE_SBCONFIG_OFFSET 0xE00 50 51 #define PCIEDEV_MAX_DMAS 4 52 53 /* PCIE Bar0 Address Mapping. Each function maps 16KB config space */ 54 #define PCIE_DEV_BAR0_SIZE 0x4000 55 #define PCIE_BAR0_WINMAPCORE_OFFSET 0x0 56 #define PCIE_BAR0_EXTSPROM_OFFSET 0x1000 57 #define PCIE_BAR0_PCIECORE_OFFSET 0x2000 58 #define PCIE_BAR0_CCCOREREG_OFFSET 0x3000 59 60 /* different register spaces to access thr'u pcie indirect access */ 61 #define PCIE_CONFIGREGS 1 /* Access to config space */ 62 #define PCIE_PCIEREGS 2 /* Access to pcie registers */ 63 64 #define PCIEDEV_HOSTADDR_MAP_BASE 0x8000000 65 #define PCIEDEV_HOSTADDR_MAP_WIN_MASK 0xFE000000 66 67 #define PCIEDEV_TR0_WINDOW_START 0x08000000 68 #define PCIEDEV_TR0_WINDOW_END 0x09FFFFFF 69 70 #define PCIEDEV_TR1_WINDOW_START 0x0A000000 71 #define PCIEDEV_TR1_WINDOW_END 0x0BFFFFFF 72 73 #define PCIEDEV_TR2_WINDOW_START 0x0C000000 74 #define PCIEDEV_TR2_WINDOW_END 0x0DFFFFFF 75 76 #define PCIEDEV_TR3_WINDOW_START 0x0E000000 77 #define PCIEDEV_TR3_WINDOW_END 0x0FFFFFFF 78 79 #define PCIEDEV_TRANS_WIN_LEN 0x2000000 80 #define PCIEDEV_ARM_ADDR_SPACE 0x0FFFFFFF 81 82 /* PCIe translation windoes */ 83 #define PCIEDEV_TRANS_WIN_0 0 84 #define PCIEDEV_TRANS_WIN_1 1 85 #define PCIEDEV_TRANS_WIN_2 2 86 #define PCIEDEV_TRANS_WIN_3 3 87 88 #define PCIEDEV_ARM_ADDR(host_addr, win) \ 89 (((host_addr) & 0x1FFFFFF) | ((win) << 25) | PCIEDEV_HOSTADDR_MAP_BASE) 90 91 /* Current mapping of PCIe translation windows to SW features */ 92 93 #define PCIEDEV_TRANS_WIN_TRAP_HANDLER PCIEDEV_TRANS_WIN_0 94 #define PCIEDEV_TRANS_WIN_HOSTMEM PCIEDEV_TRANS_WIN_1 95 #define PCIEDEV_TRANS_WIN_SWPAGING PCIEDEV_TRANS_WIN_1 96 #define PCIEDEV_TRANS_WIN_BT PCIEDEV_TRANS_WIN_2 97 #define PCIEDEV_TRANS_WIN_FWTRACE PCIEDEV_TRANS_WIN_3 98 99 /* dma regs to control the flow between host2dev and dev2host */ 100 typedef volatile struct pcie_devdmaregs { 101 dma64regs_t tx; 102 uint32 PAD[2]; 103 dma64regs_t rx; 104 uint32 PAD[2]; 105 } pcie_devdmaregs_t; 106 107 #define PCIE_DB_HOST2DEV_0 0x1 108 #define PCIE_DB_HOST2DEV_1 0x2 109 #define PCIE_DB_DEV2HOST_0 0x3 110 #define PCIE_DB_DEV2HOST_1 0x4 111 #define PCIE_DB_DEV2HOST1_0 0x5 112 113 /* door bell register sets */ 114 typedef struct pcie_doorbell { 115 uint32 host2dev_0; 116 uint32 host2dev_1; 117 uint32 dev2host_0; 118 uint32 dev2host_1; 119 } pcie_doorbell_t; 120 121 /* Flow Ring Manager */ 122 #define IFRM_FR_IDX_MAX 256 123 #define IFRM_FR_CONFIG_GID 2 124 #define IFRM_FR_GID_MAX 4 125 #define IFRM_FR_DEV_MAX 8 126 #define IFRM_FR_TID_MAX 8 127 #define IFRM_FR_DEV_VALID 2 128 129 #define IFRM_VEC_REG_BITS 32 130 131 #define IFRM_FR_PER_VECREG 4 132 #define IFRM_FR_PER_VECREG_SHIFT 2 133 #define IFRM_FR_PER_VECREG_MASK ((0x1 << IFRM_FR_PER_VECREG_SHIFT) - 1) 134 135 #define IFRM_VEC_BITS_PER_FR (IFRM_VEC_REG_BITS/IFRM_FR_PER_VECREG) 136 137 /* IFRM_DEV_0 : d11AC, IFRM_DEV_1 : d11AD */ 138 #define IFRM_DEV_0 0 139 #define IFRM_DEV_1 1 140 #define IHRM_FR_SW_MASK (1u << IFRM_DEV_0) 141 #define IHRM_FR_HW_MASK (1u << IFRM_DEV_1) 142 143 #define IFRM_FR_GID_0 0 144 #define IFRM_FR_GID_1 1 145 #define IFRM_FR_GID_2 2 146 #define IFRM_FR_GID_3 3 147 148 #define IFRM_TIDMASK 0xffffffff 149 150 /* ifrm_ctrlst register */ 151 #define IFRM_EN (1<<0) 152 #define IFRM_BUFF_INIT_DONE (1<<1) 153 #define IFRM_COMPARE_EN0 (1<<4) 154 #define IFRM_COMPARE_EN1 (1<<5) 155 #define IFRM_COMPARE_EN2 (1<<6) 156 #define IFRM_COMPARE_EN3 (1<<7) 157 #define IFRM_INIT_DV0 (1<<8) 158 #define IFRM_INIT_DV1 (1<<9) 159 #define IFRM_INIT_DV2 (1<<10) 160 #define IFRM_INIT_DV3 (1<<11) 161 162 /* ifrm_msk_arr.addr, ifrm_tid_arr.addr register */ 163 #define IFRM_ADDR_SHIFT 0 164 #define IFRM_FRG_ID_SHIFT 8 165 166 /* ifrm_vec.diff_lat register */ 167 #define IFRM_DV_LAT (1<<0) 168 #define IFRM_DV_LAT_DONE (1<<1) 169 #define IFRM_SDV_OFFSET_SHIFT 4 170 #define IFRM_SDV_FRGID_SHIFT 8 171 #define IFRM_VECSTAT_MASK 0x3 172 #define IFRM_VEC_MASK 0xff 173 174 /* HMAP Windows */ 175 #define HMAP_MAX_WINDOWS 8 176 177 /* idma frm array */ 178 typedef struct pcie_ifrm_array { 179 uint32 addr; 180 uint32 data; 181 } pcie_ifrm_array_t; 182 183 /* idma frm vector */ 184 typedef struct pcie_ifrm_vector { 185 uint32 diff_lat; 186 uint32 sav_tid; 187 uint32 sav_diff; 188 uint32 PAD[1]; 189 } pcie_ifrm_vector_t; 190 191 /* idma frm interrupt */ 192 typedef struct pcie_ifrm_intr { 193 uint32 intstat; 194 uint32 intmask; 195 } pcie_ifrm_intr_t; 196 197 /* HMAP window register set */ 198 typedef volatile struct pcie_hmapwindow { 199 uint32 baseaddr_lo; /* BaseAddrLower */ 200 uint32 baseaddr_hi; /* BaseAddrUpper */ 201 uint32 windowlength; /* Window Length */ 202 uint32 PAD[1]; 203 } pcie_hmapwindow_t; 204 205 typedef struct pcie_hmapviolation { 206 uint32 hmap_violationaddr_lo; /* violating address lo */ 207 uint32 hmap_violationaddr_hi; /* violating addr hi */ 208 uint32 hmap_violation_info; /* violation info */ 209 uint32 PAD[1]; 210 } pcie_hmapviolation_t; 211 212 #if !defined(DONGLEBUILD) || defined(BCMSTANDALONE_TEST) || \ 213 defined(ATE_BUILD) || defined(BCMDVFS) 214 /* SB side: PCIE core and host control registers */ 215 typedef volatile struct sbpcieregs { 216 uint32 control; /* host mode only */ 217 uint32 iocstatus; /* PCIE2: iostatus */ 218 uint32 PAD[1]; 219 uint32 biststatus; /* bist Status: 0x00C */ 220 uint32 gpiosel; /* PCIE gpio sel: 0x010 */ 221 uint32 gpioouten; /* PCIE gpio outen: 0x14 */ 222 uint32 gpioout; /* PCIE gpio out: 0x18 */ 223 uint32 PAD; 224 uint32 intstatus; /* Interrupt status: 0x20 */ 225 uint32 intmask; /* Interrupt mask: 0x24 */ 226 uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */ 227 uint32 obffcontrol; /* PCIE2: 0x2C */ 228 uint32 obffintstatus; /* PCIE2: 0x30 */ 229 uint32 obffdatastatus; /* PCIE2: 0x34 */ 230 uint32 PAD[1]; 231 uint32 ctoctrl; /* PCIE2: 0x3C */ 232 uint32 errlog; /* PCIE2: 0x40 */ 233 uint32 errlogaddr; /* PCIE2: 0x44 */ 234 uint32 mailboxint; /* PCIE2: 0x48 */ 235 uint32 mailboxintmsk; /* PCIE2: 0x4c */ 236 uint32 ltrspacing; /* PCIE2: 0x50 */ 237 uint32 ltrhysteresiscnt; /* PCIE2: 0x54 */ 238 uint32 msivectorassign; /* PCIE2: 0x58 */ 239 uint32 intmask2; /* PCIE2: 0x5C */ 240 uint32 PAD[40]; 241 uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */ 242 uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */ 243 uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */ 244 uint32 sbtopcie0upper; /* sb to pcie translation 0: 0x10C */ 245 uint32 sbtopcie1upper; /* sb to pcie translation 1: 0x110 */ 246 uint32 PAD[3]; 247 248 /* pcie core supports in direct access to config space */ 249 uint32 configaddr; /* pcie config space access: Address field: 0x120 */ 250 uint32 configdata; /* pcie config space access: Data field: 0x124 */ 251 union { 252 struct { 253 /* mdio access to serdes */ 254 uint32 mdiocontrol; /* controls the mdio access: 0x128 */ 255 uint32 mdiodata; /* Data to the mdio access: 0x12c */ 256 /* pcie protocol phy/dllp/tlp register indirect access mechanism */ 257 uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */ 258 uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */ 259 uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */ 260 uint32 PAD[177]; /* last 0x3FC */ 261 /* 0x400 - 0x7FF, PCIE Cfg Space, note: not used anymore in PcieGen2 */ 262 uint32 pciecfg[4][64]; 263 } pcie1; 264 struct { 265 /* mdio access to serdes */ 266 uint32 mdiocontrol; /* controls the mdio access: 0x128 */ 267 uint32 mdiowrdata; /* write data to mdio 0x12C */ 268 uint32 mdiorddata; /* read data to mdio 0x130 */ 269 uint32 PAD[3]; /* 0x134-0x138-0x13c */ 270 /* door bell registers available from gen2 rev5 onwards */ 271 pcie_doorbell_t dbls[PCIEDEV_MAX_DMAS]; /* 0x140 - 0x17F */ 272 uint32 dataintf; /* 0x180 */ 273 uint32 PAD[1]; /* 0x184 */ 274 uint32 d2h_intrlazy_0; /* 0x188 */ 275 uint32 h2d_intrlazy_0; /* 0x18c */ 276 uint32 h2d_intstat_0; /* 0x190 */ 277 uint32 h2d_intmask_0; /* 0x194 */ 278 uint32 d2h_intstat_0; /* 0x198 */ 279 uint32 d2h_intmask_0; /* 0x19c */ 280 uint32 ltr_state; /* 0x1A0 */ 281 uint32 pwr_int_status; /* 0x1A4 */ 282 uint32 pwr_int_mask; /* 0x1A8 */ 283 uint32 pme_source; /* 0x1AC */ 284 uint32 err_hdr_logreg1; /* 0x1B0 */ 285 uint32 err_hdr_logreg2; /* 0x1B4 */ 286 uint32 err_hdr_logreg3; /* 0x1B8 */ 287 uint32 err_hdr_logreg4; /* 0x1BC */ 288 uint32 err_code_logreg; /* 0x1C0 */ 289 uint32 axi_dbg_ctl; /* 0x1C4 */ 290 uint32 axi_dbg_data0; /* 0x1C8 */ 291 uint32 axi_dbg_data1; /* 0x1CC */ 292 uint32 PAD[4]; /* 0x1D0 - 0x1DF */ 293 uint32 clk_ctl_st; /* 0x1E0 */ 294 uint32 PAD[1]; /* 0x1E4 */ 295 uint32 powerctl; /* 0x1E8 */ 296 uint32 powerctl2; /* 0x1EC */ 297 uint32 PAD[4]; /* 0x1F0 - 0x1FF */ 298 pcie_devdmaregs_t h2d0_dmaregs; /* 0x200 - 0x23c */ 299 pcie_devdmaregs_t d2h0_dmaregs; /* 0x240 - 0x27c */ 300 pcie_devdmaregs_t h2d1_dmaregs; /* 0x280 - 0x2bc */ 301 pcie_devdmaregs_t d2h1_dmaregs; /* 0x2c0 - 0x2fc */ 302 pcie_devdmaregs_t h2d2_dmaregs; /* 0x300 - 0x33c */ 303 pcie_devdmaregs_t d2h2_dmaregs; /* 0x340 - 0x37c */ 304 pcie_devdmaregs_t h2d3_dmaregs; /* 0x380 - 0x3bc */ 305 pcie_devdmaregs_t d2h3_dmaregs; /* 0x3c0 - 0x3fc */ 306 uint32 d2h_intrlazy_1; /* 0x400 */ 307 uint32 h2d_intrlazy_1; /* 0x404 */ 308 uint32 h2d_intstat_1; /* 0x408 */ 309 uint32 h2d_intmask_1; /* 0x40c */ 310 uint32 d2h_intstat_1; /* 0x410 */ 311 uint32 d2h_intmask_1; /* 0x414 */ 312 uint32 PAD[2]; /* 0x418 - 0x41C */ 313 uint32 d2h_intrlazy_2; /* 0x420 */ 314 uint32 h2d_intrlazy_2; /* 0x424 */ 315 uint32 h2d_intstat_2; /* 0x428 */ 316 uint32 h2d_intmask_2; /* 0x42c */ 317 uint32 d2h_intstat_2; /* 0x430 */ 318 uint32 d2h_intmask_2; /* 0x434 */ 319 uint32 PAD[10]; /* 0x438 - 0x45F */ 320 uint32 ifrm_ctrlst; /* 0x460 */ 321 uint32 PAD[1]; /* 0x464 */ 322 pcie_ifrm_array_t ifrm_msk_arr; /* 0x468 - 0x46F */ 323 pcie_ifrm_array_t ifrm_tid_arr[IFRM_FR_DEV_VALID]; 324 /* 0x470 - 0x47F */ 325 pcie_ifrm_vector_t ifrm_vec[IFRM_FR_DEV_MAX]; 326 /* 0x480 - 0x4FF */ 327 pcie_ifrm_intr_t ifrm_intr[IFRM_FR_DEV_MAX]; 328 /* 0x500 - 0x53F */ 329 /* HMAP regs for PCIE corerev >= 24 [0x540 - 0x5DF] */ 330 pcie_hmapwindow_t hmapwindow[HMAP_MAX_WINDOWS]; /* 0x540 - 0x5BF */ 331 pcie_hmapviolation_t hmapviolation; /* 0x5C0 - 0x5CF */ 332 uint32 hmap_window_config; /* 0x5D0 */ 333 uint32 PAD[3]; /* 0x5D4 - 0x5DF */ 334 uint32 idma_hwa_status; /* 0x5E0 */ 335 uint32 PAD[7]; /* 0x5E4 - 0x5FF */ 336 uint32 PAD[2][64]; /* 0x600 - 0x7FF */ 337 } pcie2; 338 } u; 339 uint16 sprom[64]; /* SPROM shadow Area : 0x800 - 0x880 */ 340 uint32 PAD[96]; /* 0x880 - 0x9FF */ 341 /* direct memory access (pcie2 rev19 and after) : 0xA00 - 0xAFF */ 342 union { 343 /* corerev < 64 */ 344 struct { 345 uint32 dar_ctrl; /* 0xA00 */ 346 uint32 PAD[7]; /* 0xA04-0xA1F */ 347 uint32 intstatus; /* 0xA20 */ 348 uint32 PAD[1]; /* 0xA24 */ 349 uint32 h2d_db_0_0; /* 0xA28 */ 350 uint32 h2d_db_0_1; /* 0xA2C */ 351 uint32 h2d_db_1_0; /* 0xA30 */ 352 uint32 h2d_db_1_1; /* 0xA34 */ 353 uint32 h2d_db_2_0; /* 0xA38 */ 354 uint32 h2d_db_2_1; /* 0xA3C */ 355 uint32 errlog; /* 0xA40 */ 356 uint32 erraddr; /* 0xA44 */ 357 uint32 mbox_int; /* 0xA48 */ 358 uint32 fis_ctrl; /* 0xA4C */ 359 uint32 PAD[36]; /* 0xA50 - 0xADC */ 360 uint32 clk_ctl_st; /* 0xAE0 */ 361 uint32 PAD[1]; /* 0xAE4 */ 362 uint32 powerctl; /* 0xAE8 */ 363 uint32 PAD[5]; /* 0xAEC-0xAFF */ 364 } dar; 365 /* corerev > = 64 */ 366 struct { 367 uint32 dar_ctrl; /* 0xA00 */ 368 uint32 dar_cap; /* 0xA04 */ 369 uint32 clk_ctl_st; /* 0xA08 */ 370 uint32 powerctl; /* 0xA0C */ 371 uint32 intstatus; /* 0xA10 */ 372 uint32 PAD[3]; /* 0xA14-0xA1F */ 373 uint32 h2d_db_0_0; /* 0xA20 */ 374 uint32 h2d_db_0_1; /* 0xA24 */ 375 uint32 h2d_db_1_0; /* 0xA28 */ 376 uint32 h2d_db_1_1; /* 0xA2C */ 377 uint32 h2d_db_2_0; /* 0xA30 */ 378 uint32 h2d_db_2_1; /* 0xA34 */ 379 uint32 h2d_db_3_0; /* 0xA38 */ 380 uint32 h2d_db_3_1; /* 0xA3C */ 381 uint32 h2d_db_4_0; /* 0xA40 */ 382 uint32 h2d_db_4_1; /* 0xA44 */ 383 uint32 h2d_db_5_0; /* 0xA48 */ 384 uint32 h2d_db_5_1; /* 0xA4C */ 385 uint32 h2d_db_6_0; /* 0xA50 */ 386 uint32 h2d_db_6_1; /* 0xA54 */ 387 uint32 h2d_db_7_0; /* 0xA58 */ 388 uint32 h2d_db_7_1; /* 0xA5C */ 389 uint32 errlog; /* 0xA60 */ 390 uint32 erraddr; /* 0xA64 */ 391 uint32 mbox_int; /* 0xA68 */ 392 uint32 fis_ctrl; /* 0xA6C */ 393 uint32 PAD[36]; /* 0xA70-0xAFF */ 394 } dar_64; 395 } u1; 396 uint32 PAD[64]; /* 0xB00-0xBFF */ 397 /* Function Control/Status Registers for corerev >= 64 */ 398 /* 0xC00 - 0xCFF */ 399 struct { 400 uint32 control; /* 0xC00 */ 401 uint32 iostatus; /* 0xC04 */ 402 uint32 capability; /* 0xC08 */ 403 uint32 PAD[1]; /* 0xC0C */ 404 uint32 intstatus; /* 0xC10 */ 405 uint32 intmask; /* 0xC14 */ 406 uint32 pwr_intstatus; /* 0xC18 */ 407 uint32 pwr_intmask; /* 0xC1C */ 408 uint32 msi_vector; /* 0xC20 */ 409 uint32 msi_intmask; /* 0xC24 */ 410 uint32 msi_intstatus; /* 0xC28 */ 411 uint32 msi_pend_cnt; /* 0xC2C */ 412 uint32 mbox_intstatus; /* 0xC30 */ 413 uint32 mbox_intmask; /* 0xC34 */ 414 uint32 ltr_state; /* 0xC38 */ 415 uint32 PAD[1]; /* 0xC3C */ 416 uint32 intr_vector; /* 0xC40 */ 417 uint32 intr_addrlow; /* 0xC44 */ 418 uint32 intr_addrhigh; /* 0xC48 */ 419 uint32 PAD[45]; /* 0xC4C-0xCFF */ 420 } ftn_ctrl; 421 } sbpcieregs_t; 422 #endif /* !defined(DONGLEBUILD) || defined(BCMSTANDALONE_TEST) || */ 423 /* defined(ATE_BUILD) defined(BCMDVFS) */ 424 425 #define PCIE_CFG_DA_OFFSET 0x400 /* direct access register offset for configuration space */ 426 427 /* 10th and 11th 4KB BAR0 windows */ 428 #define PCIE_TER_BAR0_WIN 0xc50 429 #define PCIE_TER_BAR0_WRAPPER 0xc54 430 431 /* PCI control */ 432 #define PCIE_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */ 433 #define PCIE_RST 0x02 /* Value driven out to pin */ 434 #define PCIE_SPERST 0x04 /* SurvivePeRst */ 435 #define PCIE_FORCECFGCLKON_ALP 0x08 436 #define PCIE_DISABLE_L1CLK_GATING 0x10 437 #define PCIE_DLYPERST 0x100 /* Delay PeRst to CoE Core */ 438 #define PCIE_DISSPROMLD 0x200 /* DisableSpromLoadOnPerst */ 439 #define PCIE_WakeModeL2 0x1000 /* Wake on L2 */ 440 #define PCIE_MULTIMSI_EN 0x2000 /* enable multi-vector MSI messages */ 441 #define PCIE_PipeIddqDisable0 0x8000 /* Disable assertion of pcie_pipe_iddq during L1.2 and L2 */ 442 #define PCIE_PipeIddqDisable1 0x10000 /* Disable assertion of pcie_pipe_iddq during L2 */ 443 #define PCIE_EN_MDIO_IN_PERST 0x20000 /* enable access to internal registers when PERST */ 444 #define PCIE_HWDisableL1EntryEnable 0x40000 /* set, Hw requests can do entry/exit from L1 ASPM */ 445 #define PCIE_MSI_B2B_EN 0x100000 /* enable back-to-back MSI messages */ 446 #define PCIE_MSI_FIFO_CLEAR 0x200000 /* reset MSI FIFO */ 447 #define PCIE_IDMA_MODE_EN(rev) (REV_GE_64(rev) ? 0x1 : 0x800000) /* implicit M2M DMA mode */ 448 #define PCIE_TL_CLK_DETCT 0x4000000 /* enable TL clk detection */ 449 #define PCIE_REQ_PEND_DIS_L1 0x1000000 /* prevents entering L1 on pending requests from host */ 450 #define PCIE_DIS_L23CLK_GATE 0x10000000 /* disable clk gating in L23(pcie_tl_clk) */ 451 452 /* Function control (corerev > 64) */ 453 #define PCIE_CPLCA_ENABLE 0x01 454 /* 1: send CPL with CA on BP error, 0: send CPLD with SC and data is FFFF */ 455 #define PCIE_DLY_PERST_TO_COE 0x02 456 /* when set, PERST is holding asserted until sprom-related register updates has completed */ 457 458 #define PCIE_CFGADDR 0x120 /* offsetof(configaddr) */ 459 #define PCIE_CFGDATA 0x124 /* offsetof(configdata) */ 460 #define PCIE_SWPME_FN0 0x10000 461 #define PCIE_SWPME_FN0_SHF 16 462 463 /* Interrupt status/mask */ 464 #define PCIE_INTA 0x01 /* PCIE INTA message is received */ 465 #define PCIE_INTB 0x02 /* PCIE INTB message is received */ 466 #define PCIE_INTFATAL 0x04 /* PCIE INTFATAL message is received */ 467 #define PCIE_INTNFATAL 0x08 /* PCIE INTNONFATAL message is received */ 468 #define PCIE_INTCORR 0x10 /* PCIE INTCORR message is received */ 469 #define PCIE_INTPME 0x20 /* PCIE INTPME message is received */ 470 #define PCIE_PERST 0x40 /* PCIE Reset Interrupt */ 471 472 #define PCIE_INT_MB_FN0_0 0x0100 /* PCIE to SB Mailbox int Fn0.0 is received */ 473 #define PCIE_INT_MB_FN0_1 0x0200 /* PCIE to SB Mailbox int Fn0.1 is received */ 474 #define PCIE_INT_MB_FN1_0 0x0400 /* PCIE to SB Mailbox int Fn1.0 is received */ 475 #define PCIE_INT_MB_FN1_1 0x0800 /* PCIE to SB Mailbox int Fn1.1 is received */ 476 #define PCIE_INT_MB_FN2_0 0x1000 /* PCIE to SB Mailbox int Fn2.0 is received */ 477 #define PCIE_INT_MB_FN2_1 0x2000 /* PCIE to SB Mailbox int Fn2.1 is received */ 478 #define PCIE_INT_MB_FN3_0 0x4000 /* PCIE to SB Mailbox int Fn3.0 is received */ 479 #define PCIE_INT_MB_FN3_1 0x8000 /* PCIE to SB Mailbox int Fn3.1 is received */ 480 481 /* PCIE MSI Vector Assignment register */ 482 #define MSIVEC_MB_0 (0x1 << 1) /* MSI Vector offset for mailbox0 is 2 */ 483 #define MSIVEC_MB_1 (0x1 << 2) /* MSI Vector offset for mailbox1 is 3 */ 484 #define MSIVEC_D2H0_DB0 (0x1 << 3) /* MSI Vector offset for interface0 door bell 0 is 4 */ 485 #define MSIVEC_D2H0_DB1 (0x1 << 4) /* MSI Vector offset for interface0 door bell 1 is 5 */ 486 487 /* PCIE MailboxInt/MailboxIntMask register */ 488 #define PCIE_MB_TOSB_FN0_0 0x0001 /* write to assert PCIEtoSB Mailbox interrupt */ 489 #define PCIE_MB_TOSB_FN0_1 0x0002 490 #define PCIE_MB_TOSB_FN1_0 0x0004 491 #define PCIE_MB_TOSB_FN1_1 0x0008 492 #define PCIE_MB_TOSB_FN2_0 0x0010 493 #define PCIE_MB_TOSB_FN2_1 0x0020 494 #define PCIE_MB_TOSB_FN3_0 0x0040 495 #define PCIE_MB_TOSB_FN3_1 0x0080 496 #define PCIE_MB_TOPCIE_FN0_0 0x0100 /* int status/mask for SBtoPCIE Mailbox interrupts */ 497 #define PCIE_MB_TOPCIE_FN0_1 0x0200 498 #define PCIE_MB_TOPCIE_FN1_0 0x0400 499 #define PCIE_MB_TOPCIE_FN1_1 0x0800 500 #define PCIE_MB_TOPCIE_FN2_0 0x1000 501 #define PCIE_MB_TOPCIE_FN2_1 0x2000 502 #define PCIE_MB_TOPCIE_FN3_0 0x4000 503 #define PCIE_MB_TOPCIE_FN3_1 0x8000 504 505 #define PCIE_MB_TOPCIE_DB0_D2H0(rev) (REV_GE_64(rev) ? 0x0001 : 0x010000) 506 #define PCIE_MB_TOPCIE_DB0_D2H1(rev) (REV_GE_64(rev) ? 0x0002 : 0x020000) 507 #define PCIE_MB_TOPCIE_DB1_D2H0(rev) (REV_GE_64(rev) ? 0x0004 : 0x040000) 508 #define PCIE_MB_TOPCIE_DB1_D2H1(rev) (REV_GE_64(rev) ? 0x0008 : 0x080000) 509 #define PCIE_MB_TOPCIE_DB2_D2H0(rev) (REV_GE_64(rev) ? 0x0010 : 0x100000) 510 #define PCIE_MB_TOPCIE_DB2_D2H1(rev) (REV_GE_64(rev) ? 0x0020 : 0x200000) 511 #define PCIE_MB_TOPCIE_DB3_D2H0(rev) (REV_GE_64(rev) ? 0x0040 : 0x400000) 512 #define PCIE_MB_TOPCIE_DB3_D2H1(rev) (REV_GE_64(rev) ? 0x0080 : 0x800000) 513 #define PCIE_MB_TOPCIE_DB4_D2H0(rev) (REV_GE_64(rev) ? 0x0100 : 0x0) 514 #define PCIE_MB_TOPCIE_DB4_D2H1(rev) (REV_GE_64(rev) ? 0x0200 : 0x0) 515 #define PCIE_MB_TOPCIE_DB5_D2H0(rev) (REV_GE_64(rev) ? 0x0400 : 0x0) 516 #define PCIE_MB_TOPCIE_DB5_D2H1(rev) (REV_GE_64(rev) ? 0x0800 : 0x0) 517 #define PCIE_MB_TOPCIE_DB6_D2H0(rev) (REV_GE_64(rev) ? 0x1000 : 0x0) 518 #define PCIE_MB_TOPCIE_DB6_D2H1(rev) (REV_GE_64(rev) ? 0x2000 : 0x0) 519 #define PCIE_MB_TOPCIE_DB7_D2H0(rev) (REV_GE_64(rev) ? 0x4000 : 0x0) 520 #define PCIE_MB_TOPCIE_DB7_D2H1(rev) (REV_GE_64(rev) ? 0x8000 : 0x0) 521 522 #define PCIE_MB_D2H_MB_MASK(rev) \ 523 (PCIE_MB_TOPCIE_DB0_D2H0(rev) | PCIE_MB_TOPCIE_DB0_D2H1(rev) | \ 524 PCIE_MB_TOPCIE_DB1_D2H0(rev) | PCIE_MB_TOPCIE_DB1_D2H1(rev) | \ 525 PCIE_MB_TOPCIE_DB2_D2H0(rev) | PCIE_MB_TOPCIE_DB2_D2H1(rev) | \ 526 PCIE_MB_TOPCIE_DB3_D2H0(rev) | PCIE_MB_TOPCIE_DB3_D2H1(rev) | \ 527 PCIE_MB_TOPCIE_DB4_D2H0(rev) | PCIE_MB_TOPCIE_DB4_D2H1(rev) | \ 528 PCIE_MB_TOPCIE_DB5_D2H0(rev) | PCIE_MB_TOPCIE_DB5_D2H1(rev) | \ 529 PCIE_MB_TOPCIE_DB6_D2H0(rev) | PCIE_MB_TOPCIE_DB6_D2H1(rev) | \ 530 PCIE_MB_TOPCIE_DB7_D2H0(rev) | PCIE_MB_TOPCIE_DB7_D2H1(rev)) 531 532 #define SBTOPCIE0_BASE 0x08000000 533 #define SBTOPCIE1_BASE 0x0c000000 534 535 /* Protection Control register */ 536 #define PROTECT_CFG (1 << 0) 537 #define PROTECT_DMABADDR (1 << 1) 538 539 #define PROTECT_FN_CFG_WRITE (1 << 0) 540 #define PROTECT_FN_CFG_READ (1 << 1) 541 #define PROTECT_FN_ENUM_WRITE (1 << 2) 542 #define PROTECT_FN_ENUM_READ (1 << 3) 543 #define PROTECT_FN_DMABADDR (1 << 4) 544 545 /* On chips with CCI-400, the small pcie 128 MB region base has shifted */ 546 #define CCI400_SBTOPCIE0_BASE 0x20000000 547 #define CCI400_SBTOPCIE1_BASE 0x24000000 548 549 /* SB to PCIE translation masks */ 550 #define SBTOPCIE0_MASK 0xfc000000 551 #define SBTOPCIE1_MASK 0xfc000000 552 #define SBTOPCIE2_MASK 0xc0000000 553 554 /* Access type bits (0:1) */ 555 #define SBTOPCIE_MEM 0 556 #define SBTOPCIE_IO 1 557 #define SBTOPCIE_CFG0 2 558 #define SBTOPCIE_CFG1 3 559 560 /* Prefetch enable bit 2 */ 561 #define SBTOPCIE_PF 4 562 563 /* Write Burst enable for memory write bit 3 */ 564 #define SBTOPCIE_WR_BURST 8 565 566 /* config access */ 567 #define CONFIGADDR_FUNC_MASK 0x7000 568 #define CONFIGADDR_FUNC_SHF 12 569 #define CONFIGADDR_REG_MASK 0x0FFF 570 #define CONFIGADDR_REG_SHF 0 571 572 #define PCIE_CONFIG_INDADDR(f, r) ((((f) & CONFIGADDR_FUNC_MASK) << CONFIGADDR_FUNC_SHF) | \ 573 (((r) & CONFIGADDR_REG_MASK) << CONFIGADDR_REG_SHF)) 574 575 /* PCIE protocol regs Indirect Address */ 576 #define PCIEADDR_PROT_MASK 0x300 577 #define PCIEADDR_PROT_SHF 8 578 #define PCIEADDR_PL_TLP 0 579 #define PCIEADDR_PL_DLLP 1 580 #define PCIEADDR_PL_PLP 2 581 582 #define PCIE_CORE_REG_CONTROL 0x00u /* Control */ 583 #define PCIE_CORE_REG_IOSTATUS 0x04u /* IO status */ 584 #define PCIE_CORE_REG_BITSTATUS 0x0Cu /* bitstatus */ 585 #define PCIE_CORE_REG_GPIO_SEL 0x10u /* gpio sel */ 586 #define PCIE_CORE_REG_GPIO_OUT_EN 0x14u /* gpio out en */ 587 #define PCIE_CORE_REG_INT_STATUS 0x20u /* int status */ 588 #define PCIE_CORE_REG_INT_MASK 0x24u /* int mask */ 589 #define PCIE_CORE_REG_SB_PCIE_MB 0x28u /* sbpcie mb */ 590 #define PCIE_CORE_REG_ERRLOG 0x40u /* errlog */ 591 #define PCIE_CORE_REG_ERR_ADDR 0x44u /* errlog addr */ 592 #define PCIE_CORE_REG_MB_INTR 0x48u /* MB intr */ 593 #define PCIE_CORE_REG_SB_PCIE_0 0x100u /* sbpcie0 map */ 594 #define PCIE_CORE_REG_SB_PCIE_1 0x104u /* sbpcie1 map */ 595 #define PCIE_CORE_REG_SB_PCIE_2 0x108u /* sbpcie2 map */ 596 597 /* PCIE Config registers */ 598 #define PCIE_CFG_DEV_STS_CTRL_2 0x0d4u /* "dev_sts_control_2 */ 599 #define PCIE_CFG_ADV_ERR_CAP 0x100u /* adv_err_cap */ 600 #define PCIE_CFG_UC_ERR_STS 0x104u /* uc_err_status */ 601 #define PCIE_CFG_UC_ERR_MASK 0x108u /* ucorr_err_mask */ 602 #define PCIE_CFG_UNCOR_ERR_SERV 0x10cu /* ucorr_err_sevr */ 603 #define PCIE_CFG_CORR_ERR_STS 0x110u /* corr_err_status */ 604 #define PCIE_CFG_CORR_ERR_MASK 0x114u /* corr_err_mask */ 605 #define PCIE_CFG_ADV_ERR_CTRL 0x118u /* adv_err_cap_control */ 606 #define PCIE_CFG_HDR_LOG1 0x11Cu /* header_log1 */ 607 #define PCIE_CFG_HDR_LOG2 0x120u /* header_log2 */ 608 #define PCIE_CFG_HDR_LOG3 0x124u /* header_log3 */ 609 #define PCIE_CFG_HDR_LOG4 0x128u /* header_log4 */ 610 #define PCIE_CFG_PML1_SUB_CAP_ID 0x240u /* PML1sub_capID */ 611 #define PCIE_CFG_PML1_SUB_CAP_REG 0x244u /* PML1_sub_Cap_reg */ 612 #define PCIE_CFG_PML1_SUB_CTRL1 0x248u /* PML1_sub_control1 */ 613 #define PCIE_CFG_PML1_SUB_CTRL3 0x24Cu /* PML1_sub_control2 */ 614 #define PCIE_CFG_TL_CTRL_5 0x814u /* tl_control_5 */ 615 #define PCIE_CFG_PHY_ERR_ATT_VEC 0x1820u /* phy_err_attn_vec */ 616 #define PCIE_CFG_PHY_ERR_ATT_MASK 0x1824u /* phy_err_attn_mask */ 617 618 /* PCIE protocol PHY diagnostic registers */ 619 #define PCIE_PLP_MODEREG 0x200u /* Mode */ 620 #define PCIE_PLP_STATUSREG 0x204u /* Status */ 621 #define PCIE_PLP_LTSSMCTRLREG 0x208u /* LTSSM control */ 622 #define PCIE_PLP_LTLINKNUMREG 0x20cu /* Link Training Link number */ 623 #define PCIE_PLP_LTLANENUMREG 0x210u /* Link Training Lane number */ 624 #define PCIE_PLP_LTNFTSREG 0x214u /* Link Training N_FTS */ 625 #define PCIE_PLP_ATTNREG 0x218u /* Attention */ 626 #define PCIE_PLP_ATTNMASKREG 0x21Cu /* Attention Mask */ 627 #define PCIE_PLP_RXERRCTR 0x220u /* Rx Error */ 628 #define PCIE_PLP_RXFRMERRCTR 0x224u /* Rx Framing Error */ 629 #define PCIE_PLP_RXERRTHRESHREG 0x228u /* Rx Error threshold */ 630 #define PCIE_PLP_TESTCTRLREG 0x22Cu /* Test Control reg */ 631 #define PCIE_PLP_SERDESCTRLOVRDREG 0x230u /* SERDES Control Override */ 632 #define PCIE_PLP_TIMINGOVRDREG 0x234u /* Timing param override */ 633 #define PCIE_PLP_RXTXSMDIAGREG 0x238u /* RXTX State Machine Diag */ 634 #define PCIE_PLP_LTSSMDIAGREG 0x23Cu /* LTSSM State Machine Diag */ 635 636 /* PCIE protocol DLLP diagnostic registers */ 637 #define PCIE_DLLP_LCREG 0x100u /* Link Control */ 638 #define PCIE_DLLP_LSREG 0x104u /* Link Status */ 639 #define PCIE_DLLP_LAREG 0x108u /* Link Attention */ 640 #define PCIE_DLLP_LAMASKREG 0x10Cu /* Link Attention Mask */ 641 #define PCIE_DLLP_NEXTTXSEQNUMREG 0x110u /* Next Tx Seq Num */ 642 #define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114u /* Acked Tx Seq Num */ 643 #define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118u /* Purged Tx Seq Num */ 644 #define PCIE_DLLP_RXSEQNUMREG 0x11Cu /* Rx Sequence Number */ 645 #define PCIE_DLLP_LRREG 0x120u /* Link Replay */ 646 #define PCIE_DLLP_LACKTOREG 0x124u /* Link Ack Timeout */ 647 #define PCIE_DLLP_PMTHRESHREG 0x128u /* Power Management Threshold */ 648 #define PCIE_DLLP_RTRYWPREG 0x12Cu /* Retry buffer write ptr */ 649 #define PCIE_DLLP_RTRYRPREG 0x130u /* Retry buffer Read ptr */ 650 #define PCIE_DLLP_RTRYPPREG 0x134u /* Retry buffer Purged ptr */ 651 #define PCIE_DLLP_RTRRWREG 0x138u /* Retry buffer Read/Write */ 652 #define PCIE_DLLP_ECTHRESHREG 0x13Cu /* Error Count Threshold */ 653 #define PCIE_DLLP_TLPERRCTRREG 0x140u /* TLP Error Counter */ 654 #define PCIE_DLLP_ERRCTRREG 0x144u /* Error Counter */ 655 #define PCIE_DLLP_NAKRXCTRREG 0x148u /* NAK Received Counter */ 656 #define PCIE_DLLP_TESTREG 0x14Cu /* Test */ 657 #define PCIE_DLLP_PKTBIST 0x150u /* Packet BIST */ 658 #define PCIE_DLLP_PCIE11 0x154u /* DLLP PCIE 1.1 reg */ 659 660 #define PCIE_DLLP_LSREG_LINKUP (1u << 16u) 661 662 /* PCIE protocol TLP diagnostic registers */ 663 #define PCIE_TLP_CONFIGREG 0x000u /* Configuration */ 664 #define PCIE_TLP_WORKAROUNDSREG 0x004u /* TLP Workarounds */ 665 #define PCIE_TLP_WRDMAUPPER 0x010u /* Write DMA Upper Address */ 666 #define PCIE_TLP_WRDMALOWER 0x014u /* Write DMA Lower Address */ 667 #define PCIE_TLP_WRDMAREQ_LBEREG 0x018u /* Write DMA Len/ByteEn Req */ 668 #define PCIE_TLP_RDDMAUPPER 0x01Cu /* Read DMA Upper Address */ 669 #define PCIE_TLP_RDDMALOWER 0x020u /* Read DMA Lower Address */ 670 #define PCIE_TLP_RDDMALENREG 0x024u /* Read DMA Len Req */ 671 #define PCIE_TLP_MSIDMAUPPER 0x028u /* MSI DMA Upper Address */ 672 #define PCIE_TLP_MSIDMALOWER 0x02Cu /* MSI DMA Lower Address */ 673 #define PCIE_TLP_MSIDMALENREG 0x030u /* MSI DMA Len Req */ 674 #define PCIE_TLP_SLVREQLENREG 0x034u /* Slave Request Len */ 675 #define PCIE_TLP_FCINPUTSREQ 0x038u /* Flow Control Inputs */ 676 #define PCIE_TLP_TXSMGRSREQ 0x03Cu /* Tx StateMachine and Gated Req */ 677 #define PCIE_TLP_ADRACKCNTARBLEN 0x040u /* Address Ack XferCnt and ARB Len */ 678 #define PCIE_TLP_DMACPLHDR0 0x044u /* DMA Completion Hdr 0 */ 679 #define PCIE_TLP_DMACPLHDR1 0x048u /* DMA Completion Hdr 1 */ 680 #define PCIE_TLP_DMACPLHDR2 0x04Cu /* DMA Completion Hdr 2 */ 681 #define PCIE_TLP_DMACPLMISC0 0x050u /* DMA Completion Misc0 */ 682 #define PCIE_TLP_DMACPLMISC1 0x054u /* DMA Completion Misc1 */ 683 #define PCIE_TLP_DMACPLMISC2 0x058u /* DMA Completion Misc2 */ 684 #define PCIE_TLP_SPTCTRLLEN 0x05Cu /* Split Controller Req len */ 685 #define PCIE_TLP_SPTCTRLMSIC0 0x060u /* Split Controller Misc 0 */ 686 #define PCIE_TLP_SPTCTRLMSIC1 0x064u /* Split Controller Misc 1 */ 687 #define PCIE_TLP_BUSDEVFUNC 0x068u /* Bus/Device/Func */ 688 #define PCIE_TLP_RESETCTR 0x06Cu /* Reset Counter */ 689 #define PCIE_TLP_RTRYBUF 0x070u /* Retry Buffer value */ 690 #define PCIE_TLP_TGTDEBUG1 0x074u /* Target Debug Reg1 */ 691 #define PCIE_TLP_TGTDEBUG2 0x078u /* Target Debug Reg2 */ 692 #define PCIE_TLP_TGTDEBUG3 0x07Cu /* Target Debug Reg3 */ 693 #define PCIE_TLP_TGTDEBUG4 0x080u /* Target Debug Reg4 */ 694 695 /* PCIE2 MDIO register offsets */ 696 #define PCIE2_MDIO_CONTROL 0x128 697 #define PCIE2_MDIO_WR_DATA 0x12C 698 #define PCIE2_MDIO_RD_DATA 0x130 699 700 /* MDIO control */ 701 #define MDIOCTL_DIVISOR_MASK 0x7fu /* clock to be used on MDIO */ 702 #define MDIOCTL_DIVISOR_VAL 0x2u 703 #define MDIOCTL_PREAM_EN 0x80u /* Enable preamble sequnce */ 704 #define MDIOCTL_ACCESS_DONE 0x100u /* Tranaction complete */ 705 706 /* MDIO Data */ 707 #define MDIODATA_MASK 0x0000ffff /* data 2 bytes */ 708 #define MDIODATA_TA 0x00020000 /* Turnaround */ 709 #define MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */ 710 #define MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */ 711 #define MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */ 712 #define MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */ 713 #define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */ 714 #define MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */ 715 #define MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */ 716 #define MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */ 717 #define MDIODATA_WRITE 0x10000000 /* write Transaction */ 718 #define MDIODATA_READ 0x20000000 /* Read Transaction */ 719 #define MDIODATA_START 0x40000000 /* start of Transaction */ 720 721 #define MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */ 722 #define MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */ 723 724 /* MDIO control/wrData/rdData register defines for PCIE Gen 2 */ 725 #define MDIOCTL2_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ 726 #define MDIOCTL2_DIVISOR_VAL 0x2 727 #define MDIOCTL2_REGADDR_SHF 8 /* Regaddr shift */ 728 #define MDIOCTL2_REGADDR_MASK 0x00FFFF00 /* Regaddr Mask */ 729 #define MDIOCTL2_DEVADDR_SHF 24 /* Physmedia devaddr shift */ 730 #define MDIOCTL2_DEVADDR_MASK 0x0f000000 /* Physmedia devaddr Mask */ 731 #define MDIOCTL2_SLAVE_BYPASS 0x10000000 /* IP slave bypass */ 732 #define MDIOCTL2_READ 0x20000000 /* IP slave bypass */ 733 734 #define MDIODATA2_DONE 0x80000000u /* rd/wr transaction done */ 735 #define MDIODATA2_MASK 0x7FFFFFFF /* rd/wr transaction data */ 736 #define MDIODATA2_DEVADDR_SHF 4 /* Physmedia devaddr shift */ 737 738 /* MDIO devices (SERDES modules) 739 * unlike old pcie cores (rev < 10), rev10 pcie serde organizes registers into a few blocks. 740 * two layers mapping (blockidx, register offset) is required 741 */ 742 #define MDIO_DEV_IEEE0 0x000 743 #define MDIO_DEV_IEEE1 0x001 744 #define MDIO_DEV_BLK0 0x800 745 #define MDIO_DEV_BLK1 0x801 746 #define MDIO_DEV_BLK2 0x802 747 #define MDIO_DEV_BLK3 0x803 748 #define MDIO_DEV_BLK4 0x804 749 #define MDIO_DEV_TXPLL 0x808 /* TXPLL register block idx */ 750 #define MDIO_DEV_TXCTRL0 0x820 751 #define MDIO_DEV_SERDESID 0x831 752 #define MDIO_DEV_RXCTRL0 0x840 753 754 /* XgxsBlk1_A Register Offsets */ 755 #define BLK1_PWR_MGMT0 0x16 756 #define BLK1_PWR_MGMT1 0x17 757 #define BLK1_PWR_MGMT2 0x18 758 #define BLK1_PWR_MGMT3 0x19 759 #define BLK1_PWR_MGMT4 0x1A 760 761 /* serdes regs (rev < 10) */ 762 #define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */ 763 #define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */ 764 #define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */ 765 /* SERDES RX registers */ 766 #define SERDES_RX_CTRL 1 /* Rx cntrl */ 767 #define SERDES_RX_TIMER1 2 /* Rx Timer1 */ 768 #define SERDES_RX_CDR 6 /* CDR */ 769 #define SERDES_RX_CDRBW 7 /* CDR BW */ 770 771 /* SERDES RX control register */ 772 #define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ 773 #define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */ 774 775 /* SERDES PLL registers */ 776 #define SERDES_PLL_CTRL 1 /* PLL control reg */ 777 #define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ 778 779 /* Power management threshold */ 780 #define PCIE_L0THRESHOLDTIME_MASK 0xFF00u /* bits 0 - 7 */ 781 #define PCIE_L1THRESHOLDTIME_MASK 0xFF00u /* bits 8 - 15 */ 782 #define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */ 783 #define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */ 784 #define PCIE_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */ 785 786 /* SPROM offsets */ 787 #define SRSH_ASPM_OFFSET 4 /* word 4 */ 788 #define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */ 789 #define SRSH_ASPM_L1_ENB 0x10 /* bit 4 */ 790 #define SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */ 791 #define SRSH_PCIE_MISC_CONFIG 5 /* word 5 */ 792 #define SRSH_L23READY_EXIT_NOPERST 0x8000u /* bit 15 */ 793 #define SRSH_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */ 794 #define SRSH_CLKREQ_OFFSET_REV8 52 /* word 52 for srom rev 8 */ 795 #define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */ 796 #define SRSH_BD_OFFSET 6 /* word 6 */ 797 #define SRSH_AUTOINIT_OFFSET 18 /* auto initialization enable */ 798 799 /* PCI Capability ID's 800 * Reference include/linux/pci_regs.h 801 * #define PCI_CAP_LIST_ID 0 // Capability ID 802 * #define PCI_CAP_ID_PM 0x01 // Power Management 803 * #define PCI_CAP_ID_AGP 0x02 // Accelerated Graphics Port 804 * #define PCI_CAP_ID_VPD 0x03 // Vital Product Data 805 * #define PCI_CAP_ID_SLOTID 0x04 // Slot Identification 806 * #define PCI_CAP_ID_MSI 0x05 // Message Signalled Interrupts 807 * #define PCI_CAP_ID_CHSWP 0x06 // CompactPCI HotSwap 808 * #define PCI_CAP_ID_PCIX 0x07 // PCI-X 809 * #define PCI_CAP_ID_HT 0x08 // HyperTransport 810 * #define PCI_CAP_ID_VNDR 0x09 // Vendor-Specific 811 * #define PCI_CAP_ID_DBG 0x0A // Debug port 812 * #define PCI_CAP_ID_CCRC 0x0B // CompactPCI Central Resource Control 813 * #define PCI_CAP_ID_SHPC 0x0C // PCI Standard Hot-Plug Controller 814 * #define PCI_CAP_ID_SSVID 0x0D // Bridge subsystem vendor/device ID 815 * #define PCI_CAP_ID_AGP3 0x0E // AGP Target PCI-PCI bridge 816 * #define PCI_CAP_ID_SECDEV 0x0F // Secure Device 817 * #define PCI_CAP_ID_MSIX 0x11 // MSI-X 818 * #define PCI_CAP_ID_SATA 0x12 // SATA Data/Index Conf. 819 * #define PCI_CAP_ID_AF 0x13 // PCI Advanced Features 820 * #define PCI_CAP_ID_EA 0x14 // PCI Enhanced Allocation 821 * #define PCI_CAP_ID_MAX PCI_CAP_ID_EA 822 */ 823 824 #define PCIE_CAP_ID_EXP 0x10 // PCI Express 825 826 /* PCIe Capabilities Offsets 827 * Reference include/linux/pci_regs.h 828 * #define PCIE_CAP_FLAGS 2 // Capabilities register 829 * #define PCIE_CAP_DEVCAP 4 // Device capabilities 830 * #define PCIE_CAP_DEVCTL 8 // Device Control 831 * #define PCIE_CAP_DEVSTA 10 // Device Status 832 * #define PCIE_CAP_LNKCAP 12 // Link Capabilities 833 * #define PCIE_CAP_LNKCTL 16 // Link Control 834 * #define PCIE_CAP_LNKSTA 18 // Link Status 835 * #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 // v1 endpoints end here 836 * #define PCIE_CAP_SLTCAP 20 // Slot Capabilities 837 * #define PCIE_CAP_SLTCTL 24 // Slot Control 838 * #define PCIE_CAP_SLTSTA 26 // Slot Status 839 * #define PCIE_CAP_RTCTL 28 // Root Control 840 * #define PCIE_CAP_RTCAP 30 // Root Capabilities 841 * #define PCIE_CAP_RTSTA 32 // Root Status 842 */ 843 844 /* Linkcapability reg offset in PCIE Cap */ 845 #define PCIE_CAP_LINKCAP_OFFSET 12 /* linkcap offset in pcie cap */ 846 #define PCIE_CAP_LINKCAP_LNKSPEED_MASK 0xf /* Supported Link Speeds */ 847 #define PCIE_CAP_LINKCAP_GEN2 0x2 /* Value for GEN2 */ 848 849 /* Uc_Err reg offset in AER Cap */ 850 #define PCIE_EXTCAP_ID_ERR 0x01 /* Advanced Error Reporting */ 851 #define PCIE_EXTCAP_AER_UCERR_OFFSET 4 /* Uc_Err reg offset in AER Cap */ 852 #define PCIE_EXTCAP_ERR_HEADER_LOG_0 28 853 #define PCIE_EXTCAP_ERR_HEADER_LOG_1 32 854 #define PCIE_EXTCAP_ERR_HEADER_LOG_2 36 855 #define PCIE_EXTCAP_ERR_HEADER_LOG_3 40 856 857 /* L1SS reg offset in L1SS Ext Cap */ 858 #define PCIE_EXTCAP_ID_L1SS 0x1e /* PCI Express L1 PM Substates Capability */ 859 #define PCIE_EXTCAP_L1SS_CAP_OFFSET 4 /* L1SSCap reg offset in L1SS Cap */ 860 #define PCIE_EXTCAP_L1SS_CONTROL_OFFSET 8 /* L1SSControl reg offset in L1SS Cap */ 861 #define PCIE_EXTCAP_L1SS_CONTROL2_OFFSET 0xc /* L1SSControl reg offset in L1SS Cap */ 862 863 /* Linkcontrol reg offset in PCIE Cap */ 864 #define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */ 865 #define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */ 866 #define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */ 867 #define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */ 868 #define PCIE_LINKSPEED_MASK 0xF0000u /* bits 0 - 3 of high word */ 869 #define PCIE_LINKSPEED_SHIFT 16 /* PCIE_LINKSPEED_SHIFT */ 870 #define PCIE_LINK_STS_LINKSPEED_5Gbps (0x2 << PCIE_LINKSPEED_SHIFT) /* PCIE_LINKSPEED 5Gbps */ 871 872 /* Devcontrol reg offset in PCIE Cap */ 873 #define PCIE_CAP_DEVCTRL_OFFSET 8 /* devctrl offset in pcie cap */ 874 #define PCIE_CAP_DEVCTRL_MRRS_MASK 0x7000 /* Max read request size mask */ 875 #define PCIE_CAP_DEVCTRL_MRRS_SHIFT 12 /* Max read request size shift */ 876 #define PCIE_CAP_DEVCTRL_MRRS_128B 0 /* 128 Byte */ 877 #define PCIE_CAP_DEVCTRL_MRRS_256B 1 /* 256 Byte */ 878 #define PCIE_CAP_DEVCTRL_MRRS_512B 2 /* 512 Byte */ 879 #define PCIE_CAP_DEVCTRL_MRRS_1024B 3 /* 1024 Byte */ 880 #define PCIE_CAP_DEVCTRL_MPS_MASK 0x00e0 /* Max payload size mask */ 881 #define PCIE_CAP_DEVCTRL_MPS_SHIFT 5 /* Max payload size shift */ 882 #define PCIE_CAP_DEVCTRL_MPS_128B 0 /* 128 Byte */ 883 #define PCIE_CAP_DEVCTRL_MPS_256B 1 /* 256 Byte */ 884 #define PCIE_CAP_DEVCTRL_MPS_512B 2 /* 512 Byte */ 885 #define PCIE_CAP_DEVCTRL_MPS_1024B 3 /* 1024 Byte */ 886 887 #define PCIE_ASPM_CTRL_MASK 3 /* bit 0 and 1 */ 888 #define PCIE_ASPM_ENAB 3 /* ASPM L0s & L1 in linkctrl */ 889 #define PCIE_ASPM_L1_ENAB 2 /* ASPM L0s & L1 in linkctrl */ 890 #define PCIE_ASPM_L0s_ENAB 1 /* ASPM L0s & L1 in linkctrl */ 891 #define PCIE_ASPM_DISAB 0 /* ASPM L0s & L1 in linkctrl */ 892 893 #define PCIE_ASPM_L11_ENAB 8 /* ASPM L1.1 in PML1_sub_control2 */ 894 #define PCIE_ASPM_L12_ENAB 4 /* ASPM L1.2 in PML1_sub_control2 */ 895 896 #define PCIE_EXT_L1SS_MASK 0xf /* Bits [3:0] of L1SSControl 0x248 */ 897 #define PCIE_EXT_L1SS_ENAB 0xf /* Bits [3:0] of L1SSControl 0x248 */ 898 899 /* NumMsg and NumMsgEn in PCIE MSI Cap */ 900 #define MSICAP_NUM_MSG_SHF 17 901 #define MSICAP_NUM_MSG_MASK (0x7 << MSICAP_NUM_MSG_SHF) 902 #define MSICAP_NUM_MSG_EN_SHF 20 903 #define MSICAP_NUM_MSG_EN_MASK (0x7 << MSICAP_NUM_MSG_EN_SHF) 904 905 /* Devcontrol2 reg offset in PCIE Cap */ 906 #define PCIE_CAP_DEVCTRL2_OFFSET 0x28 /* devctrl2 offset in pcie cap */ 907 #define PCIE_CAP_DEVCTRL2_LTR_ENAB_MASK 0x400 /* Latency Tolerance Reporting Enable */ 908 #define PCIE_CAP_DEVCTRL2_OBFF_ENAB_SHIFT 13 /* Enable OBFF mechanism, select signaling method */ 909 #define PCIE_CAP_DEVCTRL2_OBFF_ENAB_MASK 0x6000 /* Enable OBFF mechanism, select signaling method */ 910 911 /* LTR registers in PCIE Cap */ 912 #define PCIE_LTR0_REG_OFFSET 0x844u /* ltr0_reg offset in pcie cap */ 913 #define PCIE_LTR1_REG_OFFSET 0x848u /* ltr1_reg offset in pcie cap */ 914 #define PCIE_LTR2_REG_OFFSET 0x84cu /* ltr2_reg offset in pcie cap */ 915 #define PCIE_LTR0_REG_DEFAULT_60 0x883c883cu /* active latency default to 60usec */ 916 #define PCIE_LTR0_REG_DEFAULT_150 0x88968896u /* active latency default to 150usec */ 917 #define PCIE_LTR1_REG_DEFAULT 0x88648864u /* idle latency default to 100usec */ 918 #define PCIE_LTR2_REG_DEFAULT 0x90039003u /* sleep latency default to 3msec */ 919 #define PCIE_LTR_LAT_VALUE_MASK 0x3FFu /* LTR Latency mask */ 920 #define PCIE_LTR_LAT_SCALE_SHIFT 10u /* LTR Scale shift */ 921 #define PCIE_LTR_LAT_SCALE_MASK 0x1C00u /* LTR Scale mask */ 922 #define PCIE_LTR_SNOOP_REQ_SHIFT 15u /* LTR SNOOP REQ shift */ 923 #define PCIE_LTR_SNOOP_REQ_MASK 0x8000u /* LTR SNOOP REQ mask */ 924 925 /* Status reg PCIE_PLP_STATUSREG */ 926 #define PCIE_PLP_POLARITYINV_STAT 0x10u 927 928 /* PCIE BRCM Vendor CAP REVID reg bits */ 929 #define BRCMCAP_PCIEREV_CT_MASK 0xF00u 930 #define BRCMCAP_PCIEREV_CT_SHIFT 8u 931 #define BRCMCAP_PCIEREV_REVID_MASK 0xFFu 932 #define BRCMCAP_PCIEREV_REVID_SHIFT 0 933 934 #define PCIE_REVREG_CT_PCIE1 0 935 #define PCIE_REVREG_CT_PCIE2 1 936 937 /* PCIE GEN2 specific defines */ 938 /* PCIE BRCM Vendor Cap offsets w.r.t to vendor cap ptr */ 939 #define PCIE2R0_BRCMCAP_REVID_OFFSET 4 940 #define PCIE2R0_BRCMCAP_BAR0_WIN0_WRAP_OFFSET 8 941 #define PCIE2R0_BRCMCAP_BAR0_WIN2_OFFSET 12 942 #define PCIE2R0_BRCMCAP_BAR0_WIN2_WRAP_OFFSET 16 943 #define PCIE2R0_BRCMCAP_BAR0_WIN_OFFSET 20 944 #define PCIE2R0_BRCMCAP_BAR1_WIN_OFFSET 24 945 #define PCIE2R0_BRCMCAP_SPROM_CTRL_OFFSET 28 946 #define PCIE2R0_BRCMCAP_BAR2_WIN_OFFSET 32 947 #define PCIE2R0_BRCMCAP_INTSTATUS_OFFSET 36 948 #define PCIE2R0_BRCMCAP_INTMASK_OFFSET 40 949 #define PCIE2R0_BRCMCAP_PCIE2SB_MB_OFFSET 44 950 #define PCIE2R0_BRCMCAP_BPADDR_OFFSET 48 951 #define PCIE2R0_BRCMCAP_BPDATA_OFFSET 52 952 #define PCIE2R0_BRCMCAP_CLKCTLSTS_OFFSET 56 953 954 /* 955 * definition of configuration space registers of PCIe gen2 956 */ 957 #define PCIECFGREG_STATUS_CMD 0x4 958 #define PCIECFGREG_PM_CSR 0x4C 959 #define PCIECFGREG_MSI_CAP 0x58 960 #define PCIECFGREG_MSI_ADDR_L 0x5C 961 #define PCIECFGREG_MSI_ADDR_H 0x60 962 #define PCIECFGREG_MSI_DATA 0x64 963 #define PCIECFGREG_SPROM_CTRL 0x88 964 #define PCIECFGREG_LINK_STATUS_CTRL 0xBCu 965 #define PCIECFGREG_LINK_STATUS_CTRL2 0xDCu 966 #define PCIECFGREG_DEV_STATUS_CTRL 0xB4u 967 #define PCIECFGGEN_DEV_STATUS_CTRL2 0xD4 968 #define PCIECFGREG_RBAR_CTRL 0x228 969 #define PCIECFGREG_PML1_SUB_CTRL1 0x248 970 #define PCIECFGREG_PML1_SUB_CTRL2 0x24C 971 #define PCIECFGREG_REG_BAR2_CONFIG 0x4E0 972 #define PCIECFGREG_REG_BAR3_CONFIG 0x4F4 973 #define PCIECFGREG_PDL_CTRL1 0x1004 974 #define PCIECFGREG_PDL_CTRL5 (0x1014u) 975 #define PCIECFGREG_PDL_IDDQ 0x1814 976 #define PCIECFGREG_REG_PHY_CTL7 0x181c 977 #define PCIECFGREG_PHY_DBG_CLKREQ0 0x1E10 978 #define PCIECFGREG_PHY_DBG_CLKREQ1 0x1E14 979 #define PCIECFGREG_PHY_DBG_CLKREQ2 0x1E18 980 #define PCIECFGREG_PHY_DBG_CLKREQ3 0x1E1C 981 #define PCIECFGREG_PHY_LTSSM_HIST_0 0x1CEC 982 #define PCIECFGREG_PHY_LTSSM_HIST_1 0x1CF0 983 #define PCIECFGREG_PHY_LTSSM_HIST_2 0x1CF4 984 #define PCIECFGREG_PHY_LTSSM_HIST_3 0x1CF8 985 #define PCIECFGREG_TREFUP 0x1814 986 #define PCIECFGREG_TREFUP_EXT 0x1818 987 988 /* PCIECFGREG_STATUS_CMD reg bit definitions */ 989 #define PCIECFG_STS_CMD_MEM_SPACE_SHIFT (1u) 990 #define PCIECFG_STS_CMD_BUS_MASTER_SHIFT (2u) 991 /* PCIECFGREG_PML1_SUB_CTRL1 Bit Definition */ 992 #define PCI_PM_L1_2_ENA_MASK 0x00000001 /* PCI-PM L1.2 Enabled */ 993 #define PCI_PM_L1_1_ENA_MASK 0x00000002 /* PCI-PM L1.1 Enabled */ 994 #define ASPM_L1_2_ENA_MASK 0x00000004 /* ASPM L1.2 Enabled */ 995 #define ASPM_L1_1_ENA_MASK 0x00000008 /* ASPM L1.1 Enabled */ 996 997 /* PCIECFGREG_PDL_CTRL1 reg bit definitions */ 998 #define PCIECFG_PDL_CTRL1_RETRAIN_REQ_MASK (0x4000u) 999 #define PCIECFG_PDL_CTRL1_RETRAIN_REQ_SHIFT (14u) 1000 #define PCIECFG_PDL_CTRL1_MAX_DLP_L1_ENTER_MASK (0x7Fu) 1001 #define PCIECFG_PDL_CTRL1_MAX_DLP_L1_ENTER_SHIFT (16u) 1002 #define PCIECFG_PDL_CTRL1_MAX_DLP_L1_ENTER_VAL (0x6Fu) 1003 1004 /* PCIECFGREG_PDL_CTRL5 reg bit definitions */ 1005 #define PCIECFG_PDL_CTRL5_DOWNSTREAM_PORT_SHIFT (8u) 1006 #define PCIECFG_PDL_CTRL5_GLOOPBACK_SHIFT (9u) 1007 1008 /* PCIe gen2 mailbox interrupt masks */ 1009 #define I_MB 0x3 1010 #define I_BIT0 0x1 1011 #define I_BIT1 0x2 1012 1013 /* PCIE gen2 config regs */ 1014 #define PCIIntstatus 0x090 1015 #define PCIIntmask 0x094 1016 #define PCISBMbx 0x98 1017 1018 /* enumeration Core regs */ 1019 #define PCIH2D_MailBox 0x140 1020 #define PCIH2D_DB1 0x144 1021 #define PCID2H_MailBox 0x148 1022 #define PCIH2D_MailBox_1 0x150 /* for dma channel1 */ 1023 #define PCIH2D_DB1_1 0x154 1024 #define PCID2H_MailBox_1 0x158 1025 #define PCIH2D_MailBox_2 0x160 /* for dma channel2 which will be used for Implicit DMA */ 1026 #define PCIH2D_DB1_2 0x164 1027 #define PCID2H_MailBox_2 0x168 1028 #define PCIH2D_DB1_3 0x174 1029 #define PCIE_CLK_CTRL 0x1E0 1030 #define PCIE_PWR_CTRL 0x1E8 1031 1032 #define PCIControl(rev) (REV_GE_64(rev) ? 0xC00 : 0x00) 1033 /* for corerev < 64 idma_en is in PCIControl regsiter */ 1034 #define IDMAControl(rev) (REV_GE_64(rev) ? 0x480 : 0x00) 1035 #define PCIMailBoxInt(rev) (REV_GE_64(rev) ? 0xC30 : 0x48) 1036 #define PCIMailBoxMask(rev) (REV_GE_64(rev) ? 0xC34 : 0x4C) 1037 #define PCIFunctionIntstatus(rev) (REV_GE_64(rev) ? 0xC10 : 0x20) 1038 #define PCIFunctionIntmask(rev) (REV_GE_64(rev) ? 0xC14 : 0x24) 1039 #define PCIPowerIntstatus(rev) (REV_GE_64(rev) ? 0xC18 : 0x1A4) 1040 #define PCIPowerIntmask(rev) (REV_GE_64(rev) ? 0xC1C : 0x1A8) 1041 #define PCIDARClkCtl(rev) (REV_GE_64(rev) ? 0xA08 : 0xAE0) 1042 #define PCIDARPwrCtl(rev) (REV_GE_64(rev) ? 0xA0C : 0xAE8) 1043 #define PCIDARFunctionIntstatus(rev) (REV_GE_64(rev) ? 0xA10 : 0xA20) 1044 #define PCIDARH2D_DB0(rev) (REV_GE_64(rev) ? 0xA20 : 0xA28) 1045 #define PCIDARErrlog(rev) (REV_GE_64(rev) ? 0xA60 : 0xA40) 1046 #define PCIDARErrlog_Addr(rev) (REV_GE_64(rev) ? 0xA64 : 0xA44) 1047 #define PCIDARMailboxint(rev) (REV_GE_64(rev) ? 0xA68 : 0xA48) 1048 1049 #define PCIMSIVecAssign 0x58 1050 1051 /* base of all HMAP window registers */ 1052 /* base of all HMAP window registers */ 1053 #define PCI_HMAP_WINDOW_BASE(rev) (REV_GE_64(rev) ? 0x580u : 0x540u) 1054 #define PCI_HMAP_VIOLATION_ADDR_L(rev) (REV_GE_64(rev) ? 0x600u : 0x5C0u) 1055 #define PCI_HMAP_VIOLATION_ADDR_U(rev) (REV_GE_64(rev) ? 0x604u : 0x5C4u) 1056 #define PCI_HMAP_VIOLATION_INFO(rev) (REV_GE_64(rev) ? 0x608u : 0x5C8u) 1057 #define PCI_HMAP_WINDOW_CONFIG(rev) (REV_GE_64(rev) ? 0x610u : 0x5D0u) 1058 1059 /* HMAP Register related offsets */ 1060 #define PCI_HMAP_NWINDOWS_SHIFT 8U 1061 #define PCI_HMAP_NWINDOWS_MASK 0x0000ff00U /* bits 8:15 */ 1062 #define PCI_HMAP_VIO_ID_MASK 0x0000007fU /* 0:14 */ 1063 #define PCI_HMAP_VIO_ID_SHIFT 0U 1064 #define PCI_HMAP_VIO_SRC_MASK 0x00008000U /* bit 15 */ 1065 #define PCI_HMAP_VIO_SRC_SHIFT 15U 1066 #define PCI_HMAP_VIO_TYPE_MASK 0x00010000U /* bit 16 */ 1067 #define PCI_HMAP_VIO_TYPE_SHIFT 16U 1068 #define PCI_HMAP_VIO_ERR_MASK 0x00060000U /* bit 17:18 */ 1069 #define PCI_HMAP_VIO_ERR_SHIFT 17U 1070 1071 #define I_F0_B0 (0x1 << 8) /* Mail box interrupt Function 0 interrupt, bit 0 */ 1072 #define I_F0_B1 (0x1 << 9) /* Mail box interrupt Function 0 interrupt, bit 1 */ 1073 1074 #define PCIECFGREG_DEVCONTROL 0xB4 1075 #define PCIECFGREG_BASEADDR0 0x10 1076 #define PCIECFGREG_BASEADDR1 0x18 1077 #define PCIECFGREG_DEVCONTROL_MRRS_SHFT 12 1078 #define PCIECFGREG_DEVCONTROL_MRRS_MASK (0x7 << PCIECFGREG_DEVCONTROL_MRRS_SHFT) 1079 #define PCIECFGREG_DEVCTRL_MPS_SHFT 5 1080 #define PCIECFGREG_DEVCTRL_MPS_MASK (0x7 << PCIECFGREG_DEVCTRL_MPS_SHFT) 1081 #define PCIECFGREG_PM_CSR_STATE_MASK 0x00000003 1082 #define PCIECFGREG_PM_CSR_STATE_D0 0 1083 #define PCIECFGREG_PM_CSR_STATE_D1 1 1084 #define PCIECFGREG_PM_CSR_STATE_D2 2 1085 #define PCIECFGREG_PM_CSR_STATE_D3_HOT 3 1086 #define PCIECFGREG_PM_CSR_STATE_D3_COLD 4 1087 1088 /* Direct Access regs */ 1089 #define DAR_ERRLOG(rev) (REV_GE_64(rev) ? \ 1090 OFFSETOF(sbpcieregs_t, u1.dar_64.errlog) : \ 1091 OFFSETOF(sbpcieregs_t, u1.dar.errlog)) 1092 #define DAR_ERRADDR(rev) (REV_GE_64(rev) ? \ 1093 OFFSETOF(sbpcieregs_t, u1.dar_64.erraddr) : \ 1094 OFFSETOF(sbpcieregs_t, u1.dar.erraddr)) 1095 #define DAR_CLK_CTRL(rev) (REV_GE_64(rev) ? \ 1096 OFFSETOF(sbpcieregs_t, u1.dar_64.clk_ctl_st) : \ 1097 OFFSETOF(sbpcieregs_t, u1.dar.clk_ctl_st)) 1098 #define DAR_INTSTAT(rev) (REV_GE_64(rev) ? \ 1099 OFFSETOF(sbpcieregs_t, u1.dar_64.intstatus) : \ 1100 OFFSETOF(sbpcieregs_t, u1.dar.intstatus)) 1101 #define DAR_PCIH2D_DB0_0(rev) (REV_GE_64(rev) ? \ 1102 OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_0_0) : \ 1103 OFFSETOF(sbpcieregs_t, u1.dar.h2d_db_0_0)) 1104 #define DAR_PCIH2D_DB0_1(rev) (REV_GE_64(rev) ? \ 1105 OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_0_1) : \ 1106 OFFSETOF(sbpcieregs_t, u1.dar.h2d_db_0_1)) 1107 #define DAR_PCIH2D_DB1_0(rev) (REV_GE_64(rev) ? \ 1108 OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_1_0) : \ 1109 OFFSETOF(sbpcieregs_t, u1.dar.h2d_db_1_0)) 1110 #define DAR_PCIH2D_DB1_1(rev) (REV_GE_64(rev) ? \ 1111 OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_1_1) : \ 1112 OFFSETOF(sbpcieregs_t, u1.dar.h2d_db_1_1)) 1113 #define DAR_PCIH2D_DB2_0(rev) (REV_GE_64(rev) ? \ 1114 OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_2_0) : \ 1115 OFFSETOF(sbpcieregs_t, u1.dar.h2d_db_2_0)) 1116 #define DAR_PCIH2D_DB2_1(rev) (REV_GE_64(rev) ? \ 1117 OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_2_1) : \ 1118 OFFSETOF(sbpcieregs_t, u1.dar.h2d_db_2_1)) 1119 #define DAR_PCIH2D_DB3_0(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_3_0) 1120 #define DAR_PCIH2D_DB3_1(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_3_1) 1121 #define DAR_PCIH2D_DB4_0(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_4_0) 1122 #define DAR_PCIH2D_DB4_1(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_4_1) 1123 #define DAR_PCIH2D_DB5_0(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_5_0) 1124 #define DAR_PCIH2D_DB5_1(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_5_1) 1125 #define DAR_PCIH2D_DB6_0(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_6_0) 1126 #define DAR_PCIH2D_DB6_1(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_6_1) 1127 #define DAR_PCIH2D_DB7_0(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_7_0) 1128 #define DAR_PCIH2D_DB7_1(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_7_1) 1129 1130 #if !defined(DONGLEBUILD) || defined(BCMSTANDALONE_TEST) 1131 #define DAR_PCIMailBoxInt(rev) (REV_GE_64(rev) ? \ 1132 OFFSETOF(sbpcieregs_t, u1.dar_64.mbox_int) : \ 1133 OFFSETOF(sbpcieregs_t, u1.dar.mbox_int)) 1134 #define DAR_PCIE_PWR_CTRL(rev) (REV_GE_64(rev) ? \ 1135 OFFSETOF(sbpcieregs_t, u1.dar_64.powerctl) : \ 1136 OFFSETOF(sbpcieregs_t, u1.dar.powerctl)) 1137 #define DAR_PCIE_DAR_CTRL(rev) (REV_GE_64(rev) ? \ 1138 OFFSETOF(sbpcieregs_t, u1.dar_64.dar_ctrl) : \ 1139 OFFSETOF(sbpcieregs_t, u1.dar.dar_ctrl)) 1140 #else 1141 #define DAR_PCIMailBoxInt(rev) PCIE_dar_mailboxint_OFFSET(rev) 1142 #define DAR_PCIE_PWR_CTRL(rev) PCIE_dar_power_control_OFFSET(rev) 1143 #define DAR_PCIE_DAR_CTRL(rev) PCIE_dar_control_OFFSET(rev) 1144 #endif 1145 1146 #define DAR_FIS_CTRL(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.fis_ctrl) 1147 1148 #define DAR_FIS_START_SHIFT 0u 1149 #define DAR_FIS_START_MASK (1u << DAR_FIS_START_SHIFT) 1150 1151 #define PCIE_PWR_REQ_PCIE (0x1 << 8) 1152 1153 /* SROM hardware region */ 1154 #define SROM_OFFSET_BAR1_CTRL 52 1155 1156 #define BAR1_ENC_SIZE_MASK 0x000e 1157 #define BAR1_ENC_SIZE_SHIFT 1 1158 1159 #define BAR1_ENC_SIZE_1M 0 1160 #define BAR1_ENC_SIZE_2M 1 1161 #define BAR1_ENC_SIZE_4M 2 1162 1163 #define PCIEGEN2_CAP_DEVSTSCTRL2_OFFSET 0xD4 1164 #define PCIEGEN2_CAP_DEVSTSCTRL2_LTRENAB 0x400 1165 1166 /* 1167 * Latency Tolerance Reporting (LTR) states 1168 * Active has the least tolerant latency requirement 1169 * Sleep is most tolerant 1170 */ 1171 #define LTR_ACTIVE 2 1172 #define LTR_ACTIVE_IDLE 1 1173 #define LTR_SLEEP 0 1174 #define LTR_FINAL_MASK 0x300 1175 #define LTR_FINAL_SHIFT 8 1176 1177 /* pwrinstatus, pwrintmask regs */ 1178 #define PCIEGEN2_PWRINT_D0_STATE_SHIFT 0 1179 #define PCIEGEN2_PWRINT_D1_STATE_SHIFT 1 1180 #define PCIEGEN2_PWRINT_D2_STATE_SHIFT 2 1181 #define PCIEGEN2_PWRINT_D3_STATE_SHIFT 3 1182 #define PCIEGEN2_PWRINT_L0_LINK_SHIFT 4 1183 #define PCIEGEN2_PWRINT_L0s_LINK_SHIFT 5 1184 #define PCIEGEN2_PWRINT_L1_LINK_SHIFT 6 1185 #define PCIEGEN2_PWRINT_L2_L3_LINK_SHIFT 7 1186 #define PCIEGEN2_PWRINT_OBFF_CHANGE_SHIFT 8 1187 1188 #define PCIEGEN2_PWRINT_D0_STATE_MASK (1 << PCIEGEN2_PWRINT_D0_STATE_SHIFT) 1189 #define PCIEGEN2_PWRINT_D1_STATE_MASK (1 << PCIEGEN2_PWRINT_D1_STATE_SHIFT) 1190 #define PCIEGEN2_PWRINT_D2_STATE_MASK (1 << PCIEGEN2_PWRINT_D2_STATE_SHIFT) 1191 #define PCIEGEN2_PWRINT_D3_STATE_MASK (1 << PCIEGEN2_PWRINT_D3_STATE_SHIFT) 1192 #define PCIEGEN2_PWRINT_L0_LINK_MASK (1 << PCIEGEN2_PWRINT_L0_LINK_SHIFT) 1193 #define PCIEGEN2_PWRINT_L0s_LINK_MASK (1 << PCIEGEN2_PWRINT_L0s_LINK_SHIFT) 1194 #define PCIEGEN2_PWRINT_L1_LINK_MASK (1 << PCIEGEN2_PWRINT_L1_LINK_SHIFT) 1195 #define PCIEGEN2_PWRINT_L2_L3_LINK_MASK (1 << PCIEGEN2_PWRINT_L2_L3_LINK_SHIFT) 1196 #define PCIEGEN2_PWRINT_OBFF_CHANGE_MASK (1 << PCIEGEN2_PWRINT_OBFF_CHANGE_SHIFT) 1197 1198 /* sbtopcie mail box */ 1199 #define SBTOPCIE_MB_FUNC0_SHIFT 8 1200 #define SBTOPCIE_MB_FUNC1_SHIFT 10 1201 #define SBTOPCIE_MB_FUNC2_SHIFT 12 1202 #define SBTOPCIE_MB_FUNC3_SHIFT 14 1203 1204 #define SBTOPCIE_MB1_FUNC0_SHIFT 9 1205 #define SBTOPCIE_MB1_FUNC1_SHIFT 11 1206 #define SBTOPCIE_MB1_FUNC2_SHIFT 13 1207 #define SBTOPCIE_MB1_FUNC3_SHIFT 15 1208 1209 /* pcieiocstatus */ 1210 #define PCIEGEN2_IOC_D0_STATE_SHIFT 8 1211 #define PCIEGEN2_IOC_D1_STATE_SHIFT 9 1212 #define PCIEGEN2_IOC_D2_STATE_SHIFT 10 1213 #define PCIEGEN2_IOC_D3_STATE_SHIFT 11 1214 #define PCIEGEN2_IOC_L0_LINK_SHIFT 12 1215 #define PCIEGEN2_IOC_L1_LINK_SHIFT 13 1216 #define PCIEGEN2_IOC_L1L2_LINK_SHIFT 14 1217 #define PCIEGEN2_IOC_L2_L3_LINK_SHIFT 15 1218 #define PCIEGEN2_IOC_BME_SHIFT 20 1219 1220 #define PCIEGEN2_IOC_D0_STATE_MASK (1 << PCIEGEN2_IOC_D0_STATE_SHIFT) 1221 #define PCIEGEN2_IOC_D1_STATE_MASK (1 << PCIEGEN2_IOC_D1_STATE_SHIFT) 1222 #define PCIEGEN2_IOC_D2_STATE_MASK (1 << PCIEGEN2_IOC_D2_STATE_SHIFT) 1223 #define PCIEGEN2_IOC_D3_STATE_MASK (1 << PCIEGEN2_IOC_D3_STATE_SHIFT) 1224 #define PCIEGEN2_IOC_L0_LINK_MASK (1 << PCIEGEN2_IOC_L0_LINK_SHIFT) 1225 #define PCIEGEN2_IOC_L1_LINK_MASK (1 << PCIEGEN2_IOC_L1_LINK_SHIFT) 1226 #define PCIEGEN2_IOC_L1L2_LINK_MASK (1 << PCIEGEN2_IOC_L1L2_LINK_SHIFT) 1227 #define PCIEGEN2_IOC_L2_L3_LINK_MASK (1 << PCIEGEN2_IOC_L2_L3_LINK_SHIFT) 1228 #define PCIEGEN2_IOC_BME_MASK (1 << PCIEGEN2_IOC_BME_SHIFT) 1229 1230 /* stat_ctrl */ 1231 #define PCIE_STAT_CTRL_RESET 0x1 1232 #define PCIE_STAT_CTRL_ENABLE 0x2 1233 #define PCIE_STAT_CTRL_INTENABLE 0x4 1234 #define PCIE_STAT_CTRL_INTSTATUS 0x8 1235 1236 /* cpl_timeout_ctrl_reg */ 1237 #define PCIE_CTO_TO_THRESHOLD_SHIFT 0 1238 #define PCIE_CTO_TO_THRESHHOLD_MASK (0xfffff << PCIE_CTO_TO_THRESHOLD_SHIFT) 1239 1240 #define PCIE_CTO_CLKCHKCNT_SHIFT 24 1241 #define PCIE_CTO_CLKCHKCNT_MASK (0xf << PCIE_CTO_CLKCHKCNT_SHIFT) 1242 1243 #define PCIE_CTO_ENAB_SHIFT 31 1244 #define PCIE_CTO_ENAB_MASK (0x1 << PCIE_CTO_ENAB_SHIFT) 1245 1246 /* 1247 * For corerev >= 69, core_fref is always 29.9MHz instead of 37.4MHz. 1248 * Use different default threshold value to have 10ms timeout (0x49FB6 * 33ns). 1249 */ 1250 #define PCIE_CTO_TO_THRESH_DEFAULT 0x58000 1251 #define PCIE_CTO_TO_THRESH_DEFAULT_REV69 0x49FB6 1252 1253 #define PCIE_CTO_CLKCHKCNT_VAL 0xA 1254 1255 /* ErrLog */ 1256 #define PCIE_SROMRD_ERR_SHIFT 5 1257 #define PCIE_SROMRD_ERR_MASK (0x1 << PCIE_SROMRD_ERR_SHIFT) 1258 1259 #define PCIE_CTO_ERR_SHIFT 8 1260 #define PCIE_CTO_ERR_MASK (0x1 << PCIE_CTO_ERR_SHIFT) 1261 1262 #define PCIE_CTO_ERR_CODE_SHIFT 9 1263 #define PCIE_CTO_ERR_CODE_MASK (0x3 << PCIE_CTO_ERR_CODE_SHIFT) 1264 1265 #define PCIE_BP_CLK_OFF_ERR_SHIFT 12 1266 #define PCIE_BP_CLK_OFF_ERR_MASK (0x1 << PCIE_BP_CLK_OFF_ERR_SHIFT) 1267 1268 #define PCIE_BP_IN_RESET_ERR_SHIFT 13 1269 #define PCIE_BP_IN_RESET_ERR_MASK (0x1 << PCIE_BP_IN_RESET_ERR_SHIFT) 1270 1271 /* PCIE control per Function */ 1272 #define PCIE_FTN_DLYPERST_SHIFT 1 1273 #define PCIE_FTN_DLYPERST_MASK (1 << PCIE_FTN_DLYPERST_SHIFT) 1274 1275 #define PCIE_FTN_WakeModeL2_SHIFT 3 1276 #define PCIE_FTN_WakeModeL2_MASK (1 << PCIE_FTN_WakeModeL2_SHIFT) 1277 1278 #define PCIE_FTN_MSI_B2B_EN_SHIFT 4 1279 #define PCIE_FTN_MSI_B2B_EN_MASK (1 << PCIE_FTN_MSI_B2B_EN_SHIFT) 1280 1281 #define PCIE_FTN_MSI_FIFO_CLEAR_SHIFT 5 1282 #define PCIE_FTN_MSI_FIFO_CLEAR_MASK (1 << PCIE_FTN_MSI_FIFO_CLEAR_SHIFT) 1283 1284 #define PCIE_FTN_SWPME_SHIFT 6 1285 #define PCIE_FTN_SWPME_MASK (1 << PCIE_FTN_SWPME_SHIFT) 1286 1287 #ifdef BCMDRIVER 1288 #if !defined(DONGLEBUILD) || defined(BCMSTANDALONE_TEST) 1289 void pcie_watchdog_reset(osl_t *osh, si_t *sih, uint32 wd_mask, uint32 wd_val); 1290 void pcie_serdes_iddqdisable(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs); 1291 void pcie_set_trefup_time_100us(si_t *sih); 1292 uint32 pcie_cto_to_thresh_default(uint corerev); 1293 uint32 pcie_corereg(osl_t *osh, volatile void *regs, uint32 offset, uint32 mask, uint32 val); 1294 #endif /* !defined(DONGLEBUILD) || defined(BCMSTANDALONE_TEST) */ 1295 #if defined(DONGLEBUILD) 1296 void pcie_coherent_accenable(osl_t *osh, si_t *sih); 1297 #endif /* DONGLEBUILD */ 1298 #endif /* BCMDRIVER */ 1299 1300 /* DMA intstatus and intmask */ 1301 #define I_PC (1 << 10) /* pci descriptor error */ 1302 #define I_PD (1 << 11) /* pci data error */ 1303 #define I_DE (1 << 12) /* descriptor protocol error */ 1304 #define I_RU (1 << 13) /* receive descriptor underflow */ 1305 #define I_RO (1 << 14) /* receive fifo overflow */ 1306 #define I_XU (1 << 15) /* transmit fifo underflow */ 1307 #define I_RI (1 << 16) /* receive interrupt */ 1308 #define I_XI (1 << 24) /* transmit interrupt */ 1309 1310 #define PD_DMA_INT_MASK_H2D 0x1DC00 1311 #define PD_DMA_INT_MASK_D2H 0x1DC00 1312 #define PD_DB_INT_MASK 0xFF0000 1313 1314 #if defined(DONGLEBUILD) 1315 #if REV_GE_64(BCMPCIEREV) 1316 #define PD_DEV0_DB_INTSHIFT 8u 1317 #define PD_DEV1_DB_INTSHIFT 10u 1318 #define PD_DEV2_DB_INTSHIFT 12u 1319 #define PD_DEV3_DB_INTSHIFT 14u 1320 #else 1321 #define PD_DEV0_DB_INTSHIFT 16u 1322 #define PD_DEV1_DB_INTSHIFT 18u 1323 #define PD_DEV2_DB_INTSHIFT 20u 1324 #define PD_DEV3_DB_INTSHIFT 22u 1325 #endif /* BCMPCIEREV */ 1326 #endif /* DONGLEBUILD */ 1327 1328 #define PCIE_INVALID_OFFSET 0x18003ffc /* Invalid Register Offset for Induce Error */ 1329 #define PCIE_INVALID_DATA 0x55555555 /* Invalid Data for Induce Error */ 1330 1331 #define PD_DEV0_DB0_INTMASK (0x1 << PD_DEV0_DB_INTSHIFT) 1332 #define PD_DEV0_DB1_INTMASK (0x2 << PD_DEV0_DB_INTSHIFT) 1333 #define PD_DEV0_DB_INTMASK ((PD_DEV0_DB0_INTMASK) | (PD_DEV0_DB1_INTMASK)) 1334 1335 #define PD_DEV1_DB0_INTMASK (0x1 << PD_DEV1_DB_INTSHIFT) 1336 #define PD_DEV1_DB1_INTMASK (0x2 << PD_DEV1_DB_INTSHIFT) 1337 #define PD_DEV1_DB_INTMASK ((PD_DEV1_DB0_INTMASK) | (PD_DEV1_DB1_INTMASK)) 1338 1339 #define PD_DEV2_DB0_INTMASK (0x1 << PD_DEV2_DB_INTSHIFT) 1340 #define PD_DEV2_DB1_INTMASK (0x2 << PD_DEV2_DB_INTSHIFT) 1341 #define PD_DEV2_DB_INTMASK ((PD_DEV2_DB0_INTMASK) | (PD_DEV2_DB1_INTMASK)) 1342 1343 #define PD_DEV3_DB0_INTMASK (0x1 << PD_DEV3_DB_INTSHIFT) 1344 #define PD_DEV3_DB1_INTMASK (0x2 << PD_DEV3_DB_INTSHIFT) 1345 #define PD_DEV3_DB_INTMASK ((PD_DEV3_DB0_INTMASK) | (PD_DEV3_DB1_INTMASK)) 1346 1347 #define PD_DEV0_DMA_INTMASK 0x80 1348 1349 #define PD_FUNC0_MB_INTSHIFT 8u 1350 #define PD_FUNC0_MB_INTMASK (0x3 << PD_FUNC0_MB_INTSHIFT) 1351 1352 #define PD_FUNC0_PCIE_SB_INTSHIFT 0u 1353 #define PD_FUNC0_PCIE_SB__INTMASK (0x3 << PD_FUNC0_PCIE_SB_INTSHIFT) 1354 1355 #define PD_DEV0_PWRSTATE_INTSHIFT 24u 1356 #define PD_DEV0_PWRSTATE_INTMASK (0x1 << PD_DEV0_PWRSTATE_INTSHIFT) 1357 1358 #define PD_DEV0_PERST_INTSHIFT 6u 1359 #define PD_DEV0_PERST_INTMASK (0x1 << PD_DEV0_PERST_INTSHIFT) 1360 1361 #define PD_MSI_FIFO_OVERFLOW_INTSHIFT 28u 1362 #define PD_MSI_FIFO_OVERFLOW_INTMASK (0x1 << PD_MSI_FIFO_OVERFLOW_INTSHIFT) 1363 1364 #if defined(BCMPCIE_IFRM) 1365 #define PD_IFRM_INTSHIFT 5u 1366 #define PD_IFRM_INTMASK (0x1 << PD_IFRM_INTSHIFT) 1367 #endif /* BCMPCIE_IFRM */ 1368 1369 /* HMAP related constants */ 1370 #define PD_HMAP_VIO_INTSHIFT 3u 1371 #define PD_HMAP_VIO_INTMASK (0x1 << PD_HMAP_VIO_INTSHIFT) 1372 #define PD_HMAP_VIO_CLR_VAL 0x3 /* write 0b11 to clear HMAP violation */ 1373 #define PD_HMAP_VIO_SHIFT_VAL 17u /* bits 17:18 clear HMAP violation */ 1374 1375 #define PD_FLR0_IN_PROG_INTSHIFT 0u 1376 #define PD_FLR0_IN_PROG_INTMASK (0x1 << PD_FLR0_IN_PROG_INTSHIFT) 1377 #define PD_FLR1_IN_PROG_INTSHIFT 1u 1378 #define PD_FLR1_IN_PROG_INTMASK (0x1 << PD_FLR1_IN_PROG_INTSHIFT) 1379 1380 /* DMA channel 2 datapath use case 1381 * Implicit DMA uses DMA channel 2 (outbound only) 1382 */ 1383 #if defined(BCMPCIE_IDMA) && !defined(BCMPCIE_IDMA_DISABLED) 1384 #define PD_DEV2_INTMASK PD_DEV2_DB0_INTMASK 1385 #elif defined(BCMPCIE_IFRM) && !defined(BCMPCIE_IFRM_DISABLED) 1386 #define PD_DEV2_INTMASK PD_DEV2_DB0_INTMASK 1387 #elif defined(BCMPCIE_DMA_CH2) 1388 #define PD_DEV2_INTMASK PD_DEV2_DB0_INTMASK 1389 #else 1390 #define PD_DEV2_INTMASK 0u 1391 #endif /* BCMPCIE_IDMA || BCMPCIE_DMA_CH2 || BCMPCIE_IFRM */ 1392 /* DMA channel 1 datapath use case */ 1393 #ifdef BCMPCIE_DMA_CH1 1394 #define PD_DEV1_INTMASK PD_DEV1_DB0_INTMASK 1395 #else 1396 #define PD_DEV1_INTMASK 0u 1397 #endif /* BCMPCIE_DMA_CH1 */ 1398 #if defined(BCMPCIE_IDMA) || defined(BCMPCIE_IFRM) 1399 #define PD_DEV1_IDMA_DW_INTMASK PD_DEV1_DB1_INTMASK 1400 #else 1401 #define PD_DEV1_IDMA_DW_INTMASK 0u 1402 #endif /* BCMPCIE_IDMA || BCMPCIE_IFRM */ 1403 1404 #define PD_DEV0_INTMASK \ 1405 (PD_DEV0_DMA_INTMASK | PD_DEV0_DB0_INTMASK | PD_DEV0_PWRSTATE_INTMASK | \ 1406 PD_DEV0_PERST_INTMASK | PD_DEV1_INTMASK | PD_DEV2_INTMASK | PD_DEV0_DB1_INTMASK | \ 1407 PD_DEV1_IDMA_DW_INTMASK) 1408 1409 /* implicit DMA index */ 1410 #define PD_IDMA_COMP 0xf /* implicit dma complete */ 1411 #define PD_IDMA_IDX0_COMP ((uint32)1 << 0) /* implicit dma index0 complete */ 1412 #define PD_IDMA_IDX1_COMP ((uint32)1 << 1) /* implicit dma index1 complete */ 1413 #define PD_IDMA_IDX2_COMP ((uint32)1 << 2) /* implicit dma index2 complete */ 1414 #define PD_IDMA_IDX3_COMP ((uint32)1 << 3) /* implicit dma index3 complete */ 1415 1416 #define PCIE_D2H_DB0_VAL (0x12345678) 1417 1418 #define PD_ERR_ATTN_INTMASK (1u << 29) 1419 #define PD_LINK_DOWN_INTMASK (1u << 27) 1420 1421 #define PD_ERR_TTX_REQ_DURING_D3 (1u << 31) /* Tx mem req on iface when in non-D0 */ 1422 #define PD_PRI_SIG_TARGET_ABORT_F1 (1u << 19) /* Rcvd target Abort Err Status (CA) F1 */ 1423 #define PD_ERR_UNSPPORT_F1 (1u << 18) /* Unsupported Request Error Status. F1 */ 1424 #define PD_ERR_ECRC_F1 (1u << 17) /* ECRC Error TLP Status. F1 */ 1425 #define PD_ERR_MALF_TLP_F1 (1u << 16) /* Malformed TLP Status. F1 */ 1426 #define PD_ERR_RX_OFLOW_F1 (1u << 15) /* Receiver Overflow Status. */ 1427 #define PD_ERR_UNEXP_CPL_F1 (1u << 14) /* Unexpected Completion Status. F1 */ 1428 #define PD_ERR_MASTER_ABRT_F1 (1u << 13) /* Receive UR Completion Status. F1 */ 1429 #define PD_ERR_CPL_TIMEOUT_F1 (1u << 12) /* Completer Timeout Status F1 */ 1430 #define PD_ERR_FC_PRTL_F1 (1u << 11) /* Flow Control Protocol Error Status F1 */ 1431 #define PD_ERR_PSND_TLP_F1 (1u << 10) /* Poisoned Error Status F1 */ 1432 #define PD_PRI_SIG_TARGET_ABORT (1u << 9) /* Received target Abort Error Status(CA) */ 1433 #define PD_ERR_UNSPPORT (1u << 8) /* Unsupported Request Error Status. */ 1434 #define PD_ERR_ECRC (1u << 7) /* ECRC Error TLP Status. */ 1435 #define PD_ERR_MALF_TLP (1u << 6) /* Malformed TLP Status. */ 1436 #define PD_ERR_RX_OFLOW (1u << 5) /* Receiver Overflow Status. */ 1437 #define PD_ERR_UNEXP_CPL (1u << 4) /* Unexpected Completion Status. */ 1438 #define PD_ERR_MASTER_ABRT (1u << 3) /* Receive UR Completion Status. */ 1439 #define PD_ERR_CPL_TIMEOUT (1u << 2) /* Completer Timeout Status */ 1440 #define PD_ERR_FC_PRTL (1u << 1) /* Flow Control Protocol Error Status */ 1441 #define PD_ERR_PSND_TLP (1u << 0) /* Poisoned Error Status */ 1442 1443 /* All ERR_ATTN of F1 */ 1444 #define PD_ERR_FUNCTION1 \ 1445 (PD_ERR_PSND_TLP_F1 | PD_ERR_FC_PRTL_F1 | PD_ERR_CPL_TIMEOUT_F1 | PD_ERR_MASTER_ABRT_F1 | \ 1446 PD_ERR_UNEXP_CPL_F1 | PD_ERR_RX_OFLOW_F1 | PD_ERR_MALF_TLP_F1 | PD_ERR_ECRC_F1 | \ 1447 PD_ERR_UNSPPORT_F1 | PD_PRI_SIG_TARGET_ABORT_F1) 1448 1449 #define PD_ERR_TTX_REQ_DURING_D3_FN0 (1u << 10) /* Tx mem req on iface when in non-D0 */ 1450 1451 /* H2D Doorbell Fields for IDMA / PWI */ 1452 #define PD_DB_FRG_ID_SHIFT (0u) 1453 #define PD_DB_FRG_ID_MASK (0xFu) /* bits 3:0 */ 1454 #define PD_DB_DMA_TYPE_SHIFT (4u) 1455 #define PD_DB_DMA_TYPE_MASK (0xFu) /* bits 7:4 */ 1456 #define PD_DB_RINGIDX_NUM_SHIFT (8u) 1457 #define PD_DB_RINGIDX_NUM_MASK (0xFFu) /* bits 15:8 */ 1458 #define PD_DB_INDEX_VAL_SHIFT (16u) 1459 #define PD_DB_INDEX_VAL_MASK (0xFFFFu) /* bits 31:16 */ 1460 1461 /* PWI LUT entry fields */ 1462 #define PWI_FLOW_VALID_MASK (0x1u) 1463 #define PWI_FLOW_VALID_SHIFT (22u) 1464 #define PWI_FLOW_RING_GROUP_ID_MASK (0x3u) 1465 #define PWI_FLOW_RING_GROUP_ID_SHIFT (20u) 1466 #define PWI_HOST_RINGIDX_MASK (0xFFu) /* Host Ring Index Number[19:12] */ 1467 #define PWI_HOST_RINGIDX_SHIFT (12u) 1468 1469 /* DMA_TYPE Values */ 1470 #define PD_DB_DMA_TYPE_NO_IDMA (0u) 1471 #define PD_DB_DMA_TYPE_IDMA (1u) 1472 #define PD_DB_DMA_TYPE_PWI (2u) 1473 #define PD_DB_DMA_TYPE_RXPOST(rev) (REV_GE_73((rev)) ? (1u) : (5u)) 1474 #define PD_DB_DMA_TYPE_TXCPL(rev) (REV_GE_73((rev)) ? (2u) : (6u)) 1475 #define PD_DB_DMA_TYPE_RXCPL(rev) (REV_GE_73((rev)) ? (3u) : (7u)) 1476 1477 /* All ERR_ATTN of F0 */ 1478 #define PD_ERR_FUNCTION0 \ 1479 (PD_ERR_PSND_TLP | PD_ERR_FC_PRTL | PD_ERR_CPL_TIMEOUT | PD_ERR_MASTER_ABRT | \ 1480 PD_ERR_UNEXP_CPL | PD_ERR_RX_OFLOW | PD_ERR_MALF_TLP | PD_ERR_ECRC | \ 1481 PD_ERR_UNSPPORT | PD_PRI_SIG_TARGET_ABORT) 1482 /* Shift of F1 bits */ 1483 #define PD_ERR_FUNCTION1_SHIFT 10u 1484 1485 #endif /* _PCIE_CORE_H */ 1486