1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2010 Broadcom Corporation 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any 5*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above 6*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11*4882a593Smuzhiyun * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13*4882a593Smuzhiyun * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14*4882a593Smuzhiyun * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef _BRCM_MAIN_H_ 18*4882a593Smuzhiyun #define _BRCM_MAIN_H_ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <linux/etherdevice.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #include <brcmu_utils.h> 23*4882a593Smuzhiyun #include "types.h" 24*4882a593Smuzhiyun #include "d11.h" 25*4882a593Smuzhiyun #include "scb.h" 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define INVCHANNEL 255 /* invalid channel */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* max # brcms_c_module_register() calls */ 30*4882a593Smuzhiyun #define BRCMS_MAXMODULES 22 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define SEQNUM_SHIFT 4 33*4882a593Smuzhiyun #define SEQNUM_MAX 0x1000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define NTXRATE 64 /* # tx MPDUs rate is reported for */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Maximum wait time for a MAC suspend */ 38*4882a593Smuzhiyun /* uS: 83mS is max packet time (64KB ampdu @ 6Mbps) */ 39*4882a593Smuzhiyun #define BRCMS_MAX_MAC_SUSPEND 83000 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* responses for probe requests older that this are tossed, zero to disable */ 42*4882a593Smuzhiyun #define BRCMS_PRB_RESP_TIMEOUT 0 /* Disable probe response timeout */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* transmit buffer max headroom for protocol headers */ 45*4882a593Smuzhiyun #define TXOFF (D11_TXH_LEN + D11_PHY_HDR_LEN) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Macros for doing definition and get/set of bitfields 48*4882a593Smuzhiyun * Usage example, e.g. a three-bit field (bits 4-6): 49*4882a593Smuzhiyun * #define <NAME>_M BITFIELD_MASK(3) 50*4882a593Smuzhiyun * #define <NAME>_S 4 51*4882a593Smuzhiyun * ... 52*4882a593Smuzhiyun * regval = R_REG(osh, ®s->regfoo); 53*4882a593Smuzhiyun * field = GFIELD(regval, <NAME>); 54*4882a593Smuzhiyun * regval = SFIELD(regval, <NAME>, 1); 55*4882a593Smuzhiyun * W_REG(osh, ®s->regfoo, regval); 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define BITFIELD_MASK(width) \ 58*4882a593Smuzhiyun (((unsigned)1 << (width)) - 1) 59*4882a593Smuzhiyun #define GFIELD(val, field) \ 60*4882a593Smuzhiyun (((val) >> field ## _S) & field ## _M) 61*4882a593Smuzhiyun #define SFIELD(val, field, bits) \ 62*4882a593Smuzhiyun (((val) & (~(field ## _M << field ## _S))) | \ 63*4882a593Smuzhiyun ((unsigned)(bits) << field ## _S)) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define SW_TIMER_MAC_STAT_UPD 30 /* periodic MAC stats update */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* max # supported core revisions (0 .. MAXCOREREV - 1) */ 68*4882a593Smuzhiyun #define MAXCOREREV 28 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Double check that unsupported cores are not enabled */ 71*4882a593Smuzhiyun #if CONF_MSK(D11CONF, 0x4f) || CONF_GE(D11CONF, MAXCOREREV) 72*4882a593Smuzhiyun #error "Configuration for D11CONF includes unsupported versions." 73*4882a593Smuzhiyun #endif /* Bad versions */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* values for shortslot_override */ 76*4882a593Smuzhiyun #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */ 77*4882a593Smuzhiyun #define BRCMS_SHORTSLOT_OFF 0 /* Turn off short slot */ 78*4882a593Smuzhiyun #define BRCMS_SHORTSLOT_ON 1 /* Turn on short slot */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* value for short/long and mixmode/greenfield preamble */ 81*4882a593Smuzhiyun #define BRCMS_LONG_PREAMBLE (0) 82*4882a593Smuzhiyun #define BRCMS_SHORT_PREAMBLE (1 << 0) 83*4882a593Smuzhiyun #define BRCMS_GF_PREAMBLE (1 << 1) 84*4882a593Smuzhiyun #define BRCMS_MM_PREAMBLE (1 << 2) 85*4882a593Smuzhiyun #define BRCMS_IS_MIMO_PREAMBLE(_pre) (((_pre) == BRCMS_GF_PREAMBLE) || \ 86*4882a593Smuzhiyun ((_pre) == BRCMS_MM_PREAMBLE)) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* TxFrameID */ 89*4882a593Smuzhiyun /* seq and frag bits: SEQNUM_SHIFT, FRAGNUM_MASK (802.11.h) */ 90*4882a593Smuzhiyun /* rate epoch bits: TXFID_RATE_SHIFT, TXFID_RATE_MASK ((wlc_rate.c) */ 91*4882a593Smuzhiyun #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */ 92*4882a593Smuzhiyun #define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */ 93*4882a593Smuzhiyun #define TXFID_SEQ_SHIFT 5 /* Number of bit shifts */ 94*4882a593Smuzhiyun #define TXFID_RATE_PROBE_MASK 0x8000 /* Bit 15 for rate probe */ 95*4882a593Smuzhiyun #define TXFID_RATE_MASK 0x0018 /* Mask for bits 3 and 4 */ 96*4882a593Smuzhiyun #define TXFID_RATE_SHIFT 3 /* Shift 3 bits for rate mask */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* promote boardrev */ 99*4882a593Smuzhiyun #define BOARDREV_PROMOTABLE 0xFF /* from */ 100*4882a593Smuzhiyun #define BOARDREV_PROMOTED 1 /* to */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define DATA_BLOCK_TX_SUPR (1 << 4) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Ucode MCTL_WAKE override bits */ 105*4882a593Smuzhiyun #define BRCMS_WAKE_OVERRIDE_CLKCTL 0x01 106*4882a593Smuzhiyun #define BRCMS_WAKE_OVERRIDE_PHYREG 0x02 107*4882a593Smuzhiyun #define BRCMS_WAKE_OVERRIDE_MACSUSPEND 0x04 108*4882a593Smuzhiyun #define BRCMS_WAKE_OVERRIDE_TXFIFO 0x08 109*4882a593Smuzhiyun #define BRCMS_WAKE_OVERRIDE_FORCEFAST 0x10 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* stuff pulled in from wlc.c */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* Interrupt bit error summary. Don't include I_RU: we refill DMA at other 114*4882a593Smuzhiyun * times; and if we run out, constant I_RU interrupts may cause lockup. We 115*4882a593Smuzhiyun * will still get error counts from rx0ovfl. 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun #define I_ERRORS (I_PC | I_PD | I_DE | I_RO | I_XU) 118*4882a593Smuzhiyun /* default software intmasks */ 119*4882a593Smuzhiyun #define DEF_RXINTMASK (I_RI) /* enable rx int on rxfifo only */ 120*4882a593Smuzhiyun #define DEF_MACINTMASK (MI_TXSTOP | MI_TBTT | MI_ATIMWINEND | MI_PMQ | \ 121*4882a593Smuzhiyun MI_PHYTXERR | MI_DMAINT | MI_TFS | MI_BG_NOISE | \ 122*4882a593Smuzhiyun MI_CCA | MI_TO | MI_GP0 | MI_RFDISABLE | MI_PWRUP) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define MAXTXPKTS 6 /* max # pkts pending */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* frameburst */ 127*4882a593Smuzhiyun #define MAXTXFRAMEBURST 8 /* vanilla xpress mode: max frames/burst */ 128*4882a593Smuzhiyun #define MAXFRAMEBURST_TXOP 10000 /* Frameburst TXOP in usec */ 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define NFIFO 6 /* # tx/rx fifopairs */ 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* PLL requests */ 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* pll is shared on old chips */ 135*4882a593Smuzhiyun #define BRCMS_PLLREQ_SHARED 0x1 136*4882a593Smuzhiyun /* hold pll for radio monitor register checking */ 137*4882a593Smuzhiyun #define BRCMS_PLLREQ_RADIO_MON 0x2 138*4882a593Smuzhiyun /* hold/release pll for some short operation */ 139*4882a593Smuzhiyun #define BRCMS_PLLREQ_FLIP 0x4 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define CHANNEL_BANDUNIT(wlc, ch) \ 142*4882a593Smuzhiyun (((ch) <= CH_MAX_2G_CHANNEL) ? BAND_2G_INDEX : BAND_5G_INDEX) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define OTHERBANDUNIT(wlc) \ 145*4882a593Smuzhiyun ((uint)((wlc)->band->bandunit ? BAND_2G_INDEX : BAND_5G_INDEX)) 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* 148*4882a593Smuzhiyun * 802.11 protection information 149*4882a593Smuzhiyun * 150*4882a593Smuzhiyun * _g: use g spec protection, driver internal. 151*4882a593Smuzhiyun * g_override: override for use of g spec protection. 152*4882a593Smuzhiyun * gmode_user: user config gmode, operating band->gmode is different. 153*4882a593Smuzhiyun * overlap: Overlap BSS/IBSS protection for both 11g and 11n. 154*4882a593Smuzhiyun * nmode_user: user config nmode, operating pub->nmode is different. 155*4882a593Smuzhiyun * n_cfg: use OFDM protection on MIMO frames. 156*4882a593Smuzhiyun * n_cfg_override: override for use of N protection. 157*4882a593Smuzhiyun * nongf: non-GF present protection. 158*4882a593Smuzhiyun * nongf_override: override for use of GF protection. 159*4882a593Smuzhiyun * n_pam_override: override for preamble: MM or GF. 160*4882a593Smuzhiyun * n_obss: indicated OBSS Non-HT STA present. 161*4882a593Smuzhiyun */ 162*4882a593Smuzhiyun struct brcms_protection { 163*4882a593Smuzhiyun bool _g; 164*4882a593Smuzhiyun s8 g_override; 165*4882a593Smuzhiyun u8 gmode_user; 166*4882a593Smuzhiyun s8 overlap; 167*4882a593Smuzhiyun s8 nmode_user; 168*4882a593Smuzhiyun s8 n_cfg; 169*4882a593Smuzhiyun s8 n_cfg_override; 170*4882a593Smuzhiyun bool nongf; 171*4882a593Smuzhiyun s8 nongf_override; 172*4882a593Smuzhiyun s8 n_pam_override; 173*4882a593Smuzhiyun bool n_obss; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* 177*4882a593Smuzhiyun * anything affecting the single/dual streams/antenna operation 178*4882a593Smuzhiyun * 179*4882a593Smuzhiyun * hw_txchain: HW txchain bitmap cfg. 180*4882a593Smuzhiyun * txchain: txchain bitmap being used. 181*4882a593Smuzhiyun * txstreams: number of txchains being used. 182*4882a593Smuzhiyun * hw_rxchain: HW rxchain bitmap cfg. 183*4882a593Smuzhiyun * rxchain: rxchain bitmap being used. 184*4882a593Smuzhiyun * rxstreams: number of rxchains being used. 185*4882a593Smuzhiyun * ant_rx_ovr: rx antenna override. 186*4882a593Smuzhiyun * txant: userTx antenna setting. 187*4882a593Smuzhiyun * phytxant: phyTx antenna setting in txheader. 188*4882a593Smuzhiyun * ss_opmode: singlestream Operational mode, 0:siso; 1:cdd. 189*4882a593Smuzhiyun * ss_algosel_auto: if true, use wlc->stf->ss_algo_channel; 190*4882a593Smuzhiyun * else use wlc->band->stf->ss_mode_band. 191*4882a593Smuzhiyun * ss_algo_channel: ss based on per-channel algo: 0: SISO, 1: CDD 2: STBC. 192*4882a593Smuzhiyun * rxchain_restore_delay: delay time to restore default rxchain. 193*4882a593Smuzhiyun * ldpc: AUTO/ON/OFF ldpc cap supported. 194*4882a593Smuzhiyun * txcore[MAX_STREAMS_SUPPORTED + 1]: bitmap of selected core for each Nsts. 195*4882a593Smuzhiyun * spatial_policy: 196*4882a593Smuzhiyun */ 197*4882a593Smuzhiyun struct brcms_stf { 198*4882a593Smuzhiyun u8 hw_txchain; 199*4882a593Smuzhiyun u8 txchain; 200*4882a593Smuzhiyun u8 txstreams; 201*4882a593Smuzhiyun u8 hw_rxchain; 202*4882a593Smuzhiyun u8 rxchain; 203*4882a593Smuzhiyun u8 rxstreams; 204*4882a593Smuzhiyun u8 ant_rx_ovr; 205*4882a593Smuzhiyun s8 txant; 206*4882a593Smuzhiyun u16 phytxant; 207*4882a593Smuzhiyun u8 ss_opmode; 208*4882a593Smuzhiyun bool ss_algosel_auto; 209*4882a593Smuzhiyun u16 ss_algo_channel; 210*4882a593Smuzhiyun u8 rxchain_restore_delay; 211*4882a593Smuzhiyun s8 ldpc; 212*4882a593Smuzhiyun u8 txcore[MAX_STREAMS_SUPPORTED + 1]; 213*4882a593Smuzhiyun s8 spatial_policy; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #define BRCMS_STF_SS_STBC_TX(wlc, scb) \ 217*4882a593Smuzhiyun (((wlc)->stf->txstreams > 1) && (((wlc)->band->band_stf_stbc_tx == ON) \ 218*4882a593Smuzhiyun || (((scb)->flags & SCB_STBCCAP) && \ 219*4882a593Smuzhiyun (wlc)->band->band_stf_stbc_tx == AUTO && \ 220*4882a593Smuzhiyun isset(&((wlc)->stf->ss_algo_channel), PHY_TXC1_MODE_STBC)))) 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun #define BRCMS_STBC_CAP_PHY(wlc) (BRCMS_ISNPHY(wlc->band) && \ 223*4882a593Smuzhiyun NREV_GE(wlc->band->phyrev, 3)) 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun #define BRCMS_SGI_CAP_PHY(wlc) ((BRCMS_ISNPHY(wlc->band) && \ 226*4882a593Smuzhiyun NREV_GE(wlc->band->phyrev, 3)) || \ 227*4882a593Smuzhiyun BRCMS_ISLCNPHY(wlc->band)) 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun #define BRCMS_CHAN_PHYTYPE(x) (((x) & RXS_CHAN_PHYTYPE_MASK) \ 230*4882a593Smuzhiyun >> RXS_CHAN_PHYTYPE_SHIFT) 231*4882a593Smuzhiyun #define BRCMS_CHAN_CHANNEL(x) (((x) & RXS_CHAN_ID_MASK) \ 232*4882a593Smuzhiyun >> RXS_CHAN_ID_SHIFT) 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun /* 235*4882a593Smuzhiyun * core state (mac) 236*4882a593Smuzhiyun */ 237*4882a593Smuzhiyun struct brcms_core { 238*4882a593Smuzhiyun uint coreidx; /* # sb enumerated core */ 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun /* fifo */ 241*4882a593Smuzhiyun uint *txavail[NFIFO]; /* # tx descriptors available */ 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun struct macstat *macstat_snapshot; /* mac hw prev read values */ 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /* 247*4882a593Smuzhiyun * band state (phy+ana+radio) 248*4882a593Smuzhiyun */ 249*4882a593Smuzhiyun struct brcms_band { 250*4882a593Smuzhiyun int bandtype; /* BRCM_BAND_2G, BRCM_BAND_5G */ 251*4882a593Smuzhiyun uint bandunit; /* bandstate[] index */ 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun u16 phytype; /* phytype */ 254*4882a593Smuzhiyun u16 phyrev; 255*4882a593Smuzhiyun u16 radioid; 256*4882a593Smuzhiyun u16 radiorev; 257*4882a593Smuzhiyun struct brcms_phy_pub *pi; /* pointer to phy specific information */ 258*4882a593Smuzhiyun bool abgphy_encore; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun u8 gmode; /* currently active gmode */ 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun struct scb *hwrs_scb; /* permanent scb for hw rateset */ 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun /* band-specific copy of default_bss.rateset */ 265*4882a593Smuzhiyun struct brcms_c_rateset defrateset; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun u8 band_stf_ss_mode; /* Configured STF type, 0:siso; 1:cdd */ 268*4882a593Smuzhiyun s8 band_stf_stbc_tx; /* STBC TX 0:off; 1:force on; -1:auto */ 269*4882a593Smuzhiyun /* rates supported by chip (phy-specific) */ 270*4882a593Smuzhiyun struct brcms_c_rateset hw_rateset; 271*4882a593Smuzhiyun u8 basic_rate[BRCM_MAXRATE + 1]; /* basic rates indexed by rate */ 272*4882a593Smuzhiyun bool mimo_cap_40; /* 40 MHz cap enabled on this band */ 273*4882a593Smuzhiyun s8 antgain; /* antenna gain from srom */ 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun u16 CWmin; /* minimum size of contention window, in unit of aSlotTime */ 276*4882a593Smuzhiyun u16 CWmax; /* maximum size of contention window, in unit of aSlotTime */ 277*4882a593Smuzhiyun struct ieee80211_supported_band band; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun /* module control blocks */ 281*4882a593Smuzhiyun struct modulecb { 282*4882a593Smuzhiyun /* module name : NULL indicates empty array member */ 283*4882a593Smuzhiyun char name[32]; 284*4882a593Smuzhiyun /* handle passed when handler 'doiovar' is called */ 285*4882a593Smuzhiyun struct brcms_info *hdl; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun int (*down_fn)(void *handle); /* down handler. Note: the int returned 288*4882a593Smuzhiyun * by the down function is a count of the 289*4882a593Smuzhiyun * number of timers that could not be 290*4882a593Smuzhiyun * freed. 291*4882a593Smuzhiyun */ 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun struct brcms_hw_band { 296*4882a593Smuzhiyun int bandtype; /* BRCM_BAND_2G, BRCM_BAND_5G */ 297*4882a593Smuzhiyun uint bandunit; /* bandstate[] index */ 298*4882a593Smuzhiyun u16 mhfs[MHFMAX]; /* MHF array shadow */ 299*4882a593Smuzhiyun u8 bandhw_stf_ss_mode; /* HW configured STF type, 0:siso; 1:cdd */ 300*4882a593Smuzhiyun u16 CWmin; 301*4882a593Smuzhiyun u16 CWmax; 302*4882a593Smuzhiyun u32 core_flags; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun u16 phytype; /* phytype */ 305*4882a593Smuzhiyun u16 phyrev; 306*4882a593Smuzhiyun u16 radioid; 307*4882a593Smuzhiyun u16 radiorev; 308*4882a593Smuzhiyun struct brcms_phy_pub *pi; /* pointer to phy specific information */ 309*4882a593Smuzhiyun bool abgphy_encore; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun struct brcms_hardware { 313*4882a593Smuzhiyun bool _piomode; /* true if pio mode */ 314*4882a593Smuzhiyun struct brcms_c_info *wlc; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun /* fifo */ 317*4882a593Smuzhiyun struct dma_pub *di[NFIFO]; /* dma handles, per fifo */ 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun uint unit; /* device instance number */ 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun /* version info */ 322*4882a593Smuzhiyun u16 vendorid; /* PCI vendor id */ 323*4882a593Smuzhiyun u16 deviceid; /* PCI device id */ 324*4882a593Smuzhiyun uint corerev; /* core revision */ 325*4882a593Smuzhiyun u8 sromrev; /* version # of the srom */ 326*4882a593Smuzhiyun u16 boardrev; /* version # of particular board */ 327*4882a593Smuzhiyun u32 boardflags; /* Board specific flags from srom */ 328*4882a593Smuzhiyun u32 boardflags2; /* More board flags if sromrev >= 4 */ 329*4882a593Smuzhiyun u32 machwcap; /* MAC capabilities */ 330*4882a593Smuzhiyun u32 machwcap_backup; /* backup of machwcap */ 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun struct si_pub *sih; /* SI handle (cookie for siutils calls) */ 333*4882a593Smuzhiyun struct bcma_device *d11core; /* pointer to 802.11 core */ 334*4882a593Smuzhiyun struct phy_shim_info *physhim; /* phy shim layer handler */ 335*4882a593Smuzhiyun struct shared_phy *phy_sh; /* pointer to shared phy state */ 336*4882a593Smuzhiyun struct brcms_hw_band *band;/* pointer to active per-band state */ 337*4882a593Smuzhiyun /* band state per phy/radio */ 338*4882a593Smuzhiyun struct brcms_hw_band *bandstate[MAXBANDS]; 339*4882a593Smuzhiyun u16 bmac_phytxant; /* cache of high phytxant state */ 340*4882a593Smuzhiyun bool shortslot; /* currently using 11g ShortSlot timing */ 341*4882a593Smuzhiyun u16 SRL; /* 802.11 dot11ShortRetryLimit */ 342*4882a593Smuzhiyun u16 LRL; /* 802.11 dot11LongRetryLimit */ 343*4882a593Smuzhiyun u16 SFBL; /* Short Frame Rate Fallback Limit */ 344*4882a593Smuzhiyun u16 LFBL; /* Long Frame Rate Fallback Limit */ 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun bool up; /* d11 hardware up and running */ 347*4882a593Smuzhiyun uint now; /* # elapsed seconds */ 348*4882a593Smuzhiyun uint _nbands; /* # bands supported */ 349*4882a593Smuzhiyun u16 chanspec; /* bmac chanspec shadow */ 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun uint *txavail[NFIFO]; /* # tx descriptors available */ 352*4882a593Smuzhiyun const u16 *xmtfifo_sz; /* fifo size in 256B for each xmt fifo */ 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun u32 pllreq; /* pll requests to keep PLL on */ 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun u8 suspended_fifos; /* Which TX fifo to remain awake for */ 357*4882a593Smuzhiyun u32 maccontrol; /* Cached value of maccontrol */ 358*4882a593Smuzhiyun uint mac_suspend_depth; /* current depth of mac_suspend levels */ 359*4882a593Smuzhiyun u32 wake_override; /* bit flags to force MAC to WAKE mode */ 360*4882a593Smuzhiyun u32 mute_override; /* Prevent ucode from sending beacons */ 361*4882a593Smuzhiyun u8 etheraddr[ETH_ALEN]; /* currently configured ethernet address */ 362*4882a593Smuzhiyun bool noreset; /* true= do not reset hw, used by WLC_OUT */ 363*4882a593Smuzhiyun bool forcefastclk; /* true if h/w is forcing to use fast clk */ 364*4882a593Smuzhiyun bool clk; /* core is out of reset and has clock */ 365*4882a593Smuzhiyun bool sbclk; /* sb has clock */ 366*4882a593Smuzhiyun bool phyclk; /* phy is out of reset and has clock */ 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun bool ucode_loaded; /* true after ucode downloaded */ 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun u8 hw_stf_ss_opmode; /* STF single stream operation mode */ 372*4882a593Smuzhiyun u8 antsel_type; /* Type of boardlevel mimo antenna switch-logic 373*4882a593Smuzhiyun * 0 = N/A, 1 = 2x4 board, 2 = 2x3 CB2 board 374*4882a593Smuzhiyun */ 375*4882a593Smuzhiyun u32 antsel_avail; /* 376*4882a593Smuzhiyun * put struct antsel_info here if more info is 377*4882a593Smuzhiyun * needed 378*4882a593Smuzhiyun */ 379*4882a593Smuzhiyun }; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun /* 382*4882a593Smuzhiyun * Principal common driver data structure. 383*4882a593Smuzhiyun * 384*4882a593Smuzhiyun * pub: pointer to driver public state. 385*4882a593Smuzhiyun * wl: pointer to specific private state. 386*4882a593Smuzhiyun * hw: HW related state. 387*4882a593Smuzhiyun * clkreq_override: setting for clkreq for PCIE : Auto, 0, 1. 388*4882a593Smuzhiyun * fastpwrup_dly: time in us needed to bring up d11 fast clock. 389*4882a593Smuzhiyun * macintstatus: bit channel between isr and dpc. 390*4882a593Smuzhiyun * macintmask: sw runtime master macintmask value. 391*4882a593Smuzhiyun * defmacintmask: default "on" macintmask value. 392*4882a593Smuzhiyun * clk: core is out of reset and has clock. 393*4882a593Smuzhiyun * core: pointer to active io core. 394*4882a593Smuzhiyun * band: pointer to active per-band state. 395*4882a593Smuzhiyun * corestate: per-core state (one per hw core). 396*4882a593Smuzhiyun * bandstate: per-band state (one per phy/radio). 397*4882a593Smuzhiyun * qvalid: DirFrmQValid and BcMcFrmQValid. 398*4882a593Smuzhiyun * ampdu: ampdu module handler. 399*4882a593Smuzhiyun * asi: antsel module handler. 400*4882a593Smuzhiyun * cmi: channel manager module handler. 401*4882a593Smuzhiyun * vendorid: PCI vendor id. 402*4882a593Smuzhiyun * deviceid: PCI device id. 403*4882a593Smuzhiyun * ucode_rev: microcode revision. 404*4882a593Smuzhiyun * machwcap: MAC capabilities, BMAC shadow. 405*4882a593Smuzhiyun * perm_etheraddr: original sprom local ethernet address. 406*4882a593Smuzhiyun * bandlocked: disable auto multi-band switching. 407*4882a593Smuzhiyun * bandinit_pending: track band init in auto band. 408*4882a593Smuzhiyun * radio_monitor: radio timer is running. 409*4882a593Smuzhiyun * going_down: down path intermediate variable. 410*4882a593Smuzhiyun * wdtimer: timer for watchdog routine. 411*4882a593Smuzhiyun * radio_timer: timer for hw radio button monitor routine. 412*4882a593Smuzhiyun * monitor: monitor (MPDU sniffing) mode. 413*4882a593Smuzhiyun * bcnmisc_monitor: bcns promisc mode override for monitor. 414*4882a593Smuzhiyun * _rifs: enable per-packet rifs. 415*4882a593Smuzhiyun * bcn_li_bcn: beacon listen interval in # beacons. 416*4882a593Smuzhiyun * bcn_li_dtim: beacon listen interval in # dtims. 417*4882a593Smuzhiyun * WDarmed: watchdog timer is armed. 418*4882a593Smuzhiyun * WDlast: last time wlc_watchdog() was called. 419*4882a593Smuzhiyun * edcf_txop[IEEE80211_NUM_ACS]: current txop for each ac. 420*4882a593Smuzhiyun * wme_retries: per-AC retry limits. 421*4882a593Smuzhiyun * bsscfg: set of BSS configurations, idx 0 is default and always valid. 422*4882a593Smuzhiyun * cfg: the primary bsscfg (can be AP or STA). 423*4882a593Smuzhiyun * modulecb: 424*4882a593Smuzhiyun * mimoft: SIGN or 11N. 425*4882a593Smuzhiyun * cck_40txbw: 11N, cck tx b/w override when in 40MHZ mode. 426*4882a593Smuzhiyun * ofdm_40txbw: 11N, ofdm tx b/w override when in 40MHZ mode. 427*4882a593Smuzhiyun * mimo_40txbw: 11N, mimo tx b/w override when in 40MHZ mode. 428*4882a593Smuzhiyun * default_bss: configured BSS parameters. 429*4882a593Smuzhiyun * mc_fid_counter: BC/MC FIFO frame ID counter. 430*4882a593Smuzhiyun * country_default: saved country for leaving 802.11d auto-country mode. 431*4882a593Smuzhiyun * autocountry_default: initial country for 802.11d auto-country mode. 432*4882a593Smuzhiyun * prb_resp_timeout: do not send prb resp if request older 433*4882a593Smuzhiyun * than this, 0 = disable. 434*4882a593Smuzhiyun * home_chanspec: shared home chanspec. 435*4882a593Smuzhiyun * chanspec: target operational channel. 436*4882a593Smuzhiyun * usr_fragthresh: user configured fragmentation threshold. 437*4882a593Smuzhiyun * fragthresh[NFIFO]: per-fifo fragmentation thresholds. 438*4882a593Smuzhiyun * RTSThresh: 802.11 dot11RTSThreshold. 439*4882a593Smuzhiyun * SRL: 802.11 dot11ShortRetryLimit. 440*4882a593Smuzhiyun * LRL: 802.11 dot11LongRetryLimit. 441*4882a593Smuzhiyun * SFBL: Short Frame Rate Fallback Limit. 442*4882a593Smuzhiyun * LFBL: Long Frame Rate Fallback Limit. 443*4882a593Smuzhiyun * shortslot: currently using 11g ShortSlot timing. 444*4882a593Smuzhiyun * shortslot_override: 11g ShortSlot override. 445*4882a593Smuzhiyun * include_legacy_erp: include Legacy ERP info elt ID 47 as well as g ID 42. 446*4882a593Smuzhiyun * PLCPHdr_override: 802.11b Preamble Type override. 447*4882a593Smuzhiyun * stf: 448*4882a593Smuzhiyun * bcn_rspec: save bcn ratespec purpose. 449*4882a593Smuzhiyun * tempsense_lasttime; 450*4882a593Smuzhiyun * tx_duty_cycle_ofdm: maximum allowed duty cycle for OFDM. 451*4882a593Smuzhiyun * tx_duty_cycle_cck: maximum allowed duty cycle for CCK. 452*4882a593Smuzhiyun * wiphy: 453*4882a593Smuzhiyun * pri_scb: primary Station Control Block 454*4882a593Smuzhiyun */ 455*4882a593Smuzhiyun struct brcms_c_info { 456*4882a593Smuzhiyun struct brcms_pub *pub; 457*4882a593Smuzhiyun struct brcms_info *wl; 458*4882a593Smuzhiyun struct brcms_hardware *hw; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun /* clock */ 461*4882a593Smuzhiyun u16 fastpwrup_dly; 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun /* interrupt */ 464*4882a593Smuzhiyun u32 macintstatus; 465*4882a593Smuzhiyun u32 macintmask; 466*4882a593Smuzhiyun u32 defmacintmask; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun bool clk; 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun /* multiband */ 471*4882a593Smuzhiyun struct brcms_core *core; 472*4882a593Smuzhiyun struct brcms_band *band; 473*4882a593Smuzhiyun struct brcms_core *corestate; 474*4882a593Smuzhiyun struct brcms_band *bandstate[MAXBANDS]; 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun /* packet queue */ 477*4882a593Smuzhiyun uint qvalid; 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun struct ampdu_info *ampdu; 480*4882a593Smuzhiyun struct antsel_info *asi; 481*4882a593Smuzhiyun struct brcms_cm_info *cmi; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun u16 vendorid; 484*4882a593Smuzhiyun u16 deviceid; 485*4882a593Smuzhiyun uint ucode_rev; 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun u8 perm_etheraddr[ETH_ALEN]; 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun bool bandlocked; 490*4882a593Smuzhiyun bool bandinit_pending; 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun bool radio_monitor; 493*4882a593Smuzhiyun bool going_down; 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun bool beacon_template_virgin; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun struct brcms_timer *wdtimer; 498*4882a593Smuzhiyun struct brcms_timer *radio_timer; 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun /* promiscuous */ 501*4882a593Smuzhiyun uint filter_flags; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun /* driver feature */ 504*4882a593Smuzhiyun bool _rifs; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun /* AP-STA synchronization, power save */ 507*4882a593Smuzhiyun u8 bcn_li_bcn; 508*4882a593Smuzhiyun u8 bcn_li_dtim; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun bool WDarmed; 511*4882a593Smuzhiyun u32 WDlast; 512*4882a593Smuzhiyun 513*4882a593Smuzhiyun /* WME */ 514*4882a593Smuzhiyun u16 edcf_txop[IEEE80211_NUM_ACS]; 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun u16 wme_retries[IEEE80211_NUM_ACS]; 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun struct brcms_bss_cfg *bsscfg; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun struct modulecb *modulecb; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun u8 mimoft; 523*4882a593Smuzhiyun s8 cck_40txbw; 524*4882a593Smuzhiyun s8 ofdm_40txbw; 525*4882a593Smuzhiyun s8 mimo_40txbw; 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun struct brcms_bss_info *default_bss; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun u16 mc_fid_counter; 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun char country_default[BRCM_CNTRY_BUF_SZ]; 532*4882a593Smuzhiyun char autocountry_default[BRCM_CNTRY_BUF_SZ]; 533*4882a593Smuzhiyun u16 prb_resp_timeout; 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun u16 home_chanspec; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun /* PHY parameters */ 538*4882a593Smuzhiyun u16 chanspec; 539*4882a593Smuzhiyun u16 usr_fragthresh; 540*4882a593Smuzhiyun u16 fragthresh[NFIFO]; 541*4882a593Smuzhiyun u16 RTSThresh; 542*4882a593Smuzhiyun u16 SRL; 543*4882a593Smuzhiyun u16 LRL; 544*4882a593Smuzhiyun u16 SFBL; 545*4882a593Smuzhiyun u16 LFBL; 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun /* network config */ 548*4882a593Smuzhiyun bool shortslot; 549*4882a593Smuzhiyun s8 shortslot_override; 550*4882a593Smuzhiyun bool include_legacy_erp; 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun struct brcms_protection *protection; 553*4882a593Smuzhiyun s8 PLCPHdr_override; 554*4882a593Smuzhiyun 555*4882a593Smuzhiyun struct brcms_stf *stf; 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun u32 bcn_rspec; 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun uint tempsense_lasttime; 560*4882a593Smuzhiyun 561*4882a593Smuzhiyun u16 tx_duty_cycle_ofdm; 562*4882a593Smuzhiyun u16 tx_duty_cycle_cck; 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun struct wiphy *wiphy; 565*4882a593Smuzhiyun struct scb pri_scb; 566*4882a593Smuzhiyun struct ieee80211_vif *vif; 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun struct sk_buff *beacon; 569*4882a593Smuzhiyun u16 beacon_tim_offset; 570*4882a593Smuzhiyun u16 beacon_dtim_period; 571*4882a593Smuzhiyun struct sk_buff *probe_resp; 572*4882a593Smuzhiyun }; 573*4882a593Smuzhiyun 574*4882a593Smuzhiyun /* antsel module specific state */ 575*4882a593Smuzhiyun struct antsel_info { 576*4882a593Smuzhiyun struct brcms_c_info *wlc; /* pointer to main wlc structure */ 577*4882a593Smuzhiyun struct brcms_pub *pub; /* pointer to public fn */ 578*4882a593Smuzhiyun u8 antsel_type; /* Type of boardlevel mimo antenna switch-logic 579*4882a593Smuzhiyun * 0 = N/A, 1 = 2x4 board, 2 = 2x3 CB2 board 580*4882a593Smuzhiyun */ 581*4882a593Smuzhiyun u8 antsel_antswitch; /* board level antenna switch type */ 582*4882a593Smuzhiyun bool antsel_avail; /* Ant selection availability (SROM based) */ 583*4882a593Smuzhiyun struct brcms_antselcfg antcfg_11n; /* antenna configuration */ 584*4882a593Smuzhiyun struct brcms_antselcfg antcfg_cur; /* current antenna config (auto) */ 585*4882a593Smuzhiyun }; 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun enum brcms_bss_type { 588*4882a593Smuzhiyun BRCMS_TYPE_STATION, 589*4882a593Smuzhiyun BRCMS_TYPE_AP, 590*4882a593Smuzhiyun BRCMS_TYPE_ADHOC, 591*4882a593Smuzhiyun }; 592*4882a593Smuzhiyun 593*4882a593Smuzhiyun /* 594*4882a593Smuzhiyun * BSS configuration state 595*4882a593Smuzhiyun * 596*4882a593Smuzhiyun * wlc: wlc to which this bsscfg belongs to. 597*4882a593Smuzhiyun * type: interface type 598*4882a593Smuzhiyun * SSID_len: the length of SSID 599*4882a593Smuzhiyun * SSID: SSID string 600*4882a593Smuzhiyun * 601*4882a593Smuzhiyun * 602*4882a593Smuzhiyun * BSSID: BSSID (associated) 603*4882a593Smuzhiyun * cur_etheraddr: h/w address 604*4882a593Smuzhiyun * flags: BSSCFG flags; see below 605*4882a593Smuzhiyun * 606*4882a593Smuzhiyun * current_bss: BSS parms in ASSOCIATED state 607*4882a593Smuzhiyun * 608*4882a593Smuzhiyun * 609*4882a593Smuzhiyun * ID: 'unique' ID of this bsscfg, assigned at bsscfg allocation 610*4882a593Smuzhiyun */ 611*4882a593Smuzhiyun struct brcms_bss_cfg { 612*4882a593Smuzhiyun struct brcms_c_info *wlc; 613*4882a593Smuzhiyun enum brcms_bss_type type; 614*4882a593Smuzhiyun u8 SSID_len; 615*4882a593Smuzhiyun u8 SSID[IEEE80211_MAX_SSID_LEN]; 616*4882a593Smuzhiyun u8 BSSID[ETH_ALEN]; 617*4882a593Smuzhiyun struct brcms_bss_info *current_bss; 618*4882a593Smuzhiyun }; 619*4882a593Smuzhiyun 620*4882a593Smuzhiyun int brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p); 621*4882a593Smuzhiyun int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo, 622*4882a593Smuzhiyun uint *blocks); 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config); 625*4882a593Smuzhiyun void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags); 626*4882a593Smuzhiyun u16 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec, uint mac_len); 627*4882a593Smuzhiyun u32 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec, 628*4882a593Smuzhiyun bool use_rspec, u16 mimo_ctlchbw); 629*4882a593Smuzhiyun u16 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only, 630*4882a593Smuzhiyun u32 rts_rate, u32 frame_rate, 631*4882a593Smuzhiyun u8 rts_preamble_type, u8 frame_preamble_type, 632*4882a593Smuzhiyun uint frame_len, bool ba); 633*4882a593Smuzhiyun void brcms_c_inval_dma_pkts(struct brcms_hardware *hw, 634*4882a593Smuzhiyun struct ieee80211_sta *sta, void (*dma_callback_fn)); 635*4882a593Smuzhiyun void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend); 636*4882a593Smuzhiyun int brcms_c_set_nmode(struct brcms_c_info *wlc); 637*4882a593Smuzhiyun void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc, u32 bcn_rate); 638*4882a593Smuzhiyun void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type); 639*4882a593Smuzhiyun void brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec, 640*4882a593Smuzhiyun bool mute, struct txpwr_limits *txpwr); 641*4882a593Smuzhiyun void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v); 642*4882a593Smuzhiyun u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset); 643*4882a593Smuzhiyun void brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val, 644*4882a593Smuzhiyun int bands); 645*4882a593Smuzhiyun void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags); 646*4882a593Smuzhiyun void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val); 647*4882a593Smuzhiyun void brcms_b_phy_reset(struct brcms_hardware *wlc_hw); 648*4882a593Smuzhiyun void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw); 649*4882a593Smuzhiyun void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw); 650*4882a593Smuzhiyun void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw, 651*4882a593Smuzhiyun u32 override_bit); 652*4882a593Smuzhiyun void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw, 653*4882a593Smuzhiyun u32 override_bit); 654*4882a593Smuzhiyun void brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, 655*4882a593Smuzhiyun int len, void *buf); 656*4882a593Smuzhiyun u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate); 657*4882a593Smuzhiyun void brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset, 658*4882a593Smuzhiyun const void *buf, int len, u32 sel); 659*4882a593Smuzhiyun void brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, 660*4882a593Smuzhiyun void *buf, int len, u32 sel); 661*4882a593Smuzhiyun void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode); 662*4882a593Smuzhiyun u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw); 663*4882a593Smuzhiyun void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk); 664*4882a593Smuzhiyun void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk); 665*4882a593Smuzhiyun void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on); 666*4882a593Smuzhiyun void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant); 667*4882a593Smuzhiyun void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode); 668*4882a593Smuzhiyun void brcms_c_init_scb(struct scb *scb); 669*4882a593Smuzhiyun 670*4882a593Smuzhiyun #endif /* _BRCM_MAIN_H_ */ 671