1 /* 2 * BCM43XX PCIE core hardware definitions. 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: pcie_core.h 698652 2017-05-10 10:39:24Z $ 30 */ 31 #ifndef _PCIE_CORE_H 32 #define _PCIE_CORE_H 33 34 #include <sbhnddma.h> 35 #include <siutils.h> 36 37 #define REV_GE_64(rev) (rev >= 64) 38 39 /* cpp contortions to concatenate w/arg prescan */ 40 #ifndef PAD 41 #define _PADLINE(line) pad ## line 42 #define _XSTR(line) _PADLINE(line) 43 #define PAD _XSTR(__LINE__) 44 #endif // endif 45 46 /* PCIE Enumeration space offsets */ 47 #define PCIE_CORE_CONFIG_OFFSET 0x0 48 #define PCIE_FUNC0_CONFIG_OFFSET 0x400 49 #define PCIE_FUNC1_CONFIG_OFFSET 0x500 50 #define PCIE_FUNC2_CONFIG_OFFSET 0x600 51 #define PCIE_FUNC3_CONFIG_OFFSET 0x700 52 #define PCIE_SPROM_SHADOW_OFFSET 0x800 53 #define PCIE_SBCONFIG_OFFSET 0xE00 54 55 #define PCIEDEV_MAX_DMAS 4 56 57 /* PCIE Bar0 Address Mapping. Each function maps 16KB config space */ 58 #define PCIE_DEV_BAR0_SIZE 0x4000 59 #define PCIE_BAR0_WINMAPCORE_OFFSET 0x0 60 #define PCIE_BAR0_EXTSPROM_OFFSET 0x1000 61 #define PCIE_BAR0_PCIECORE_OFFSET 0x2000 62 #define PCIE_BAR0_CCCOREREG_OFFSET 0x3000 63 64 /* different register spaces to access thr'u pcie indirect access */ 65 #define PCIE_CONFIGREGS 1 /* Access to config space */ 66 #define PCIE_PCIEREGS 2 /* Access to pcie registers */ 67 68 #define PCIEDEV_HOSTADDR_MAP_BASE 0x8000000 69 #define PCIEDEV_HOSTADDR_MAP_WIN_MASK 0xFC000000 70 71 /* dma regs to control the flow between host2dev and dev2host */ 72 typedef volatile struct pcie_devdmaregs { 73 dma64regs_t tx; 74 uint32 PAD[2]; 75 dma64regs_t rx; 76 uint32 PAD[2]; 77 } pcie_devdmaregs_t; 78 79 #define PCIE_DB_HOST2DEV_0 0x1 80 #define PCIE_DB_HOST2DEV_1 0x2 81 #define PCIE_DB_DEV2HOST_0 0x3 82 #define PCIE_DB_DEV2HOST_1 0x4 83 84 /* door bell register sets */ 85 typedef struct pcie_doorbell { 86 uint32 host2dev_0; 87 uint32 host2dev_1; 88 uint32 dev2host_0; 89 uint32 dev2host_1; 90 } pcie_doorbell_t; 91 92 /* Flow Ring Manager */ 93 #define IFRM_FR_IDX_MAX 256 94 #define IFRM_FR_GID_MAX 4 95 #define IFRM_FR_DEV_MAX 8 96 #define IFRM_FR_TID_MAX 8 97 #define IFRM_FR_DEV_VALID 2 98 99 #define IFRM_VEC_REG_BITS 32 100 101 #define IFRM_FR_PER_VECREG 4 102 #define IFRM_FR_PER_VECREG_SHIFT 2 103 #define IFRM_FR_PER_VECREG_MASK ((0x1 << IFRM_FR_PER_VECREG_SHIFT) - 1) 104 105 #define IFRM_VEC_BITS_PER_FR (IFRM_VEC_REG_BITS/IFRM_FR_PER_VECREG) 106 107 /* IFRM_DEV_0 : d11AC, IFRM_DEV_1 : d11AD */ 108 #define IFRM_DEV_0 0 109 #define IFRM_DEV_1 1 110 111 #define IFRM_FR_GID_0 0 112 #define IFRM_FR_GID_1 1 113 #define IFRM_FR_GID_2 2 114 #define IFRM_FR_GID_3 3 115 116 #define IFRM_TIDMASK 0xffffffff 117 118 /* ifrm_ctrlst register */ 119 #define IFRM_EN (1<<0) 120 #define IFRM_BUFF_INIT_DONE (1<<1) 121 #define IFRM_COMPARE_EN0 (1<<4) 122 #define IFRM_COMPARE_EN1 (1<<5) 123 #define IFRM_COMPARE_EN2 (1<<6) 124 #define IFRM_COMPARE_EN3 (1<<7) 125 #define IFRM_INIT_DV0 (1<<8) 126 #define IFRM_INIT_DV1 (1<<9) 127 #define IFRM_INIT_DV2 (1<<10) 128 #define IFRM_INIT_DV3 (1<<11) 129 130 /* ifrm_msk_arr.addr, ifrm_tid_arr.addr register */ 131 #define IFRM_ADDR_SHIFT 0 132 #define IFRM_FRG_ID_SHIFT 8 133 134 /* ifrm_vec.diff_lat register */ 135 #define IFRM_DV_LAT (1<<0) 136 #define IFRM_DV_LAT_DONE (1<<1) 137 #define IFRM_SDV_OFFSET_SHIFT 4 138 #define IFRM_SDV_FRGID_SHIFT 8 139 #define IFRM_VECSTAT_MASK 0x3 140 #define IFRM_VEC_MASK 0xff 141 142 /* HMAP Windows */ 143 #define HMAP_MAX_WINDOWS 8 144 145 /* idma frm array */ 146 typedef struct pcie_ifrm_array { 147 uint32 addr; 148 uint32 data; 149 } pcie_ifrm_array_t; 150 151 /* idma frm vector */ 152 typedef struct pcie_ifrm_vector { 153 uint32 diff_lat; 154 uint32 sav_tid; 155 uint32 sav_diff; 156 uint32 PAD[1]; 157 } pcie_ifrm_vector_t; 158 159 /* idma frm interrupt */ 160 typedef struct pcie_ifrm_intr { 161 uint32 intstat; 162 uint32 intmask; 163 } pcie_ifrm_intr_t; 164 165 /* HMAP window register set */ 166 typedef volatile struct pcie_hmapwindow { 167 uint32 baseaddr_lo; /* BaseAddrLower */ 168 uint32 baseaddr_hi; /* BaseAddrUpper */ 169 uint32 windowlength; /* Window Length */ 170 uint32 PAD[1]; 171 } pcie_hmapwindow_t; 172 173 typedef volatile struct pcie_hmapviolation { 174 uint32 hmap_violationaddr_lo; /* violating address lo */ 175 uint32 hmap_violationaddr_hi; /* violating addr hi */ 176 uint32 hmap_violation_info; /* violation info */ 177 uint32 PAD[1]; 178 } pcie_hmapviolation_t; 179 /* SB side: PCIE core and host control registers */ 180 typedef volatile struct sbpcieregs { 181 uint32 control; /* host mode only */ 182 uint32 iocstatus; /* PCIE2: iostatus */ 183 uint32 PAD[1]; 184 uint32 biststatus; /* bist Status: 0x00C */ 185 uint32 gpiosel; /* PCIE gpio sel: 0x010 */ 186 uint32 gpioouten; /* PCIE gpio outen: 0x14 */ 187 uint32 gpioout; /* PCIE gpio out: 0x18 */ 188 uint32 PAD; 189 uint32 intstatus; /* Interrupt status: 0x20 */ 190 uint32 intmask; /* Interrupt mask: 0x24 */ 191 uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */ 192 uint32 obffcontrol; /* PCIE2: 0x2C */ 193 uint32 obffintstatus; /* PCIE2: 0x30 */ 194 uint32 obffdatastatus; /* PCIE2: 0x34 */ 195 uint32 PAD[1]; 196 uint32 ctoctrl; /* PCIE2: 0x3C */ 197 uint32 errlog; /* PCIE2: 0x40 */ 198 uint32 errlogaddr; /* PCIE2: 0x44 */ 199 uint32 mailboxint; /* PCIE2: 0x48 */ 200 uint32 mailboxintmsk; /* PCIE2: 0x4c */ 201 uint32 ltrspacing; /* PCIE2: 0x50 */ 202 uint32 ltrhysteresiscnt; /* PCIE2: 0x54 */ 203 uint32 msivectorassign; /* PCIE2: 0x58 */ 204 uint32 intmask2; /* PCIE2: 0x5C */ 205 uint32 PAD[40]; 206 uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */ 207 uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */ 208 uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */ 209 uint32 sbtopcie0upper; /* sb to pcie translation 0: 0x10C */ 210 uint32 sbtopcie1upper; /* sb to pcie translation 1: 0x110 */ 211 uint32 PAD[3]; 212 213 /* pcie core supports in direct access to config space */ 214 uint32 configaddr; /* pcie config space access: Address field: 0x120 */ 215 uint32 configdata; /* pcie config space access: Data field: 0x124 */ 216 union { 217 struct { 218 /* mdio access to serdes */ 219 uint32 mdiocontrol; /* controls the mdio access: 0x128 */ 220 uint32 mdiodata; /* Data to the mdio access: 0x12c */ 221 /* pcie protocol phy/dllp/tlp register indirect access mechanism */ 222 uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */ 223 uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */ 224 uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */ 225 uint32 PAD[177]; 226 /* 0x400 - 0x7FF, PCIE Cfg Space, note: not used anymore in PcieGen2 */ 227 uint32 pciecfg[4][64]; 228 } pcie1; 229 struct { 230 /* mdio access to serdes */ 231 uint32 mdiocontrol; /* controls the mdio access: 0x128 */ 232 uint32 mdiowrdata; /* write data to mdio 0x12C */ 233 uint32 mdiorddata; /* read data to mdio 0x130 */ 234 uint32 PAD[3]; /* 0x134-0x138-0x13c */ 235 /* door bell registers available from gen2 rev5 onwards */ 236 pcie_doorbell_t dbls[PCIEDEV_MAX_DMAS]; /* 0x140 - 0x17F */ 237 uint32 dataintf; /* 0x180 */ 238 uint32 PAD[1]; /* 0x184 */ 239 uint32 d2h_intrlazy_0; /* 0x188 */ 240 uint32 h2d_intrlazy_0; /* 0x18c */ 241 uint32 h2d_intstat_0; /* 0x190 */ 242 uint32 h2d_intmask_0; /* 0x194 */ 243 uint32 d2h_intstat_0; /* 0x198 */ 244 uint32 d2h_intmask_0; /* 0x19c */ 245 uint32 ltr_state; /* 0x1A0 */ 246 uint32 pwr_int_status; /* 0x1A4 */ 247 uint32 pwr_int_mask; /* 0x1A8 */ 248 uint32 pme_source; /* 0x1AC */ 249 uint32 err_hdr_logreg1; /* 0x1B0 */ 250 uint32 err_hdr_logreg2; /* 0x1B4 */ 251 uint32 err_hdr_logreg3; /* 0x1B8 */ 252 uint32 err_hdr_logreg4; /* 0x1BC */ 253 uint32 err_code_logreg; /* 0x1C0 */ 254 uint32 axi_dbg_ctl; /* 0x1C4 */ 255 uint32 axi_dbg_data0; /* 0x1C8 */ 256 uint32 axi_dbg_data1; /* 0x1CC */ 257 uint32 PAD[4]; /* 0x1D0 - 0x1DF */ 258 uint32 clk_ctl_st; /* 0x1E0 */ 259 uint32 PAD[1]; /* 0x1E4 */ 260 uint32 powerctl; /* 0x1E8 */ 261 uint32 PAD[5]; /* 0x1EC - 0x1FF */ 262 pcie_devdmaregs_t h2d0_dmaregs; /* 0x200 - 0x23c */ 263 pcie_devdmaregs_t d2h0_dmaregs; /* 0x240 - 0x27c */ 264 pcie_devdmaregs_t h2d1_dmaregs; /* 0x280 - 0x2bc */ 265 pcie_devdmaregs_t d2h1_dmaregs; /* 0x2c0 - 0x2fc */ 266 pcie_devdmaregs_t h2d2_dmaregs; /* 0x300 - 0x33c */ 267 pcie_devdmaregs_t d2h2_dmaregs; /* 0x340 - 0x37c */ 268 pcie_devdmaregs_t h2d3_dmaregs; /* 0x380 - 0x3bc */ 269 pcie_devdmaregs_t d2h3_dmaregs; /* 0x3c0 - 0x3fc */ 270 uint32 d2h_intrlazy_1; /* 0x400 */ 271 uint32 h2d_intrlazy_1; /* 0x404 */ 272 uint32 h2d_intstat_1; /* 0x408 */ 273 uint32 h2d_intmask_1; /* 0x40c */ 274 uint32 d2h_intstat_1; /* 0x410 */ 275 uint32 d2h_intmask_1; /* 0x414 */ 276 uint32 PAD[2]; /* 0x418 - 0x41C */ 277 uint32 d2h_intrlazy_2; /* 0x420 */ 278 uint32 h2d_intrlazy_2; /* 0x424 */ 279 uint32 h2d_intstat_2; /* 0x428 */ 280 uint32 h2d_intmask_2; /* 0x42c */ 281 uint32 d2h_intstat_2; /* 0x430 */ 282 uint32 d2h_intmask_2; /* 0x434 */ 283 uint32 PAD[10]; /* 0x438 - 0x45F */ 284 uint32 ifrm_ctrlst; /* 0x460 */ 285 uint32 PAD[1]; /* 0x464 */ 286 pcie_ifrm_array_t ifrm_msk_arr; /* 0x468 - 0x46F */ 287 pcie_ifrm_array_t ifrm_tid_arr[IFRM_FR_DEV_VALID]; 288 /* 0x470 - 0x47F */ 289 pcie_ifrm_vector_t ifrm_vec[IFRM_FR_DEV_MAX]; 290 /* 0x480 - 0x4FF */ 291 pcie_ifrm_intr_t ifrm_intr[IFRM_FR_DEV_MAX]; 292 /* 0x500 - 0x53F */ 293 /* HMAP regs for PCIE corerev >= 24 [0x540 - 0x5DF] */ 294 pcie_hmapwindow_t hmapwindow[HMAP_MAX_WINDOWS]; /* 0x540 - 0x5BF */ 295 pcie_hmapviolation_t hmapviolation; /* 0x5C0 - 0x5CF */ 296 uint32 hmap_window_config; /* 0x5D0 */ 297 uint32 PAD[3]; /* 0x5D4 - 0x5DF */ 298 299 uint32 PAD[8]; /* 0x5E0 - 0x5FF */ 300 uint32 PAD[2][64]; /* 0x600 - 0x7FF */ 301 } pcie2; 302 } u; 303 uint16 sprom[64]; /* SPROM shadow Area : 0x800 - 0x880 */ 304 uint32 PAD[96]; /* 0x880 - 0x9FF */ 305 /* direct memory access (pcie2 rev19 and after) : 0xA00 - 0xAFF */ 306 union { 307 /* corerev < 64 */ 308 struct { 309 uint32 dar_ctrl; /* 0xA00 */ 310 uint32 PAD[7]; /* 0xA04-0xA1F */ 311 uint32 intstatus; /* 0xA20 */ 312 uint32 PAD[1]; /* 0xA24 */ 313 uint32 h2d_db_0_0; /* 0xA28 */ 314 uint32 h2d_db_0_1; /* 0xA2C */ 315 uint32 h2d_db_1_0; /* 0xA30 */ 316 uint32 h2d_db_1_1; /* 0xA34 */ 317 uint32 h2d_db_2_0; /* 0xA38 */ 318 uint32 h2d_db_2_1; /* 0xA3C */ 319 uint32 errlog; /* 0xA40 */ 320 uint32 erraddr; /* 0xA44 */ 321 uint32 mbox_int; /* 0xA48 */ 322 uint32 fis_ctrl; /* 0xA4C */ 323 uint32 PAD[36]; /* 0xA50 - 0xADC */ 324 uint32 clk_ctl_st; /* 0xAE0 */ 325 uint32 PAD[1]; /* 0xAE4 */ 326 uint32 powerctl; /* 0xAE8 */ 327 uint32 PAD[5]; /* 0xAEC-0xAFF */ 328 } dar; 329 /* corerev > = 64 */ 330 struct { 331 uint32 dar_ctrl; /* 0xA00 */ 332 uint32 dar_cap; /* 0xA04 */ 333 uint32 clk_ctl_st; /* 0xA08 */ 334 uint32 powerctl; /* 0xA0C */ 335 uint32 intstatus; /* 0xA10 */ 336 uint32 PAD[3]; /* 0xA14-0xA1F */ 337 uint32 h2d_db_0_0; /* 0xA20 */ 338 uint32 h2d_db_0_1; /* 0xA24 */ 339 uint32 h2d_db_1_0; /* 0xA28 */ 340 uint32 h2d_db_1_1; /* 0xA2C */ 341 uint32 h2d_db_2_0; /* 0xA30 */ 342 uint32 h2d_db_2_1; /* 0xA34 */ 343 uint32 h2d_db_3_0; /* 0xA38 */ 344 uint32 h2d_db_3_1; /* 0xA3C */ 345 uint32 h2d_db_4_0; /* 0xA40 */ 346 uint32 h2d_db_4_1; /* 0xA44 */ 347 uint32 h2d_db_5_0; /* 0xA48 */ 348 uint32 h2d_db_5_1; /* 0xA4C */ 349 uint32 h2d_db_6_0; /* 0xA50 */ 350 uint32 h2d_db_6_1; /* 0xA54 */ 351 uint32 h2d_db_7_0; /* 0xA58 */ 352 uint32 h2d_db_7_1; /* 0xA5C */ 353 uint32 errlog; /* 0xA60 */ 354 uint32 erraddr; /* 0xA64 */ 355 uint32 mbox_int; /* 0xA68 */ 356 uint32 fis_ctrl; /* 0xA6C */ 357 uint32 PAD[4]; /* 0xA70-0xAFF */ 358 uint32 d2h_msg_reg0; /* 0xA80 */ 359 uint32 d2h_msg_reg1; /* 0xA84 */ 360 uint32 PAD[2]; /* 0xA88 - 0xA8C */ 361 uint32 h2d_msg_reg0; /* 0xA90 */ 362 uint32 h2d_msg_reg1; /* 0xA94 */ 363 } dar_64; 364 } u1; 365 uint32 PAD[64]; /* 0xB00-0xBFF */ 366 /* Function Control/Status Registers for corerev >= 64 */ 367 /* 0xC00 - 0xCFF */ 368 struct { 369 uint32 control; /* 0xC00 */ 370 uint32 iostatus; /* 0xC04 */ 371 uint32 capability; /* 0xC08 */ 372 uint32 PAD[1]; /* 0xC0C */ 373 uint32 intstatus; /* 0xC10 */ 374 uint32 intmask; /* 0xC14 */ 375 uint32 pwr_intstatus; /* 0xC18 */ 376 uint32 pwr_intmask; /* 0xC1C */ 377 uint32 msi_vector; /* 0xC20 */ 378 uint32 msi_intmask; /* 0xC24 */ 379 uint32 msi_intstatus; /* 0xC28 */ 380 uint32 msi_pend_cnt; /* 0xC2C */ 381 uint32 mbox_intstatus; /* 0xC30 */ 382 uint32 mbox_intmask; /* 0xC34 */ 383 uint32 ltr_state; /* 0xC38 */ 384 uint32 PAD[1]; /* 0xC3C */ 385 uint32 intr_vector; /* 0xC40 */ 386 uint32 intr_addrlow; /* 0xC44 */ 387 uint32 intr_addrhigh; /* 0xC48 */ 388 uint32 PAD[45]; /* 0xC4C-0xCFF */ 389 } ftn_ctrl; 390 } sbpcieregs_t; 391 392 #define PCIE_CFG_DA_OFFSET 0x400 /* direct access register offset for configuration space */ 393 394 /* PCI control */ 395 #define PCIE_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */ 396 #define PCIE_RST 0x02 /* Value driven out to pin */ 397 #define PCIE_SPERST 0x04 /* SurvivePeRst */ 398 #define PCIE_FORCECFGCLKON_ALP 0x08 399 #define PCIE_DISABLE_L1CLK_GATING 0x10 400 #define PCIE_DLYPERST 0x100 /* Delay PeRst to CoE Core */ 401 #define PCIE_DISSPROMLD 0x200 /* DisableSpromLoadOnPerst */ 402 #define PCIE_WakeModeL2 0x1000 /* Wake on L2 */ 403 #define PCIE_MULTIMSI_EN 0x2000 /* enable multi-vector MSI messages */ 404 #define PCIE_PipeIddqDisable0 0x8000 /* Disable assertion of pcie_pipe_iddq during L1.2 and L2 */ 405 #define PCIE_PipeIddqDisable1 0x10000 /* Disable assertion of pcie_pipe_iddq during L2 */ 406 #define PCIE_EN_MDIO_IN_PERST 0x20000 /* enable access to internal registers when PERST */ 407 #define PCIE_MSI_B2B_EN 0x100000 /* enable back-to-back MSI messages */ 408 #define PCIE_MSI_FIFO_CLEAR 0x200000 /* reset MSI FIFO */ 409 #define PCIE_IDMA_MODE_EN(rev) (REV_GE_64(rev) ? 0x1 : 0x800000) /* implicit M2M DMA mode */ 410 #define PCIE_TL_CLK_DETCT 0x4000000 /* enable TL clk detection */ 411 412 /* Function control (corerev > 64) */ 413 #define PCIE_CPLCA_ENABLE 0x01 414 /* 1: send CPL with CA on BP error, 0: send CPLD with SC and data is FFFF */ 415 #define PCIE_DLY_PERST_TO_COE 0x02 416 /* when set, PERST is holding asserted until sprom-related register updates has completed */ 417 418 #define PCIE_CFGADDR 0x120 /* offsetof(configaddr) */ 419 #define PCIE_CFGDATA 0x124 /* offsetof(configdata) */ 420 #define PCIE_SWPME_FN0 0x10000 421 #define PCIE_SWPME_FN0_SHF 16 422 423 /* Interrupt status/mask */ 424 #define PCIE_INTA 0x01 /* PCIE INTA message is received */ 425 #define PCIE_INTB 0x02 /* PCIE INTB message is received */ 426 #define PCIE_INTFATAL 0x04 /* PCIE INTFATAL message is received */ 427 #define PCIE_INTNFATAL 0x08 /* PCIE INTNONFATAL message is received */ 428 #define PCIE_INTCORR 0x10 /* PCIE INTCORR message is received */ 429 #define PCIE_INTPME 0x20 /* PCIE INTPME message is received */ 430 #define PCIE_PERST 0x40 /* PCIE Reset Interrupt */ 431 432 #define PCIE_INT_MB_FN0_0 0x0100 /* PCIE to SB Mailbox int Fn0.0 is received */ 433 #define PCIE_INT_MB_FN0_1 0x0200 /* PCIE to SB Mailbox int Fn0.1 is received */ 434 #define PCIE_INT_MB_FN1_0 0x0400 /* PCIE to SB Mailbox int Fn1.0 is received */ 435 #define PCIE_INT_MB_FN1_1 0x0800 /* PCIE to SB Mailbox int Fn1.1 is received */ 436 #define PCIE_INT_MB_FN2_0 0x1000 /* PCIE to SB Mailbox int Fn2.0 is received */ 437 #define PCIE_INT_MB_FN2_1 0x2000 /* PCIE to SB Mailbox int Fn2.1 is received */ 438 #define PCIE_INT_MB_FN3_0 0x4000 /* PCIE to SB Mailbox int Fn3.0 is received */ 439 #define PCIE_INT_MB_FN3_1 0x8000 /* PCIE to SB Mailbox int Fn3.1 is received */ 440 441 /* PCIE MSI Vector Assignment register */ 442 #define MSIVEC_MB_0 (0x1 << 1) /* MSI Vector offset for mailbox0 is 2 */ 443 #define MSIVEC_MB_1 (0x1 << 2) /* MSI Vector offset for mailbox1 is 3 */ 444 #define MSIVEC_D2H0_DB0 (0x1 << 3) /* MSI Vector offset for interface0 door bell 0 is 4 */ 445 #define MSIVEC_D2H0_DB1 (0x1 << 4) /* MSI Vector offset for interface0 door bell 1 is 5 */ 446 447 /* PCIE MailboxInt/MailboxIntMask register */ 448 #define PCIE_MB_TOSB_FN0_0 0x0001 /* write to assert PCIEtoSB Mailbox interrupt */ 449 #define PCIE_MB_TOSB_FN0_1 0x0002 450 #define PCIE_MB_TOSB_FN1_0 0x0004 451 #define PCIE_MB_TOSB_FN1_1 0x0008 452 #define PCIE_MB_TOSB_FN2_0 0x0010 453 #define PCIE_MB_TOSB_FN2_1 0x0020 454 #define PCIE_MB_TOSB_FN3_0 0x0040 455 #define PCIE_MB_TOSB_FN3_1 0x0080 456 #define PCIE_MB_TOPCIE_FN0_0 0x0100 /* int status/mask for SBtoPCIE Mailbox interrupts */ 457 #define PCIE_MB_TOPCIE_FN0_1 0x0200 458 #define PCIE_MB_TOPCIE_FN1_0 0x0400 459 #define PCIE_MB_TOPCIE_FN1_1 0x0800 460 #define PCIE_MB_TOPCIE_FN2_0 0x1000 461 #define PCIE_MB_TOPCIE_FN2_1 0x2000 462 #define PCIE_MB_TOPCIE_FN3_0 0x4000 463 #define PCIE_MB_TOPCIE_FN3_1 0x8000 464 465 #define PCIE_MB_TOPCIE_DB0_D2H0(rev) (REV_GE_64(rev) ? 0x0001 : 0x010000) 466 #define PCIE_MB_TOPCIE_DB0_D2H1(rev) (REV_GE_64(rev) ? 0x0002 : 0x020000) 467 #define PCIE_MB_TOPCIE_DB1_D2H0(rev) (REV_GE_64(rev) ? 0x0004 : 0x040000) 468 #define PCIE_MB_TOPCIE_DB1_D2H1(rev) (REV_GE_64(rev) ? 0x0008 : 0x080000) 469 #define PCIE_MB_TOPCIE_DB2_D2H0(rev) (REV_GE_64(rev) ? 0x0010 : 0x100000) 470 #define PCIE_MB_TOPCIE_DB2_D2H1(rev) (REV_GE_64(rev) ? 0x0020 : 0x200000) 471 #define PCIE_MB_TOPCIE_DB3_D2H0(rev) (REV_GE_64(rev) ? 0x0040 : 0x400000) 472 #define PCIE_MB_TOPCIE_DB3_D2H1(rev) (REV_GE_64(rev) ? 0x0080 : 0x800000) 473 #define PCIE_MB_TOPCIE_DB4_D2H0(rev) (REV_GE_64(rev) ? 0x0100 : 0x0) 474 #define PCIE_MB_TOPCIE_DB4_D2H1(rev) (REV_GE_64(rev) ? 0x0200 : 0x0) 475 #define PCIE_MB_TOPCIE_DB5_D2H0(rev) (REV_GE_64(rev) ? 0x0400 : 0x0) 476 #define PCIE_MB_TOPCIE_DB5_D2H1(rev) (REV_GE_64(rev) ? 0x0800 : 0x0) 477 #define PCIE_MB_TOPCIE_DB6_D2H0(rev) (REV_GE_64(rev) ? 0x1000 : 0x0) 478 #define PCIE_MB_TOPCIE_DB6_D2H1(rev) (REV_GE_64(rev) ? 0x2000 : 0x0) 479 #define PCIE_MB_TOPCIE_DB7_D2H0(rev) (REV_GE_64(rev) ? 0x4000 : 0x0) 480 #define PCIE_MB_TOPCIE_DB7_D2H1(rev) (REV_GE_64(rev) ? 0x8000 : 0x0) 481 482 #define PCIE_MB_D2H_MB_MASK(rev) \ 483 (PCIE_MB_TOPCIE_DB0_D2H0(rev) | PCIE_MB_TOPCIE_DB0_D2H1(rev) | \ 484 PCIE_MB_TOPCIE_DB1_D2H0(rev) | PCIE_MB_TOPCIE_DB1_D2H1(rev) | \ 485 PCIE_MB_TOPCIE_DB2_D2H0(rev) | PCIE_MB_TOPCIE_DB2_D2H1(rev) | \ 486 PCIE_MB_TOPCIE_DB3_D2H0(rev) | PCIE_MB_TOPCIE_DB3_D2H1(rev) | \ 487 PCIE_MB_TOPCIE_DB4_D2H0(rev) | PCIE_MB_TOPCIE_DB4_D2H1(rev) | \ 488 PCIE_MB_TOPCIE_DB5_D2H0(rev) | PCIE_MB_TOPCIE_DB5_D2H1(rev) | \ 489 PCIE_MB_TOPCIE_DB6_D2H0(rev) | PCIE_MB_TOPCIE_DB6_D2H1(rev) | \ 490 PCIE_MB_TOPCIE_DB7_D2H0(rev) | PCIE_MB_TOPCIE_DB7_D2H1(rev)) 491 492 #define SBTOPCIE0_BASE 0x08000000 493 #define SBTOPCIE1_BASE 0x0c000000 494 495 /* On chips with CCI-400, the small pcie 128 MB region base has shifted */ 496 #define CCI400_SBTOPCIE0_BASE 0x20000000 497 #define CCI400_SBTOPCIE1_BASE 0x24000000 498 499 /* SB to PCIE translation masks */ 500 #define SBTOPCIE0_MASK 0xfc000000 501 #define SBTOPCIE1_MASK 0xfc000000 502 #define SBTOPCIE2_MASK 0xc0000000 503 504 /* Access type bits (0:1) */ 505 #define SBTOPCIE_MEM 0 506 #define SBTOPCIE_IO 1 507 #define SBTOPCIE_CFG0 2 508 #define SBTOPCIE_CFG1 3 509 510 /* Prefetch enable bit 2 */ 511 #define SBTOPCIE_PF 4 512 513 /* Write Burst enable for memory write bit 3 */ 514 #define SBTOPCIE_WR_BURST 8 515 516 /* config access */ 517 #define CONFIGADDR_FUNC_MASK 0x7000 518 #define CONFIGADDR_FUNC_SHF 12 519 #define CONFIGADDR_REG_MASK 0x0FFF 520 #define CONFIGADDR_REG_SHF 0 521 522 #define PCIE_CONFIG_INDADDR(f, r) ((((f) & CONFIGADDR_FUNC_MASK) << CONFIGADDR_FUNC_SHF) | \ 523 (((r) & CONFIGADDR_REG_MASK) << CONFIGADDR_REG_SHF)) 524 525 /* PCIE protocol regs Indirect Address */ 526 #define PCIEADDR_PROT_MASK 0x300 527 #define PCIEADDR_PROT_SHF 8 528 #define PCIEADDR_PL_TLP 0 529 #define PCIEADDR_PL_DLLP 1 530 #define PCIEADDR_PL_PLP 2 531 532 #define PCIE_CORE_REG_CONTROL 0x00u /* Control */ 533 #define PCIE_CORE_REG_IOSTATUS 0x04u /* IO status */ 534 #define PCIE_CORE_REG_BITSTATUS 0x0Cu /* bitstatus */ 535 #define PCIE_CORE_REG_GPIO_SEL 0x10u /* gpio sel */ 536 #define PCIE_CORE_REG_GPIO_OUT_EN 0x14u /* gpio out en */ 537 #define PCIE_CORE_REG_INT_STATUS 0x20u /* int status */ 538 #define PCIE_CORE_REG_INT_MASK 0x24u /* int mask */ 539 #define PCIE_CORE_REG_SB_PCIE_MB 0x28u /* sbpcie mb */ 540 #define PCIE_CORE_REG_ERRLOG 0x40u /* errlog */ 541 #define PCIE_CORE_REG_ERR_ADDR 0x44u /* errlog addr */ 542 #define PCIE_CORE_REG_MB_INTR 0x48u /* MB intr */ 543 #define PCIE_CORE_REG_SB_PCIE_0 0x100u /* sbpcie0 map */ 544 #define PCIE_CORE_REG_SB_PCIE_1 0x104u /* sbpcie1 map */ 545 #define PCIE_CORE_REG_SB_PCIE_2 0x108u /* sbpcie2 map */ 546 547 /* PCIE Config registers */ 548 #define PCIE_CFG_DEV_STS_CTRL_2 0x0d4u /* "dev_sts_control_2 */ 549 #define PCIE_CFG_ADV_ERR_CAP 0x100u /* adv_err_cap */ 550 #define PCIE_CFG_UC_ERR_STS 0x104u /* uc_err_status */ 551 #define PCIE_CFG_UC_ERR_MASK 0x108u /* ucorr_err_mask */ 552 #define PCIE_CFG_UNCOR_ERR_SERV 0x10cu /* ucorr_err_sevr */ 553 #define PCIE_CFG_CORR_ERR_STS 0x110u /* corr_err_status */ 554 #define PCIE_CFG_CORR_ERR_MASK 0x114u /* corr_err_mask */ 555 #define PCIE_CFG_ADV_ERR_CTRL 0x118u /* adv_err_cap_control */ 556 #define PCIE_CFG_HDR_LOG1 0x11Cu /* header_log1 */ 557 #define PCIE_CFG_HDR_LOG2 0x120u /* header_log2 */ 558 #define PCIE_CFG_HDR_LOG3 0x124u /* header_log3 */ 559 #define PCIE_CFG_HDR_LOG4 0x128u /* header_log4 */ 560 #define PCIE_CFG_PML1_SUB_CAP_ID 0x240u /* PML1sub_capID */ 561 #define PCIE_CFG_PML1_SUB_CAP_REG 0x244u /* PML1_sub_Cap_reg */ 562 #define PCIE_CFG_PML1_SUB_CTRL1 0x248u /* PML1_sub_control1 */ 563 #define PCIE_CFG_PML1_SUB_CTRL3 0x24Cu /* PML1_sub_control2 */ 564 #define PCIE_CFG_TL_CTRL_5 0x814u /* tl_control_5 */ 565 #define PCIE_CFG_PHY_ERR_ATT_VEC 0x1820u /* phy_err_attn_vec */ 566 #define PCIE_CFG_PHY_ERR_ATT_MASK 0x1824u /* phy_err_attn_mask */ 567 568 /* PCIE protocol PHY diagnostic registers */ 569 #define PCIE_PLP_MODEREG 0x200u /* Mode */ 570 #define PCIE_PLP_STATUSREG 0x204u /* Status */ 571 #define PCIE_PLP_LTSSMCTRLREG 0x208u /* LTSSM control */ 572 #define PCIE_PLP_LTLINKNUMREG 0x20cu /* Link Training Link number */ 573 #define PCIE_PLP_LTLANENUMREG 0x210u /* Link Training Lane number */ 574 #define PCIE_PLP_LTNFTSREG 0x214u /* Link Training N_FTS */ 575 #define PCIE_PLP_ATTNREG 0x218u /* Attention */ 576 #define PCIE_PLP_ATTNMASKREG 0x21Cu /* Attention Mask */ 577 #define PCIE_PLP_RXERRCTR 0x220u /* Rx Error */ 578 #define PCIE_PLP_RXFRMERRCTR 0x224u /* Rx Framing Error */ 579 #define PCIE_PLP_RXERRTHRESHREG 0x228u /* Rx Error threshold */ 580 #define PCIE_PLP_TESTCTRLREG 0x22Cu /* Test Control reg */ 581 #define PCIE_PLP_SERDESCTRLOVRDREG 0x230u /* SERDES Control Override */ 582 #define PCIE_PLP_TIMINGOVRDREG 0x234u /* Timing param override */ 583 #define PCIE_PLP_RXTXSMDIAGREG 0x238u /* RXTX State Machine Diag */ 584 #define PCIE_PLP_LTSSMDIAGREG 0x23Cu /* LTSSM State Machine Diag */ 585 586 /* PCIE protocol DLLP diagnostic registers */ 587 #define PCIE_DLLP_LCREG 0x100u /* Link Control */ 588 #define PCIE_DLLP_LSREG 0x104u /* Link Status */ 589 #define PCIE_DLLP_LAREG 0x108u /* Link Attention */ 590 #define PCIE_DLLP_LAMASKREG 0x10Cu /* Link Attention Mask */ 591 #define PCIE_DLLP_NEXTTXSEQNUMREG 0x110u /* Next Tx Seq Num */ 592 #define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114u /* Acked Tx Seq Num */ 593 #define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118u /* Purged Tx Seq Num */ 594 #define PCIE_DLLP_RXSEQNUMREG 0x11Cu /* Rx Sequence Number */ 595 #define PCIE_DLLP_LRREG 0x120u /* Link Replay */ 596 #define PCIE_DLLP_LACKTOREG 0x124u /* Link Ack Timeout */ 597 #define PCIE_DLLP_PMTHRESHREG 0x128u /* Power Management Threshold */ 598 #define PCIE_DLLP_RTRYWPREG 0x12Cu /* Retry buffer write ptr */ 599 #define PCIE_DLLP_RTRYRPREG 0x130u /* Retry buffer Read ptr */ 600 #define PCIE_DLLP_RTRYPPREG 0x134u /* Retry buffer Purged ptr */ 601 #define PCIE_DLLP_RTRRWREG 0x138u /* Retry buffer Read/Write */ 602 #define PCIE_DLLP_ECTHRESHREG 0x13Cu /* Error Count Threshold */ 603 #define PCIE_DLLP_TLPERRCTRREG 0x140u /* TLP Error Counter */ 604 #define PCIE_DLLP_ERRCTRREG 0x144u /* Error Counter */ 605 #define PCIE_DLLP_NAKRXCTRREG 0x148u /* NAK Received Counter */ 606 #define PCIE_DLLP_TESTREG 0x14Cu /* Test */ 607 #define PCIE_DLLP_PKTBIST 0x150u /* Packet BIST */ 608 #define PCIE_DLLP_PCIE11 0x154u /* DLLP PCIE 1.1 reg */ 609 610 #define PCIE_DLLP_LSREG_LINKUP (1u << 16u) 611 612 /* PCIE protocol TLP diagnostic registers */ 613 #define PCIE_TLP_CONFIGREG 0x000u /* Configuration */ 614 #define PCIE_TLP_WORKAROUNDSREG 0x004u /* TLP Workarounds */ 615 #define PCIE_TLP_WRDMAUPPER 0x010u /* Write DMA Upper Address */ 616 #define PCIE_TLP_WRDMALOWER 0x014u /* Write DMA Lower Address */ 617 #define PCIE_TLP_WRDMAREQ_LBEREG 0x018u /* Write DMA Len/ByteEn Req */ 618 #define PCIE_TLP_RDDMAUPPER 0x01Cu /* Read DMA Upper Address */ 619 #define PCIE_TLP_RDDMALOWER 0x020u /* Read DMA Lower Address */ 620 #define PCIE_TLP_RDDMALENREG 0x024u /* Read DMA Len Req */ 621 #define PCIE_TLP_MSIDMAUPPER 0x028u /* MSI DMA Upper Address */ 622 #define PCIE_TLP_MSIDMALOWER 0x02Cu /* MSI DMA Lower Address */ 623 #define PCIE_TLP_MSIDMALENREG 0x030u /* MSI DMA Len Req */ 624 #define PCIE_TLP_SLVREQLENREG 0x034u /* Slave Request Len */ 625 #define PCIE_TLP_FCINPUTSREQ 0x038u /* Flow Control Inputs */ 626 #define PCIE_TLP_TXSMGRSREQ 0x03Cu /* Tx StateMachine and Gated Req */ 627 #define PCIE_TLP_ADRACKCNTARBLEN 0x040u /* Address Ack XferCnt and ARB Len */ 628 #define PCIE_TLP_DMACPLHDR0 0x044u /* DMA Completion Hdr 0 */ 629 #define PCIE_TLP_DMACPLHDR1 0x048u /* DMA Completion Hdr 1 */ 630 #define PCIE_TLP_DMACPLHDR2 0x04Cu /* DMA Completion Hdr 2 */ 631 #define PCIE_TLP_DMACPLMISC0 0x050u /* DMA Completion Misc0 */ 632 #define PCIE_TLP_DMACPLMISC1 0x054u /* DMA Completion Misc1 */ 633 #define PCIE_TLP_DMACPLMISC2 0x058u /* DMA Completion Misc2 */ 634 #define PCIE_TLP_SPTCTRLLEN 0x05Cu /* Split Controller Req len */ 635 #define PCIE_TLP_SPTCTRLMSIC0 0x060u /* Split Controller Misc 0 */ 636 #define PCIE_TLP_SPTCTRLMSIC1 0x064u /* Split Controller Misc 1 */ 637 #define PCIE_TLP_BUSDEVFUNC 0x068u /* Bus/Device/Func */ 638 #define PCIE_TLP_RESETCTR 0x06Cu /* Reset Counter */ 639 #define PCIE_TLP_RTRYBUF 0x070u /* Retry Buffer value */ 640 #define PCIE_TLP_TGTDEBUG1 0x074u /* Target Debug Reg1 */ 641 #define PCIE_TLP_TGTDEBUG2 0x078u /* Target Debug Reg2 */ 642 #define PCIE_TLP_TGTDEBUG3 0x07Cu /* Target Debug Reg3 */ 643 #define PCIE_TLP_TGTDEBUG4 0x080u /* Target Debug Reg4 */ 644 645 /* PCIE2 MDIO register offsets */ 646 #define PCIE2_MDIO_CONTROL 0x128 647 #define PCIE2_MDIO_WR_DATA 0x12C 648 #define PCIE2_MDIO_RD_DATA 0x130 649 650 /* MDIO control */ 651 #define MDIOCTL_DIVISOR_MASK 0x7fu /* clock to be used on MDIO */ 652 #define MDIOCTL_DIVISOR_VAL 0x2u 653 #define MDIOCTL_PREAM_EN 0x80u /* Enable preamble sequnce */ 654 #define MDIOCTL_ACCESS_DONE 0x100u /* Tranaction complete */ 655 656 /* MDIO Data */ 657 #define MDIODATA_MASK 0x0000ffff /* data 2 bytes */ 658 #define MDIODATA_TA 0x00020000 /* Turnaround */ 659 #define MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */ 660 #define MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */ 661 #define MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */ 662 #define MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */ 663 #define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */ 664 #define MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */ 665 #define MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */ 666 #define MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */ 667 #define MDIODATA_WRITE 0x10000000 /* write Transaction */ 668 #define MDIODATA_READ 0x20000000 /* Read Transaction */ 669 #define MDIODATA_START 0x40000000 /* start of Transaction */ 670 671 #define MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */ 672 #define MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */ 673 674 /* MDIO control/wrData/rdData register defines for PCIE Gen 2 */ 675 #define MDIOCTL2_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ 676 #define MDIOCTL2_DIVISOR_VAL 0x2 677 #define MDIOCTL2_REGADDR_SHF 8 /* Regaddr shift */ 678 #define MDIOCTL2_REGADDR_MASK 0x00FFFF00 /* Regaddr Mask */ 679 #define MDIOCTL2_DEVADDR_SHF 24 /* Physmedia devaddr shift */ 680 #define MDIOCTL2_DEVADDR_MASK 0x0f000000 /* Physmedia devaddr Mask */ 681 #define MDIOCTL2_SLAVE_BYPASS 0x10000000 /* IP slave bypass */ 682 #define MDIOCTL2_READ 0x20000000 /* IP slave bypass */ 683 684 #define MDIODATA2_DONE 0x80000000u /* rd/wr transaction done */ 685 #define MDIODATA2_MASK 0x7FFFFFFF /* rd/wr transaction data */ 686 #define MDIODATA2_DEVADDR_SHF 4 /* Physmedia devaddr shift */ 687 688 /* MDIO devices (SERDES modules) 689 * unlike old pcie cores (rev < 10), rev10 pcie serde organizes registers into a few blocks. 690 * two layers mapping (blockidx, register offset) is required 691 */ 692 #define MDIO_DEV_IEEE0 0x000 693 #define MDIO_DEV_IEEE1 0x001 694 #define MDIO_DEV_BLK0 0x800 695 #define MDIO_DEV_BLK1 0x801 696 #define MDIO_DEV_BLK2 0x802 697 #define MDIO_DEV_BLK3 0x803 698 #define MDIO_DEV_BLK4 0x804 699 #define MDIO_DEV_TXPLL 0x808 /* TXPLL register block idx */ 700 #define MDIO_DEV_TXCTRL0 0x820 701 #define MDIO_DEV_SERDESID 0x831 702 #define MDIO_DEV_RXCTRL0 0x840 703 704 /* XgxsBlk1_A Register Offsets */ 705 #define BLK1_PWR_MGMT0 0x16 706 #define BLK1_PWR_MGMT1 0x17 707 #define BLK1_PWR_MGMT2 0x18 708 #define BLK1_PWR_MGMT3 0x19 709 #define BLK1_PWR_MGMT4 0x1A 710 711 /* serdes regs (rev < 10) */ 712 #define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */ 713 #define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */ 714 #define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */ 715 /* SERDES RX registers */ 716 #define SERDES_RX_CTRL 1 /* Rx cntrl */ 717 #define SERDES_RX_TIMER1 2 /* Rx Timer1 */ 718 #define SERDES_RX_CDR 6 /* CDR */ 719 #define SERDES_RX_CDRBW 7 /* CDR BW */ 720 721 /* SERDES RX control register */ 722 #define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ 723 #define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */ 724 725 /* SERDES PLL registers */ 726 #define SERDES_PLL_CTRL 1 /* PLL control reg */ 727 #define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ 728 729 /* Power management threshold */ 730 #define PCIE_L0THRESHOLDTIME_MASK 0xFF00u /* bits 0 - 7 */ 731 #define PCIE_L1THRESHOLDTIME_MASK 0xFF00u /* bits 8 - 15 */ 732 #define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */ 733 #define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */ 734 #define PCIE_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */ 735 736 /* SPROM offsets */ 737 #define SRSH_ASPM_OFFSET 4 /* word 4 */ 738 #define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */ 739 #define SRSH_ASPM_L1_ENB 0x10 /* bit 4 */ 740 #define SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */ 741 #define SRSH_PCIE_MISC_CONFIG 5 /* word 5 */ 742 #define SRSH_L23READY_EXIT_NOPERST 0x8000u /* bit 15 */ 743 #define SRSH_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */ 744 #define SRSH_CLKREQ_OFFSET_REV8 52 /* word 52 for srom rev 8 */ 745 #define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */ 746 #define SRSH_BD_OFFSET 6 /* word 6 */ 747 #define SRSH_AUTOINIT_OFFSET 18 /* auto initialization enable */ 748 749 /* PCI Capability ID's 750 * Reference include/linux/pci_regs.h 751 * #define PCI_CAP_LIST_ID 0 // Capability ID 752 * #define PCI_CAP_ID_PM 0x01 // Power Management 753 * #define PCI_CAP_ID_AGP 0x02 // Accelerated Graphics Port 754 * #define PCI_CAP_ID_VPD 0x03 // Vital Product Data 755 * #define PCI_CAP_ID_SLOTID 0x04 // Slot Identification 756 * #define PCI_CAP_ID_MSI 0x05 // Message Signalled Interrupts 757 * #define PCI_CAP_ID_CHSWP 0x06 // CompactPCI HotSwap 758 * #define PCI_CAP_ID_PCIX 0x07 // PCI-X 759 * #define PCI_CAP_ID_HT 0x08 // HyperTransport 760 * #define PCI_CAP_ID_VNDR 0x09 // Vendor-Specific 761 * #define PCI_CAP_ID_DBG 0x0A // Debug port 762 * #define PCI_CAP_ID_CCRC 0x0B // CompactPCI Central Resource Control 763 * #define PCI_CAP_ID_SHPC 0x0C // PCI Standard Hot-Plug Controller 764 * #define PCI_CAP_ID_SSVID 0x0D // Bridge subsystem vendor/device ID 765 * #define PCI_CAP_ID_AGP3 0x0E // AGP Target PCI-PCI bridge 766 * #define PCI_CAP_ID_SECDEV 0x0F // Secure Device 767 * #define PCI_CAP_ID_MSIX 0x11 // MSI-X 768 * #define PCI_CAP_ID_SATA 0x12 // SATA Data/Index Conf. 769 * #define PCI_CAP_ID_AF 0x13 // PCI Advanced Features 770 * #define PCI_CAP_ID_EA 0x14 // PCI Enhanced Allocation 771 * #define PCI_CAP_ID_MAX PCI_CAP_ID_EA 772 */ 773 774 #define PCIE_CAP_ID_EXP 0x10 // PCI Express 775 776 /* PCIe Capabilities Offsets 777 * Reference include/linux/pci_regs.h 778 * #define PCIE_CAP_FLAGS 2 // Capabilities register 779 * #define PCIE_CAP_DEVCAP 4 // Device capabilities 780 * #define PCIE_CAP_DEVCTL 8 // Device Control 781 * #define PCIE_CAP_DEVSTA 10 // Device Status 782 * #define PCIE_CAP_LNKCAP 12 // Link Capabilities 783 * #define PCIE_CAP_LNKCTL 16 // Link Control 784 * #define PCIE_CAP_LNKSTA 18 // Link Status 785 * #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 // v1 endpoints end here 786 * #define PCIE_CAP_SLTCAP 20 // Slot Capabilities 787 * #define PCIE_CAP_SLTCTL 24 // Slot Control 788 * #define PCIE_CAP_SLTSTA 26 // Slot Status 789 * #define PCIE_CAP_RTCTL 28 // Root Control 790 * #define PCIE_CAP_RTCAP 30 // Root Capabilities 791 * #define PCIE_CAP_RTSTA 32 // Root Status 792 */ 793 794 /* Linkcapability reg offset in PCIE Cap */ 795 #define PCIE_CAP_LINKCAP_OFFSET 12 /* linkcap offset in pcie cap */ 796 #define PCIE_CAP_LINKCAP_LNKSPEED_MASK 0xf /* Supported Link Speeds */ 797 #define PCIE_CAP_LINKCAP_GEN2 0x2 /* Value for GEN2 */ 798 799 /* Uc_Err reg offset in AER Cap */ 800 #define PCIE_EXTCAP_ID_ERR 0x01 /* Advanced Error Reporting */ 801 #define PCIE_EXTCAP_AER_UCERR_OFFSET 4 /* Uc_Err reg offset in AER Cap */ 802 #define PCIE_EXTCAP_ERR_HEADER_LOG_0 28 803 #define PCIE_EXTCAP_ERR_HEADER_LOG_1 32 804 #define PCIE_EXTCAP_ERR_HEADER_LOG_2 36 805 #define PCIE_EXTCAP_ERR_HEADER_LOG_3 40 806 807 /* L1SS reg offset in L1SS Ext Cap */ 808 #define PCIE_EXTCAP_ID_L1SS 0x1e /* PCI Express L1 PM Substates Capability */ 809 #define PCIE_EXTCAP_L1SS_CAP_OFFSET 4 /* L1SSCap reg offset in L1SS Cap */ 810 #define PCIE_EXTCAP_L1SS_CONTROL_OFFSET 8 /* L1SSControl reg offset in L1SS Cap */ 811 #define PCIE_EXTCAP_L1SS_CONTROL2_OFFSET 0xc /* L1SSControl reg offset in L1SS Cap */ 812 813 /* Linkcontrol reg offset in PCIE Cap */ 814 #define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */ 815 #define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */ 816 #define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */ 817 #define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */ 818 #define PCIE_LINKSPEED_MASK 0xF0000u /* bits 0 - 3 of high word */ 819 #define PCIE_LINKSPEED_SHIFT 16 /* PCIE_LINKSPEED_SHIFT */ 820 821 /* Devcontrol reg offset in PCIE Cap */ 822 #define PCIE_CAP_DEVCTRL_OFFSET 8 /* devctrl offset in pcie cap */ 823 #define PCIE_CAP_DEVCTRL_MRRS_MASK 0x7000 /* Max read request size mask */ 824 #define PCIE_CAP_DEVCTRL_MRRS_SHIFT 12 /* Max read request size shift */ 825 #define PCIE_CAP_DEVCTRL_MRRS_128B 0 /* 128 Byte */ 826 #define PCIE_CAP_DEVCTRL_MRRS_256B 1 /* 256 Byte */ 827 #define PCIE_CAP_DEVCTRL_MRRS_512B 2 /* 512 Byte */ 828 #define PCIE_CAP_DEVCTRL_MRRS_1024B 3 /* 1024 Byte */ 829 #define PCIE_CAP_DEVCTRL_MPS_MASK 0x00e0 /* Max payload size mask */ 830 #define PCIE_CAP_DEVCTRL_MPS_SHIFT 5 /* Max payload size shift */ 831 #define PCIE_CAP_DEVCTRL_MPS_128B 0 /* 128 Byte */ 832 #define PCIE_CAP_DEVCTRL_MPS_256B 1 /* 256 Byte */ 833 #define PCIE_CAP_DEVCTRL_MPS_512B 2 /* 512 Byte */ 834 #define PCIE_CAP_DEVCTRL_MPS_1024B 3 /* 1024 Byte */ 835 836 #define PCIE_ASPM_CTRL_MASK 3 /* bit 0 and 1 */ 837 #define PCIE_ASPM_ENAB 3 /* ASPM L0s & L1 in linkctrl */ 838 #define PCIE_ASPM_L1_ENAB 2 /* ASPM L0s & L1 in linkctrl */ 839 #define PCIE_ASPM_L0s_ENAB 1 /* ASPM L0s & L1 in linkctrl */ 840 #define PCIE_ASPM_DISAB 0 /* ASPM L0s & L1 in linkctrl */ 841 842 #define PCIE_ASPM_L11_ENAB 8 /* ASPM L1.1 in PML1_sub_control2 */ 843 #define PCIE_ASPM_L12_ENAB 4 /* ASPM L1.2 in PML1_sub_control2 */ 844 845 #define PCIE_EXT_L1SS_MASK 0xf /* Bits [3:0] of L1SSControl 0x248 */ 846 #define PCIE_EXT_L1SS_ENAB 0xf /* Bits [3:0] of L1SSControl 0x248 */ 847 848 /* NumMsg and NumMsgEn in PCIE MSI Cap */ 849 #define MSICAP_NUM_MSG_SHF 17 850 #define MSICAP_NUM_MSG_MASK (0x7 << MSICAP_NUM_MSG_SHF) 851 #define MSICAP_NUM_MSG_EN_SHF 20 852 #define MSICAP_NUM_MSG_EN_MASK (0x7 << MSICAP_NUM_MSG_EN_SHF) 853 854 /* Devcontrol2 reg offset in PCIE Cap */ 855 #define PCIE_CAP_DEVCTRL2_OFFSET 0x28 /* devctrl2 offset in pcie cap */ 856 #define PCIE_CAP_DEVCTRL2_LTR_ENAB_MASK 0x400 /* Latency Tolerance Reporting Enable */ 857 #define PCIE_CAP_DEVCTRL2_OBFF_ENAB_SHIFT 13 /* Enable OBFF mechanism, select signaling method */ 858 #define PCIE_CAP_DEVCTRL2_OBFF_ENAB_MASK 0x6000 /* Enable OBFF mechanism, select signaling method */ 859 860 /* LTR registers in PCIE Cap */ 861 #define PCIE_LTR0_REG_OFFSET 0x844u /* ltr0_reg offset in pcie cap */ 862 #define PCIE_LTR1_REG_OFFSET 0x848u /* ltr1_reg offset in pcie cap */ 863 #define PCIE_LTR2_REG_OFFSET 0x84cu /* ltr2_reg offset in pcie cap */ 864 #define PCIE_LTR0_REG_DEFAULT_60 0x883c883cu /* active latency default to 60usec */ 865 #define PCIE_LTR0_REG_DEFAULT_150 0x88968896u /* active latency default to 150usec */ 866 #define PCIE_LTR1_REG_DEFAULT 0x88648864u /* idle latency default to 100usec */ 867 #define PCIE_LTR2_REG_DEFAULT 0x90039003u /* sleep latency default to 3msec */ 868 #define PCIE_LTR_LAT_VALUE_MASK 0x3FF /* LTR Latency mask */ 869 #define PCIE_LTR_LAT_SCALE_SHIFT 10 /* LTR Scale shift */ 870 #define PCIE_LTR_LAT_SCALE_MASK 0x1C00 /* LTR Scale mask */ 871 #define PCIE_LTR_SNOOP_REQ_SHIFT 15 /* LTR SNOOP REQ shift */ 872 #define PCIE_LTR_SNOOP_REQ_MASK 0x8000 /* LTR SNOOP REQ mask */ 873 874 /* Status reg PCIE_PLP_STATUSREG */ 875 #define PCIE_PLP_POLARITYINV_STAT 0x10 876 877 /* PCIE BRCM Vendor CAP REVID reg bits */ 878 #define BRCMCAP_PCIEREV_CT_MASK 0xF00u 879 #define BRCMCAP_PCIEREV_CT_SHIFT 8u 880 #define BRCMCAP_PCIEREV_REVID_MASK 0xFFu 881 #define BRCMCAP_PCIEREV_REVID_SHIFT 0 882 883 #define PCIE_REVREG_CT_PCIE1 0 884 #define PCIE_REVREG_CT_PCIE2 1 885 886 /* PCIE GEN2 specific defines */ 887 /* PCIE BRCM Vendor Cap offsets w.r.t to vendor cap ptr */ 888 #define PCIE2R0_BRCMCAP_REVID_OFFSET 4 889 #define PCIE2R0_BRCMCAP_BAR0_WIN0_WRAP_OFFSET 8 890 #define PCIE2R0_BRCMCAP_BAR0_WIN2_OFFSET 12 891 #define PCIE2R0_BRCMCAP_BAR0_WIN2_WRAP_OFFSET 16 892 #define PCIE2R0_BRCMCAP_BAR0_WIN_OFFSET 20 893 #define PCIE2R0_BRCMCAP_BAR1_WIN_OFFSET 24 894 #define PCIE2R0_BRCMCAP_SPROM_CTRL_OFFSET 28 895 #define PCIE2R0_BRCMCAP_BAR2_WIN_OFFSET 32 896 #define PCIE2R0_BRCMCAP_INTSTATUS_OFFSET 36 897 #define PCIE2R0_BRCMCAP_INTMASK_OFFSET 40 898 #define PCIE2R0_BRCMCAP_PCIE2SB_MB_OFFSET 44 899 #define PCIE2R0_BRCMCAP_BPADDR_OFFSET 48 900 #define PCIE2R0_BRCMCAP_BPDATA_OFFSET 52 901 #define PCIE2R0_BRCMCAP_CLKCTLSTS_OFFSET 56 902 903 /* definition of configuration space registers of PCIe gen2 904 * http://hwnbu-twiki.sj.broadcom.com/twiki/pub/Mwgroup/CurrentPcieGen2ProgramGuide/pcie_ep.htm 905 */ 906 #define PCIECFGREG_STATUS_CMD 0x4 907 #define PCIECFGREG_PM_CSR 0x4C 908 #define PCIECFGREG_MSI_CAP 0x58 909 #define PCIECFGREG_MSI_ADDR_L 0x5C 910 #define PCIECFGREG_MSI_ADDR_H 0x60 911 #define PCIECFGREG_MSI_DATA 0x64 912 #define PCIECFGREG_REVID 0x6c 913 #define PCIECFGREG_SPROM_CTRL 0x88 914 #define PCIECFGREG_LINK_STATUS_CTRL 0xBCu 915 #define PCIECFGREG_LINK_STATUS_CTRL2 0xDCu 916 #define PCIECFGREG_DEV_STATUS_CTRL 0xB4u 917 #define PCIECFGGEN_DEV_STATUS_CTRL2 0xD4 918 #define PCIECFGREG_RBAR_CTRL 0x228 919 #define PCIECFGREG_PML1_SUB_CTRL1 0x248 920 #define PCIECFGREG_PML1_SUB_CTRL2 0x24C 921 #define PCIECFGREG_REG_BAR2_CONFIG 0x4E0 922 #define PCIECFGREG_REG_BAR3_CONFIG 0x4F4 923 #define PCIECFGREG_PDL_CTRL1 0x1004 924 #define PCIECFGREG_PDL_IDDQ 0x1814 925 #define PCIECFGREG_REG_PHY_CTL7 0x181c 926 #define PCIECFGREG_PHY_DBG_CLKREQ0 0x1E10 927 #define PCIECFGREG_PHY_DBG_CLKREQ1 0x1E14 928 #define PCIECFGREG_PHY_DBG_CLKREQ2 0x1E18 929 #define PCIECFGREG_PHY_DBG_CLKREQ3 0x1E1C 930 #define PCIECFGREG_PHY_LTSSM_HIST_0 0x1CEC 931 #define PCIECFGREG_PHY_LTSSM_HIST_1 0x1CF0 932 #define PCIECFGREG_PHY_LTSSM_HIST_2 0x1CF4 933 #define PCIECFGREG_PHY_LTSSM_HIST_3 0x1CF8 934 #define PCIECFGREG_TREFUP 0x1814 935 #define PCIECFGREG_TREFUP_EXT 0x1818 936 937 /* PCIECFGREG_PML1_SUB_CTRL1 Bit Definition */ 938 #define PCI_PM_L1_2_ENA_MASK 0x00000001 /* PCI-PM L1.2 Enabled */ 939 #define PCI_PM_L1_1_ENA_MASK 0x00000002 /* PCI-PM L1.1 Enabled */ 940 #define ASPM_L1_2_ENA_MASK 0x00000004 /* ASPM L1.2 Enabled */ 941 #define ASPM_L1_1_ENA_MASK 0x00000008 /* ASPM L1.1 Enabled */ 942 943 /* PCIe gen2 mailbox interrupt masks */ 944 #define I_MB 0x3 945 #define I_BIT0 0x1 946 #define I_BIT1 0x2 947 948 /* PCIE gen2 config regs */ 949 #define PCIIntstatus 0x090 950 #define PCIIntmask 0x094 951 #define PCISBMbx 0x98 952 953 /* enumeration Core regs */ 954 #define PCIH2D_MailBox 0x140 955 #define PCIH2D_DB1 0x144 956 #define PCID2H_MailBox 0x148 957 #define PCIH2D_MailBox_1 0x150 /* for dma channel1 */ 958 #define PCIH2D_DB1_1 0x154 959 #define PCID2H_MailBox_1 0x158 960 #define PCIH2D_MailBox_2 0x160 /* for dma channel2 which will be used for Implicit DMA */ 961 #define PCIH2D_DB1_2 0x164 962 #define PCID2H_MailBox_2 0x168 963 #define PCIE_CLK_CTRL 0x1E0 964 #define PCIE_PWR_CTRL 0x1E8 965 966 #define PCIControl(rev) (REV_GE_64(rev) ? 0xC00 : 0x00) 967 /* for corerev < 64 idma_en is in PCIControl regsiter */ 968 #define IDMAControl(rev) (REV_GE_64(rev) ? 0x480 : 0x00) 969 #define PCIMailBoxInt(rev) (REV_GE_64(rev) ? 0xC30 : 0x48) 970 #define PCIMailBoxMask(rev) (REV_GE_64(rev) ? 0xC34 : 0x4C) 971 #define PCIFunctionIntstatus(rev) (REV_GE_64(rev) ? 0xC10 : 0x20) 972 #define PCIFunctionIntmask(rev) (REV_GE_64(rev) ? 0xC14 : 0x24) 973 #define PCIPowerIntstatus(rev) (REV_GE_64(rev) ? 0xC18 : 0x1A4) 974 #define PCIPowerIntmask(rev) (REV_GE_64(rev) ? 0xC1C : 0x1A8) 975 #define PCIDARClkCtl(rev) (REV_GE_64(rev) ? 0xA08 : 0xAE0) 976 #define PCIDARPwrCtl(rev) (REV_GE_64(rev) ? 0xA0C : 0xAE8) 977 #define PCIDARFunctionIntstatus(rev) (REV_GE_64(rev) ? 0xA10 : 0xA20) 978 #define PCIDARH2D_DB0(rev) (REV_GE_64(rev) ? 0xA20 : 0xA28) 979 #define PCIDARErrlog(rev) (REV_GE_64(rev) ? 0xA60 : 0xA40) 980 #define PCIDARErrlog_Addr(rev) (REV_GE_64(rev) ? 0xA64 : 0xA44) 981 #define PCIDARMailboxint(rev) (REV_GE_64(rev) ? 0xA68 : 0xA48) 982 983 #define PCIMSIVecAssign 0x58 984 985 /* HMAP Registers */ 986 /* base of all HMAP window registers */ 987 #define PCI_HMAP_WINDOW_BASE(rev) (REV_GE_64(rev) ? 0x580u : 0x540u) 988 #define PCI_HMAP_VIOLATION_ADDR_L(rev) (REV_GE_64(rev) ? 0x600u : 0x5C0u) 989 #define PCI_HMAP_VIOLATION_ADDR_U(rev) (REV_GE_64(rev) ? 0x604u : 0x5C4u) 990 #define PCI_HMAP_VIOLATION_INFO(rev) (REV_GE_64(rev) ? 0x608u : 0x5C8u) 991 #define PCI_HMAP_WINDOW_CONFIG(rev) (REV_GE_64(rev) ? 0x610u : 0x5D0u) 992 #define PCI_HMAP_NWINDOWS_SHIFT 8 993 #define PCI_HMAP_NWINDOWS_MASK 0x0000ff00 /* bits 8:15 */ 994 995 #define I_F0_B0 (0x1 << 8) /* Mail box interrupt Function 0 interrupt, bit 0 */ 996 #define I_F0_B1 (0x1 << 9) /* Mail box interrupt Function 0 interrupt, bit 1 */ 997 998 #define PCIECFGREG_DEVCONTROL 0xB4 999 #define PCIECFGREG_BASEADDR0 0x10 1000 #define PCIECFGREG_BASEADDR1 0x18 1001 #define PCIECFGREG_SECURE_MODE_SHIFT 31 1002 #define PCIECFGREG_DEVCONTROL_MRRS_SHFT 12 1003 #define PCIECFGREG_DEVCONTROL_MRRS_MASK (0x7 << PCIECFGREG_DEVCONTROL_MRRS_SHFT) 1004 #define PCIECFGREG_DEVCTRL_MPS_SHFT 5 1005 #define PCIECFGREG_DEVCTRL_MPS_MASK (0x7 << PCIECFGREG_DEVCTRL_MPS_SHFT) 1006 #define PCIECFGREG_PM_CSR_STATE_MASK 0x00000003 1007 #define PCIECFGREG_PM_CSR_STATE_D0 0 1008 #define PCIECFGREG_PM_CSR_STATE_D1 1 1009 #define PCIECFGREG_PM_CSR_STATE_D2 2 1010 #define PCIECFGREG_PM_CSR_STATE_D3_HOT 3 1011 #define PCIECFGREG_PM_CSR_STATE_D3_COLD 4 1012 1013 /* Direct Access regs */ 1014 #define DAR_ERRADDR(rev) (REV_GE_64(rev) ? \ 1015 OFFSETOF(sbpcieregs_t, u1.dar_64.erraddr) : \ 1016 OFFSETOF(sbpcieregs_t, u1.dar.erraddr)) 1017 #define DAR_ERRLOG(rev) (REV_GE_64(rev) ? \ 1018 OFFSETOF(sbpcieregs_t, u1.dar_64.errlog) : \ 1019 OFFSETOF(sbpcieregs_t, u1.dar.errlog)) 1020 #define DAR_PCIH2D_DB0_0(rev) (REV_GE_64(rev) ? \ 1021 OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_0_0) : \ 1022 OFFSETOF(sbpcieregs_t, u1.dar.h2d_db_0_0)) 1023 #define DAR_PCIH2D_DB0_1(rev) (REV_GE_64(rev) ? \ 1024 OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_0_1) : \ 1025 OFFSETOF(sbpcieregs_t, u1.dar.h2d_db_0_1)) 1026 #define DAR_PCIH2D_DB1_0(rev) (REV_GE_64(rev) ? \ 1027 OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_1_0) : \ 1028 OFFSETOF(sbpcieregs_t, u1.dar.h2d_db_1_0)) 1029 #define DAR_PCIH2D_DB1_1(rev) (REV_GE_64(rev) ? \ 1030 OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_1_1) : \ 1031 OFFSETOF(sbpcieregs_t, u1.dar.h2d_db_1_1)) 1032 #define DAR_PCIH2D_DB2_0(rev) (REV_GE_64(rev) ? \ 1033 OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_2_0) : \ 1034 OFFSETOF(sbpcieregs_t, u1.dar.h2d_db_2_0)) 1035 #define DAR_PCIH2D_DB2_1(rev) (REV_GE_64(rev) ? \ 1036 OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_2_1) : \ 1037 OFFSETOF(sbpcieregs_t, u1.dar.h2d_db_2_1)) 1038 #define DAR_PCIH2D_DB3_0(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_3_0) 1039 #define DAR_PCIH2D_DB3_1(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_3_1) 1040 #define DAR_PCIH2D_DB4_0(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_4_0) 1041 #define DAR_PCIH2D_DB4_1(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_4_1) 1042 #define DAR_PCIH2D_DB5_0(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_5_0) 1043 #define DAR_PCIH2D_DB5_1(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_5_1) 1044 #define DAR_PCIH2D_DB6_0(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_6_0) 1045 #define DAR_PCIH2D_DB6_1(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_6_1) 1046 #define DAR_PCIH2D_DB7_0(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_7_0) 1047 #define DAR_PCIH2D_DB7_1(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.h2d_db_7_1) 1048 1049 #define DAR_PCIMailBoxInt(rev) (REV_GE_64(rev) ? \ 1050 OFFSETOF(sbpcieregs_t, u1.dar_64.mbox_int) : \ 1051 OFFSETOF(sbpcieregs_t, u1.dar.mbox_int)) 1052 #define DAR_PCIE_PWR_CTRL(rev) (REV_GE_64(rev) ? \ 1053 OFFSETOF(sbpcieregs_t, u1.dar_64.powerctl) : \ 1054 OFFSETOF(sbpcieregs_t, u1.dar.powerctl)) 1055 #define DAR_CLK_CTRL(rev) (REV_GE_64(rev) ? \ 1056 OFFSETOF(sbpcieregs_t, u1.dar_64.clk_ctl_st) : \ 1057 OFFSETOF(sbpcieregs_t, u1.dar.clk_ctl_st)) 1058 #define DAR_INTSTAT(rev) (REV_GE_64(rev) ? \ 1059 OFFSETOF(sbpcieregs_t, u1.dar_64.intstatus) : \ 1060 OFFSETOF(sbpcieregs_t, u1.dar.intstatus)) 1061 1062 #define DAR_FIS_CTRL(rev) OFFSETOF(sbpcieregs_t, u1.dar_64.fis_ctrl) 1063 1064 #define DAR_FIS_START_SHIFT 0u 1065 #define DAR_FIS_START_MASK (1u << DAR_FIS_START_SHIFT) 1066 1067 #define PCIE_PWR_REQ_PCIE (0x1 << 8) 1068 1069 /* SROM hardware region */ 1070 #define SROM_OFFSET_BAR1_CTRL 52 1071 1072 #define BAR1_ENC_SIZE_MASK 0x000e 1073 #define BAR1_ENC_SIZE_SHIFT 1 1074 1075 #define BAR1_ENC_SIZE_1M 0 1076 #define BAR1_ENC_SIZE_2M 1 1077 #define BAR1_ENC_SIZE_4M 2 1078 1079 #define PCIEGEN2_CAP_DEVSTSCTRL2_OFFSET 0xD4 1080 #define PCIEGEN2_CAP_DEVSTSCTRL2_LTRENAB 0x400 1081 1082 /* 1083 * Latency Tolerance Reporting (LTR) states 1084 * Active has the least tolerant latency requirement 1085 * Sleep is most tolerant 1086 */ 1087 #define LTR_ACTIVE 2 1088 #define LTR_ACTIVE_IDLE 1 1089 #define LTR_SLEEP 0 1090 #define LTR_FINAL_MASK 0x300 1091 #define LTR_FINAL_SHIFT 8 1092 1093 /* pwrinstatus, pwrintmask regs */ 1094 #define PCIEGEN2_PWRINT_D0_STATE_SHIFT 0 1095 #define PCIEGEN2_PWRINT_D1_STATE_SHIFT 1 1096 #define PCIEGEN2_PWRINT_D2_STATE_SHIFT 2 1097 #define PCIEGEN2_PWRINT_D3_STATE_SHIFT 3 1098 #define PCIEGEN2_PWRINT_L0_LINK_SHIFT 4 1099 #define PCIEGEN2_PWRINT_L0s_LINK_SHIFT 5 1100 #define PCIEGEN2_PWRINT_L1_LINK_SHIFT 6 1101 #define PCIEGEN2_PWRINT_L2_L3_LINK_SHIFT 7 1102 #define PCIEGEN2_PWRINT_OBFF_CHANGE_SHIFT 8 1103 1104 #define PCIEGEN2_PWRINT_D0_STATE_MASK (1 << PCIEGEN2_PWRINT_D0_STATE_SHIFT) 1105 #define PCIEGEN2_PWRINT_D1_STATE_MASK (1 << PCIEGEN2_PWRINT_D1_STATE_SHIFT) 1106 #define PCIEGEN2_PWRINT_D2_STATE_MASK (1 << PCIEGEN2_PWRINT_D2_STATE_SHIFT) 1107 #define PCIEGEN2_PWRINT_D3_STATE_MASK (1 << PCIEGEN2_PWRINT_D3_STATE_SHIFT) 1108 #define PCIEGEN2_PWRINT_L0_LINK_MASK (1 << PCIEGEN2_PWRINT_L0_LINK_SHIFT) 1109 #define PCIEGEN2_PWRINT_L0s_LINK_MASK (1 << PCIEGEN2_PWRINT_L0s_LINK_SHIFT) 1110 #define PCIEGEN2_PWRINT_L1_LINK_MASK (1 << PCIEGEN2_PWRINT_L1_LINK_SHIFT) 1111 #define PCIEGEN2_PWRINT_L2_L3_LINK_MASK (1 << PCIEGEN2_PWRINT_L2_L3_LINK_SHIFT) 1112 #define PCIEGEN2_PWRINT_OBFF_CHANGE_MASK (1 << PCIEGEN2_PWRINT_OBFF_CHANGE_SHIFT) 1113 1114 /* sbtopcie mail box */ 1115 #define SBTOPCIE_MB_FUNC0_SHIFT 8 1116 #define SBTOPCIE_MB_FUNC1_SHIFT 10 1117 #define SBTOPCIE_MB_FUNC2_SHIFT 12 1118 #define SBTOPCIE_MB_FUNC3_SHIFT 14 1119 1120 #define SBTOPCIE_MB1_FUNC0_SHIFT 9 1121 #define SBTOPCIE_MB1_FUNC1_SHIFT 11 1122 #define SBTOPCIE_MB1_FUNC2_SHIFT 13 1123 #define SBTOPCIE_MB1_FUNC3_SHIFT 15 1124 1125 /* pcieiocstatus */ 1126 #define PCIEGEN2_IOC_D0_STATE_SHIFT 8 1127 #define PCIEGEN2_IOC_D1_STATE_SHIFT 9 1128 #define PCIEGEN2_IOC_D2_STATE_SHIFT 10 1129 #define PCIEGEN2_IOC_D3_STATE_SHIFT 11 1130 #define PCIEGEN2_IOC_L0_LINK_SHIFT 12 1131 #define PCIEGEN2_IOC_L1_LINK_SHIFT 13 1132 #define PCIEGEN2_IOC_L1L2_LINK_SHIFT 14 1133 #define PCIEGEN2_IOC_L2_L3_LINK_SHIFT 15 1134 #define PCIEGEN2_IOC_BME_SHIFT 20 1135 1136 #define PCIEGEN2_IOC_D0_STATE_MASK (1 << PCIEGEN2_IOC_D0_STATE_SHIFT) 1137 #define PCIEGEN2_IOC_D1_STATE_MASK (1 << PCIEGEN2_IOC_D1_STATE_SHIFT) 1138 #define PCIEGEN2_IOC_D2_STATE_MASK (1 << PCIEGEN2_IOC_D2_STATE_SHIFT) 1139 #define PCIEGEN2_IOC_D3_STATE_MASK (1 << PCIEGEN2_IOC_D3_STATE_SHIFT) 1140 #define PCIEGEN2_IOC_L0_LINK_MASK (1 << PCIEGEN2_IOC_L0_LINK_SHIFT) 1141 #define PCIEGEN2_IOC_L1_LINK_MASK (1 << PCIEGEN2_IOC_L1_LINK_SHIFT) 1142 #define PCIEGEN2_IOC_L1L2_LINK_MASK (1 << PCIEGEN2_IOC_L1L2_LINK_SHIFT) 1143 #define PCIEGEN2_IOC_L2_L3_LINK_MASK (1 << PCIEGEN2_IOC_L2_L3_LINK_SHIFT) 1144 #define PCIEGEN2_IOC_BME_MASK (1 << PCIEGEN2_IOC_BME_SHIFT) 1145 1146 /* stat_ctrl */ 1147 #define PCIE_STAT_CTRL_RESET 0x1 1148 #define PCIE_STAT_CTRL_ENABLE 0x2 1149 #define PCIE_STAT_CTRL_INTENABLE 0x4 1150 #define PCIE_STAT_CTRL_INTSTATUS 0x8 1151 1152 /* SPROMControl */ 1153 #define PCIE_BAR1COHERENTACCEN (1 << 8) 1154 #define PCIE_BAR2COHERENTACCEN (1 << 9) 1155 1156 /* cpl_timeout_ctrl_reg */ 1157 #define PCIE_CTO_TO_THRESHOLD_SHIFT 0 1158 #define PCIE_CTO_TO_THRESHHOLD_MASK (0xfffff << PCIE_CTO_TO_THRESHOLD_SHIFT) 1159 1160 #define PCIE_CTO_CLKCHKCNT_SHIFT 24 1161 #define PCIE_CTO_CLKCHKCNT_MASK (0xf << PCIE_CTO_CLKCHKCNT_SHIFT) 1162 1163 #define PCIE_CTO_ENAB_SHIFT 31 1164 #define PCIE_CTO_ENAB_MASK (0x1 << PCIE_CTO_ENAB_SHIFT) 1165 1166 #define PCIE_CTO_TO_THRESH_DEFAULT 0x58000 1167 #define PCIE_CTO_CLKCHKCNT_VAL 0xA 1168 1169 /* ErrLog */ 1170 #define PCIE_SROMRD_ERR_SHIFT 5 1171 #define PCIE_SROMRD_ERR_MASK (0x1 << PCIE_SROMRD_ERR_SHIFT) 1172 1173 #define PCIE_CTO_ERR_SHIFT 8 1174 #define PCIE_CTO_ERR_MASK (0x1 << PCIE_CTO_ERR_SHIFT) 1175 1176 #define PCIE_CTO_ERR_CODE_SHIFT 9 1177 #define PCIE_CTO_ERR_CODE_MASK (0x3 << PCIE_CTO_ERR_CODE_SHIFT) 1178 1179 #define PCIE_BP_CLK_OFF_ERR_SHIFT 12 1180 #define PCIE_BP_CLK_OFF_ERR_MASK (0x1 << PCIE_BP_CLK_OFF_ERR_SHIFT) 1181 1182 #define PCIE_BP_IN_RESET_ERR_SHIFT 13 1183 #define PCIE_BP_IN_RESET_ERR_MASK (0x1 << PCIE_BP_IN_RESET_ERR_SHIFT) 1184 1185 #ifdef BCMDRIVER 1186 void pcie_watchdog_reset(osl_t *osh, si_t *sih, uint32 wd_mask, uint32 wd_val); 1187 void pcie_serdes_iddqdisable(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs); 1188 void pcie_set_trefup_time_100us(si_t *sih); 1189 #endif /* BCMDRIVER */ 1190 1191 /* DMA intstatus and intmask */ 1192 #define I_PC (1 << 10) /* pci descriptor error */ 1193 #define I_PD (1 << 11) /* pci data error */ 1194 #define I_DE (1 << 12) /* descriptor protocol error */ 1195 #define I_RU (1 << 13) /* receive descriptor underflow */ 1196 #define I_RO (1 << 14) /* receive fifo overflow */ 1197 #define I_XU (1 << 15) /* transmit fifo underflow */ 1198 #define I_RI (1 << 16) /* receive interrupt */ 1199 #define I_XI (1 << 24) /* transmit interrupt */ 1200 1201 /* PCIEGen2 message exchange registers */ 1202 /* http://twiki.cypress.com/do/view/Mwgroup/Pciegen2Rev70#Message_Exchange_Registers */ 1203 #define PCIE_DAR_MSG_D2H_REG0_OFFSET 0xA80 1204 #define PCIE_DAR_MSG_H2D_REG0_OFFSET 0xA90 1205 #define PCIE_DAR_MSG_D2H_REG1_OFFSET 0xA84 1206 #define PCIE_DAR_MSG_H2D_REG1_OFFSET 0xA94 1207 1208 #define HS_POLL_PERIOD_US 10 1209 #ifdef BCMQT 1210 #define D2H_READY_WD_RESET_COUNT (84) /* ~84secs >~ BL ready time after wd rst */ 1211 #define D2H_READY_WD_RESET_US 1000000 /* 1s */ 1212 #define D2H_READY_TIMEOUT_US (1000000 * 60 * 3) /* 3 Mins >~ FW download time */ 1213 #define D2H_VALDN_DONE_TIMEOUT_US (1000000 * 60 * 5) /* 5 Mins >~ Validation time */ 1214 #define D2H_TRX_HDR_PARSE_DONE_TIMEOUT_US (1000000 * 60 * 1) /* 1 Mins >~ TRX Parsing */ 1215 #else 1216 #define D2H_READY_WD_RESET_COUNT (200) /* ~200ms >~ BL ready time after wd rst */ 1217 #define D2H_READY_WD_RESET_US 1000 /* 1ms */ 1218 #define D2H_READY_TIMEOUT_US (100000) /* 100ms >~ FW download time */ 1219 #define D2H_VALDN_DONE_TIMEOUT_US (250000) /* 250ms >~ Validation time */ 1220 #define D2H_TRX_HDR_PARSE_DONE_TIMEOUT_US (50000) /* 50ms >~ TRX Parsing */ 1221 #endif // endif 1222 1223 typedef struct bl_hs_address { 1224 volatile void *d2h; 1225 volatile void *h2d; 1226 } hs_addrs_t; 1227 1228 /* [D2H] Dongle to host handshake bits shift */ 1229 enum { 1230 D2H_START_SHIFT = 0, 1231 D2H_READY_SHIFT = 1, 1232 D2H_STEADY_SHIFT = 2, 1233 D2H_TRX_HDR_PARSE_DONE_SHIFT = 3, 1234 D2H_VALDN_START_SHIFT = 4, 1235 D2H_VALDN_RESULT_SHIFT = 5, 1236 D2H_VALDN_DONE_SHIFT = 6 1237 /* Bits 31:7 reserved for future */ 1238 }; 1239 1240 /* [H2D] Host to dongle handshake bits shift */ 1241 enum { 1242 H2D_DL_START_SHIFT = 0, 1243 H2D_DL_DONE_SHIFT = 1, 1244 H2D_DL_NVRAM_DONE_SHIFT = 2, 1245 H2D_BL_RESET_ON_ERROR_SHIFT = 3 1246 /* Bits 31:4 reserved for future */ 1247 }; 1248 #endif /* _PCIE_CORE_H */ 1249