1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2015 Samsung Electronics Co., Ltd.
4*4882a593Smuzhiyun // http://www.samsung.com/
5*4882a593Smuzhiyun //
6*4882a593Smuzhiyun // Exynos - SROM Controller support
7*4882a593Smuzhiyun // Author: Pankaj Dubey <pankaj.dubey@samsung.com>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "exynos-srom.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static const unsigned long exynos_srom_offsets[] = {
20*4882a593Smuzhiyun /* SROM side */
21*4882a593Smuzhiyun EXYNOS_SROM_BW,
22*4882a593Smuzhiyun EXYNOS_SROM_BC0,
23*4882a593Smuzhiyun EXYNOS_SROM_BC1,
24*4882a593Smuzhiyun EXYNOS_SROM_BC2,
25*4882a593Smuzhiyun EXYNOS_SROM_BC3,
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /**
29*4882a593Smuzhiyun * struct exynos_srom_reg_dump: register dump of SROM Controller registers.
30*4882a593Smuzhiyun * @offset: srom register offset from the controller base address.
31*4882a593Smuzhiyun * @value: the value of register under the offset.
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun struct exynos_srom_reg_dump {
34*4882a593Smuzhiyun u32 offset;
35*4882a593Smuzhiyun u32 value;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /**
39*4882a593Smuzhiyun * struct exynos_srom: platform data for exynos srom controller driver.
40*4882a593Smuzhiyun * @dev: platform device pointer
41*4882a593Smuzhiyun * @reg_base: srom base address
42*4882a593Smuzhiyun * @reg_offset: exynos_srom_reg_dump pointer to hold offset and its value.
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun struct exynos_srom {
45*4882a593Smuzhiyun struct device *dev;
46*4882a593Smuzhiyun void __iomem *reg_base;
47*4882a593Smuzhiyun struct exynos_srom_reg_dump *reg_offset;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static struct exynos_srom_reg_dump *
exynos_srom_alloc_reg_dump(const unsigned long * rdump,unsigned long nr_rdump)51*4882a593Smuzhiyun exynos_srom_alloc_reg_dump(const unsigned long *rdump,
52*4882a593Smuzhiyun unsigned long nr_rdump)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct exynos_srom_reg_dump *rd;
55*4882a593Smuzhiyun unsigned int i;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
58*4882a593Smuzhiyun if (!rd)
59*4882a593Smuzhiyun return NULL;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun for (i = 0; i < nr_rdump; ++i)
62*4882a593Smuzhiyun rd[i].offset = rdump[i];
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return rd;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
exynos_srom_configure_bank(struct exynos_srom * srom,struct device_node * np)67*4882a593Smuzhiyun static int exynos_srom_configure_bank(struct exynos_srom *srom,
68*4882a593Smuzhiyun struct device_node *np)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun u32 bank, width, pmc = 0;
71*4882a593Smuzhiyun u32 timing[6];
72*4882a593Smuzhiyun u32 cs, bw;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if (of_property_read_u32(np, "reg", &bank))
75*4882a593Smuzhiyun return -EINVAL;
76*4882a593Smuzhiyun if (of_property_read_u32(np, "reg-io-width", &width))
77*4882a593Smuzhiyun width = 1;
78*4882a593Smuzhiyun if (of_property_read_bool(np, "samsung,srom-page-mode"))
79*4882a593Smuzhiyun pmc = 1 << EXYNOS_SROM_BCX__PMC__SHIFT;
80*4882a593Smuzhiyun if (of_property_read_u32_array(np, "samsung,srom-timing", timing,
81*4882a593Smuzhiyun ARRAY_SIZE(timing)))
82*4882a593Smuzhiyun return -EINVAL;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun bank *= 4; /* Convert bank into shift/offset */
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun cs = 1 << EXYNOS_SROM_BW__BYTEENABLE__SHIFT;
87*4882a593Smuzhiyun if (width == 2)
88*4882a593Smuzhiyun cs |= 1 << EXYNOS_SROM_BW__DATAWIDTH__SHIFT;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun bw = readl_relaxed(srom->reg_base + EXYNOS_SROM_BW);
91*4882a593Smuzhiyun bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank);
92*4882a593Smuzhiyun writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |
95*4882a593Smuzhiyun (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) |
96*4882a593Smuzhiyun (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) |
97*4882a593Smuzhiyun (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) |
98*4882a593Smuzhiyun (timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) |
99*4882a593Smuzhiyun (timing[5] << EXYNOS_SROM_BCX__TACS__SHIFT),
100*4882a593Smuzhiyun srom->reg_base + EXYNOS_SROM_BC0 + bank);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
exynos_srom_probe(struct platform_device * pdev)105*4882a593Smuzhiyun static int exynos_srom_probe(struct platform_device *pdev)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun struct device_node *np, *child;
108*4882a593Smuzhiyun struct exynos_srom *srom;
109*4882a593Smuzhiyun struct device *dev = &pdev->dev;
110*4882a593Smuzhiyun bool bad_bank_config = false;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun np = dev->of_node;
113*4882a593Smuzhiyun if (!np) {
114*4882a593Smuzhiyun dev_err(&pdev->dev, "could not find device info\n");
115*4882a593Smuzhiyun return -EINVAL;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun srom = devm_kzalloc(&pdev->dev,
119*4882a593Smuzhiyun sizeof(struct exynos_srom), GFP_KERNEL);
120*4882a593Smuzhiyun if (!srom)
121*4882a593Smuzhiyun return -ENOMEM;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun srom->dev = dev;
124*4882a593Smuzhiyun srom->reg_base = of_iomap(np, 0);
125*4882a593Smuzhiyun if (!srom->reg_base) {
126*4882a593Smuzhiyun dev_err(&pdev->dev, "iomap of exynos srom controller failed\n");
127*4882a593Smuzhiyun return -ENOMEM;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun platform_set_drvdata(pdev, srom);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets,
133*4882a593Smuzhiyun ARRAY_SIZE(exynos_srom_offsets));
134*4882a593Smuzhiyun if (!srom->reg_offset) {
135*4882a593Smuzhiyun iounmap(srom->reg_base);
136*4882a593Smuzhiyun return -ENOMEM;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun for_each_child_of_node(np, child) {
140*4882a593Smuzhiyun if (exynos_srom_configure_bank(srom, child)) {
141*4882a593Smuzhiyun dev_err(dev,
142*4882a593Smuzhiyun "Could not decode bank configuration for %pOFn\n",
143*4882a593Smuzhiyun child);
144*4882a593Smuzhiyun bad_bank_config = true;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /*
149*4882a593Smuzhiyun * If any bank failed to configure, we still provide suspend/resume,
150*4882a593Smuzhiyun * but do not probe child devices
151*4882a593Smuzhiyun */
152*4882a593Smuzhiyun if (bad_bank_config)
153*4882a593Smuzhiyun return 0;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun return of_platform_populate(np, NULL, NULL, dev);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
exynos_srom_save(void __iomem * base,struct exynos_srom_reg_dump * rd,unsigned int num_regs)159*4882a593Smuzhiyun static void exynos_srom_save(void __iomem *base,
160*4882a593Smuzhiyun struct exynos_srom_reg_dump *rd,
161*4882a593Smuzhiyun unsigned int num_regs)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun for (; num_regs > 0; --num_regs, ++rd)
164*4882a593Smuzhiyun rd->value = readl(base + rd->offset);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
exynos_srom_restore(void __iomem * base,const struct exynos_srom_reg_dump * rd,unsigned int num_regs)167*4882a593Smuzhiyun static void exynos_srom_restore(void __iomem *base,
168*4882a593Smuzhiyun const struct exynos_srom_reg_dump *rd,
169*4882a593Smuzhiyun unsigned int num_regs)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun for (; num_regs > 0; --num_regs, ++rd)
172*4882a593Smuzhiyun writel(rd->value, base + rd->offset);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
exynos_srom_suspend(struct device * dev)175*4882a593Smuzhiyun static int exynos_srom_suspend(struct device *dev)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun struct exynos_srom *srom = dev_get_drvdata(dev);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun exynos_srom_save(srom->reg_base, srom->reg_offset,
180*4882a593Smuzhiyun ARRAY_SIZE(exynos_srom_offsets));
181*4882a593Smuzhiyun return 0;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
exynos_srom_resume(struct device * dev)184*4882a593Smuzhiyun static int exynos_srom_resume(struct device *dev)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun struct exynos_srom *srom = dev_get_drvdata(dev);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun exynos_srom_restore(srom->reg_base, srom->reg_offset,
189*4882a593Smuzhiyun ARRAY_SIZE(exynos_srom_offsets));
190*4882a593Smuzhiyun return 0;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun #endif
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun static const struct of_device_id of_exynos_srom_ids[] = {
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun .compatible = "samsung,exynos4210-srom",
197*4882a593Smuzhiyun },
198*4882a593Smuzhiyun {},
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(exynos_srom_pm_ops, exynos_srom_suspend, exynos_srom_resume);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun static struct platform_driver exynos_srom_driver = {
204*4882a593Smuzhiyun .probe = exynos_srom_probe,
205*4882a593Smuzhiyun .driver = {
206*4882a593Smuzhiyun .name = "exynos-srom",
207*4882a593Smuzhiyun .of_match_table = of_exynos_srom_ids,
208*4882a593Smuzhiyun .pm = &exynos_srom_pm_ops,
209*4882a593Smuzhiyun .suppress_bind_attrs = true,
210*4882a593Smuzhiyun },
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun builtin_platform_driver(exynos_srom_driver);
213