1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 Samsung Electronics 3*4882a593Smuzhiyun * Naveen Krishna Ch <ch.naveen@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Note: This file contains the register description for SROMC 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_SROMC_H_ 11*4882a593Smuzhiyun #define __ASM_ARCH_SROMC_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0)) 14*4882a593Smuzhiyun #define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ 15*4882a593Smuzhiyun /* 1-> Byte base address*/ 16*4882a593Smuzhiyun #define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2)) 17*4882a593Smuzhiyun #define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3)) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define SROMC_BC_TACS(x) (x << 28) /* address set-up */ 20*4882a593Smuzhiyun #define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */ 21*4882a593Smuzhiyun #define SROMC_BC_TACC(x) (x << 16) /* access cycle */ 22*4882a593Smuzhiyun #define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */ 23*4882a593Smuzhiyun #define SROMC_BC_TAH(x) (x << 8) /* address holding time */ 24*4882a593Smuzhiyun #define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */ 25*4882a593Smuzhiyun #define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 28*4882a593Smuzhiyun struct s5p_sromc { 29*4882a593Smuzhiyun unsigned int bw; 30*4882a593Smuzhiyun unsigned int bc[4]; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Configure the Band Width and Bank Control Regs for required SROMC Bank */ 35*4882a593Smuzhiyun void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun enum { 38*4882a593Smuzhiyun FDT_SROM_PMC, 39*4882a593Smuzhiyun FDT_SROM_TACP, 40*4882a593Smuzhiyun FDT_SROM_TAH, 41*4882a593Smuzhiyun FDT_SROM_TCOH, 42*4882a593Smuzhiyun FDT_SROM_TACC, 43*4882a593Smuzhiyun FDT_SROM_TCOS, 44*4882a593Smuzhiyun FDT_SROM_TACS, 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun FDT_SROM_TIMING_COUNT, 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun struct fdt_sromc { 50*4882a593Smuzhiyun u8 bank; /* srom bank number */ 51*4882a593Smuzhiyun u8 width; /* bus width in bytes */ 52*4882a593Smuzhiyun unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */ 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #endif /* __ASM_ARCH_SROMC_H_ */ 56