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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h4 * SPDX-License-Identifier: GPL-2.0+
30 * register. As such, the U-Boot clock driver is currently a bit lazy, and
40 #include <asm/arch/clock-tables.h>
72 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
78 * Read low-level parameters of a PLL.
87 * @returns 0 if ok, -1 on error (invalid clock id)
115 * Reset a peripheral. This puts it in reset, waits for a delay, then takes
116 * it out of reset and waits for th delay again.
118 * @param periph_id peripheral to reset
124 * Put a peripheral into or out of reset.
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/via/
H A Dvia_clock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
30 return ((pll.divisor - 2) << 16) in k800_encode_pll()
32 | (pll.multiplier - 2); in k800_encode_pll()
44 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in cle266_set_primary_pll_encoded()
47 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in cle266_set_primary_pll_encoded()
52 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in k800_set_primary_pll_encoded()
56 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in k800_set_primary_pll_encoded()
[all …]
/OK3568_Linux_fs/kernel/drivers/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-omap1/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP1 reset support
14 /* ARM_SYSST bit shifts related to SoC reset sources */
20 /* Standardized reset source bits (across all OMAP SoCs) */
31 * "Global Software Reset Affects Traffic Controller Frequency". in omap1_restart()
42 * omap1_get_reset_sources - return the source of the SoC's last reset
44 * Returns bits that represent the last reset source for the SoC. The
/OK3568_Linux_fs/kernel/arch/sparc/include/asm/
H A Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
24 #define BBC_PSRC 0x08 /* [W] POR Source */
25 #define BBC_XSRC 0x0c /* [B] XIR Source */
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/mellanox/mlx4/
H A Dreset.c8 * COPYING in the main directory of this source tree, or the
11 * Redistribution and use in source and binary forms, with or
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
44 void __iomem *reset; in mlx4_reset() local
65 * Reset the chip. This is somewhat ugly because we have to in mlx4_reset()
66 * save off the PCI header before reset and then restore it in mlx4_reset()
74 err = -ENOMEM; in mlx4_reset()
79 pcie_cap = pci_pcie_cap(dev->persist->pdev); in mlx4_reset()
84 if (pci_read_config_dword(dev->persist->pdev, i * 4, in mlx4_reset()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/input/
H A Dnvidia,tegra20-kbc.txt7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.txt4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
[all …]
/OK3568_Linux_fs/u-boot/test/py/
H A DREADME.md1 # U-Boot pytest suite
5 This tool aims to test U-Boot by executing U-Boot shell commands using the
6 console interface. A single top-level script exists to execute or attach to the
7 U-Boot console, run the entire script of tests against it, and summarize the
10 - Testing is performed in the same way a user or script would interact with
11 U-Boot; there can be no disconnect.
12 - There is no need to write or embed test-related code into U-Boot itself.
13 It is asserted that writing test-related code in Python is simpler and more
15 - It is reasonably simple to interact with U-Boot in this way.
19 The test suite is implemented using pytest. Interaction with the U-Boot console
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-sc7180.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SC7180
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-sc7180.h
22 const: qcom,gcc-sc7180
26 - description: Board XO source
[all …]
H A Dqcom,gpucc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding
10 - Taniya Das <tdas@codeaurora.org>
17 dt-bindings/clock/qcom,gpucc-sdm845.h
18 dt-bindings/clock/qcom,gpucc-sc7180.h
19 dt-bindings/clock/qcom,gpucc-sm8150.h
20 dt-bindings/clock/qcom,gpucc-sm8250.h
25 - qcom,sdm845-gpucc
[all …]
H A Dqcom,gcc-msm8996.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for MSM8996
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-msm8996.h
22 const: qcom,gcc-msm8996
27 - description: XO source
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H A Dqcom,sdm845-dispcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for SDM845
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,dispcc-sdm845.h.
20 const: qcom,sdm845-dispcc
27 - description: Board XO source
28 - description: GPLL0 source from GCC
[all …]
H A Dsilabs,si5351.txt8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
20 - reg: i2c device address, shall be 0x60 or 0x61.
21 - #clock-cells: from common clock binding; shall be set to 1.
22 - clocks: from common clock binding; list of parent clock
26 - #address-cells: shall be set to 1.
[all …]
H A Dqcom,msm8998-gpucc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,gpucc-msm8998.h.
20 const: qcom,msm8998-gpucc
24 - description: Board XO source
25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
[all …]
H A Dqcom,gcc-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SM8250
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-sm8250.h
22 const: qcom,gcc-sm8250
26 - description: Board XO source
[all …]
H A Dqcom,gcc-sm8150.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SM8150
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-sm8150.h
22 const: qcom,gcc-sm8150
26 - description: Board XO source
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dwm8804.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8804.c -- WM8804 S/PDIF transceiver driver
5 * Copyright 2010-11 Wolfson Microelectronics plc
26 #include <sound/soc-dapm.h>
37 { 3, 0x21 }, /* R3 - PLL1 */
38 { 4, 0xFD }, /* R4 - PLL2 */
39 { 5, 0x36 }, /* R5 - PLL3 */
40 { 6, 0x07 }, /* R6 - PLL4 */
41 { 7, 0x16 }, /* R7 - PLL5 */
42 { 8, 0x18 }, /* R8 - PLL6 */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/
H A Dopen-pic.txt13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
23 interrupt source. The type shall be a <u32> and the value shall be 2.
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
31 - pic-no-reset: The presence of this property indicates that the PIC
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Drockchip-pcie.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Dprm2xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2012 Texas Instruments, Inc.
22 #include "prm-regbits-24xx.h"
25 * OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits -
33 * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
35 * reset source ID bit shifts (which is an OMAP SoC-independent
45 { -1, -1 },
49 * omap2xxx_prm_read_reset_sources - return the last SoC reset source
51 * Return a u32 representing the last reset sources of the SoC. The
52 * returned reset source bits are standardized across OMAP SoCs.
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
21 * 0=Release from reset.
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
25 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
26 * 0=Release from reset. Default 1.
27 * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
28 * 0=Release from reset. Default 1.
[all …]
/OK3568_Linux_fs/yocto/poky/documentation/ref-manual/
H A Ddevtool-reference.rst1 .. SPDX-License-Identifier: CC-BY-SA-2.0-UK
7 The ``devtool`` command-line tool provides a number of features that
14 SDK, see the ":doc:`/sdk-manual/extensible`" chapter in the Yocto
18 .. _devtool-getting-help:
24 has a number of sub-commands for each function. You can run
25 ``devtool --help`` to see all the commands::
27 $ devtool -h
29 …usage: devtool [--basepath BASEPATH] [--bbpath BBPATH] [-d] [-q] [--color COLOR] [-h] <subcommand>…
34 --basepath BASEPATH Base directory of SDK / build directory
35 --bbpath BBPATH Explicitly specify the BBPATH, rather than getting it from the metadata
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/OK3568_Linux_fs/kernel/Documentation/userspace-api/media/v4l/
H A Ddev-encoder.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
6 Memory-to-Memory Stateful Video Encoder Interface
12 further post-processing by the client.
34 5. Single-planar API (see :ref:`planar-apis`) and applicable structures may be
35 used interchangeably with multi-planar API, unless specified otherwise,
47 Refer to :ref:`decoder-glossary`.
52 .. kernel-render:: DOT
62 node [shape = circle, label="Reset"] Reset;
65 qi -> Initialization [ label = "open()" ];
67 Initialization -> Encoding [ label = "Both queues streaming" ];
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dtda1997x.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/v4l2-dv-timings.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-dv-timings.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-fwnode.h>
31 #include <dt-bindings/media/tda1997x.h>
40 MODULE_PARM_DESC(debug, "debug level (0-2)");
46 "OBA", /* One-Bit Audio */
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