1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Global Clock & Reset Controller Binding for MSM8996 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Stephen Boyd <sboyd@kernel.org> 11*4882a593Smuzhiyun - Taniya Das <tdas@codeaurora.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun Qualcomm global clock control module which supports the clocks, resets and 15*4882a593Smuzhiyun power domains on MSM8996. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun See also: 18*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-msm8996.h 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun const: qcom,gcc-msm8996 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun clocks: 25*4882a593Smuzhiyun minItems: 3 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - description: XO source 28*4882a593Smuzhiyun - description: Second XO source 29*4882a593Smuzhiyun - description: Sleep clock source 30*4882a593Smuzhiyun - description: PCIe 0 PIPE clock (optional) 31*4882a593Smuzhiyun - description: PCIe 1 PIPE clock (optional) 32*4882a593Smuzhiyun - description: PCIe 2 PIPE clock (optional) 33*4882a593Smuzhiyun - description: USB3 PIPE clock (optional) 34*4882a593Smuzhiyun - description: UFS RX symbol 0 clock (optional) 35*4882a593Smuzhiyun - description: UFS RX symbol 1 clock (optional) 36*4882a593Smuzhiyun - description: UFS TX symbol 0 clock (optional) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun clock-names: 39*4882a593Smuzhiyun minItems: 3 40*4882a593Smuzhiyun items: 41*4882a593Smuzhiyun - const: cxo 42*4882a593Smuzhiyun - const: cxo2 43*4882a593Smuzhiyun - const: sleep_clk 44*4882a593Smuzhiyun - const: pcie_0_pipe_clk_src 45*4882a593Smuzhiyun - const: pcie_1_pipe_clk_src 46*4882a593Smuzhiyun - const: pcie_2_pipe_clk_src 47*4882a593Smuzhiyun - const: usb3_phy_pipe_clk_src 48*4882a593Smuzhiyun - const: ufs_rx_symbol_0_clk_src 49*4882a593Smuzhiyun - const: ufs_rx_symbol_1_clk_src 50*4882a593Smuzhiyun - const: ufs_tx_symbol_0_clk_src 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun '#clock-cells': 53*4882a593Smuzhiyun const: 1 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun '#reset-cells': 56*4882a593Smuzhiyun const: 1 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun '#power-domain-cells': 59*4882a593Smuzhiyun const: 1 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun reg: 62*4882a593Smuzhiyun maxItems: 1 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun protected-clocks: 65*4882a593Smuzhiyun description: 66*4882a593Smuzhiyun Protected clock specifier list as per common clock binding. 67*4882a593Smuzhiyun 68*4882a593Smuzhiyunrequired: 69*4882a593Smuzhiyun - compatible 70*4882a593Smuzhiyun - reg 71*4882a593Smuzhiyun - '#clock-cells' 72*4882a593Smuzhiyun - '#reset-cells' 73*4882a593Smuzhiyun - '#power-domain-cells' 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunadditionalProperties: false 76*4882a593Smuzhiyun 77*4882a593Smuzhiyunexamples: 78*4882a593Smuzhiyun - | 79*4882a593Smuzhiyun clock-controller@300000 { 80*4882a593Smuzhiyun compatible = "qcom,gcc-msm8996"; 81*4882a593Smuzhiyun #clock-cells = <1>; 82*4882a593Smuzhiyun #reset-cells = <1>; 83*4882a593Smuzhiyun #power-domain-cells = <1>; 84*4882a593Smuzhiyun reg = <0x300000 0x90000>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun... 87