1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Graphics Clock & Reset Controller Binding 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Taniya Das <tdas@codeaurora.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun Qualcomm graphics clock control module which supports the clocks, resets and 14*4882a593Smuzhiyun power domains on SDM845/SC7180/SM8150/SM8250. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun See also: 17*4882a593Smuzhiyun dt-bindings/clock/qcom,gpucc-sdm845.h 18*4882a593Smuzhiyun dt-bindings/clock/qcom,gpucc-sc7180.h 19*4882a593Smuzhiyun dt-bindings/clock/qcom,gpucc-sm8150.h 20*4882a593Smuzhiyun dt-bindings/clock/qcom,gpucc-sm8250.h 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunproperties: 23*4882a593Smuzhiyun compatible: 24*4882a593Smuzhiyun enum: 25*4882a593Smuzhiyun - qcom,sdm845-gpucc 26*4882a593Smuzhiyun - qcom,sc7180-gpucc 27*4882a593Smuzhiyun - qcom,sm8150-gpucc 28*4882a593Smuzhiyun - qcom,sm8250-gpucc 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clocks: 31*4882a593Smuzhiyun items: 32*4882a593Smuzhiyun - description: Board XO source 33*4882a593Smuzhiyun - description: GPLL0 main branch source 34*4882a593Smuzhiyun - description: GPLL0 div branch source 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clock-names: 37*4882a593Smuzhiyun items: 38*4882a593Smuzhiyun - const: bi_tcxo 39*4882a593Smuzhiyun - const: gcc_gpu_gpll0_clk_src 40*4882a593Smuzhiyun - const: gcc_gpu_gpll0_div_clk_src 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun '#clock-cells': 43*4882a593Smuzhiyun const: 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun '#reset-cells': 46*4882a593Smuzhiyun const: 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun '#power-domain-cells': 49*4882a593Smuzhiyun const: 1 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun reg: 52*4882a593Smuzhiyun maxItems: 1 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunrequired: 55*4882a593Smuzhiyun - compatible 56*4882a593Smuzhiyun - reg 57*4882a593Smuzhiyun - clocks 58*4882a593Smuzhiyun - clock-names 59*4882a593Smuzhiyun - '#clock-cells' 60*4882a593Smuzhiyun - '#reset-cells' 61*4882a593Smuzhiyun - '#power-domain-cells' 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunadditionalProperties: false 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunexamples: 66*4882a593Smuzhiyun - | 67*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,gcc-sdm845.h> 68*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,rpmh.h> 69*4882a593Smuzhiyun clock-controller@5090000 { 70*4882a593Smuzhiyun compatible = "qcom,sdm845-gpucc"; 71*4882a593Smuzhiyun reg = <0x05090000 0x9000>; 72*4882a593Smuzhiyun clocks = <&rpmhcc RPMH_CXO_CLK>, 73*4882a593Smuzhiyun <&gcc GCC_GPU_GPLL0_CLK_SRC>, 74*4882a593Smuzhiyun <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 75*4882a593Smuzhiyun clock-names = "bi_tcxo", 76*4882a593Smuzhiyun "gcc_gpu_gpll0_clk_src", 77*4882a593Smuzhiyun "gcc_gpu_gpll0_div_clk_src"; 78*4882a593Smuzhiyun #clock-cells = <1>; 79*4882a593Smuzhiyun #reset-cells = <1>; 80*4882a593Smuzhiyun #power-domain-cells = <1>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun... 83