1*4882a593Smuzhiyun* Open PIC Binding 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding specifies what properties must be available in the device tree 4*4882a593Smuzhiyunrepresentation of an Open PIC compliant interrupt controller. This binding is 5*4882a593Smuzhiyunbased on the binding defined for Open PIC in [1] and is a superset of that 6*4882a593Smuzhiyunbinding. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun NOTE: Many of these descriptions were paraphrased here from [1] to aid 11*4882a593Smuzhiyun readability. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun - compatible: Specifies the compatibility list for the PIC. The type 14*4882a593Smuzhiyun shall be <string> and the value shall include "open-pic". 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun - reg: Specifies the base physical address(s) and size(s) of this 17*4882a593Smuzhiyun PIC's addressable register space. The type shall be <prop-encoded-array>. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun - interrupt-controller: The presence of this property identifies the node 20*4882a593Smuzhiyun as an Open PIC. No property value shall be defined. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun - #interrupt-cells: Specifies the number of cells needed to encode an 23*4882a593Smuzhiyun interrupt source. The type shall be a <u32> and the value shall be 2. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun - #address-cells: Specifies the number of cells needed to encode an 26*4882a593Smuzhiyun address. The type shall be <u32> and the value shall be 0. As such, 27*4882a593Smuzhiyun 'interrupt-map' nodes do not have to specify a parent unit address. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunOptional properties: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun - pic-no-reset: The presence of this property indicates that the PIC 32*4882a593Smuzhiyun shall not be reset during runtime initialization. No property value shall 33*4882a593Smuzhiyun be defined. The presence of this property also mandates that any 34*4882a593Smuzhiyun initialization related to interrupt sources shall be limited to sources 35*4882a593Smuzhiyun explicitly referenced in the device tree. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun* Interrupt Specifier Definition 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun Interrupt specifiers consists of 2 cells encoded as 40*4882a593Smuzhiyun follows: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun - <1st-cell>: The interrupt-number that identifies the interrupt source. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun - <2nd-cell>: The level-sense information, encoded as follows: 45*4882a593Smuzhiyun 0 = low-to-high edge triggered 46*4882a593Smuzhiyun 1 = active low level-sensitive 47*4882a593Smuzhiyun 2 = active high level-sensitive 48*4882a593Smuzhiyun 3 = high-to-low edge triggered 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun* Examples 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunExample 1: 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * An Open PIC interrupt controller 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun mpic: pic@40000 { 58*4882a593Smuzhiyun // This is an interrupt controller node. 59*4882a593Smuzhiyun interrupt-controller; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun // No address cells so that 'interrupt-map' nodes which reference 62*4882a593Smuzhiyun // this Open PIC node do not need a parent address specifier. 63*4882a593Smuzhiyun #address-cells = <0>; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun // Two cells to encode interrupt sources. 66*4882a593Smuzhiyun #interrupt-cells = <2>; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun // Offset address of 0x40000 and size of 0x40000. 69*4882a593Smuzhiyun reg = <0x40000 0x40000>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun // Compatible with Open PIC. 72*4882a593Smuzhiyun compatible = "open-pic"; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun // The PIC shall not be reset. 75*4882a593Smuzhiyun pic-no-reset; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593SmuzhiyunExample 2: 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* 81*4882a593Smuzhiyun * An interrupt generating device that is wired to an Open PIC. 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun serial0: serial@4500 { 84*4882a593Smuzhiyun // Interrupt source '42' that is active high level-sensitive. 85*4882a593Smuzhiyun // Note that there are only two cells as specified in the interrupt 86*4882a593Smuzhiyun // parent's '#interrupt-cells' property. 87*4882a593Smuzhiyun interrupts = <42 2>; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun // The interrupt controller that this device is wired to. 90*4882a593Smuzhiyun interrupt-parent = <&mpic>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun* References 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun[1] Devicetree Specification 96*4882a593Smuzhiyun (https://www.devicetree.org/specifications/) 97*4882a593Smuzhiyun 98