bindings/pci/rockchip-pcie.txt

4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 		interrupt source. The value must be 1.
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 	- "axi-base"
12 	- "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 		See ../clocks/clock-bindings.txt for details.
15 - clock-names: Must include the following entries:
16 	- "aclk"
17 	- "aclk-perf"
18 	- "hclk"
19 	- "pm"
20 - msi-map: Maps a Requester ID to an MSI controller and associated
21 	msi-specifier data. See ./pci-msi.txt
22 - phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
23 - phy-names:  MUST be "pcie-phy".
24 - interrupts: Three interrupt entries must be specified.
25 - interrupt-names: Must include the following names
26 	- "sys"
27 	- "legacy"
28 	- "client"
29 - resets: Must contain seven entries for each entry in reset-names.
30 	   See ../reset/reset.txt for details.
31 - reset-names: Must include the following names
32 	- "core"
33 	- "mgmt"
34 	- "mgmt-sticky"
35 	- "pipe"
36 	- "pm"
37 	- "aclk"
38 	- "pclk"
39 - pinctrl-names : The pin control state names
40 - pinctrl-0: The "default" pinctrl state
41 - #interrupt-cells: specifies the number of cells needed to encode an
42 	interrupt source. The value must be 1.
43 - interrupt-map-mask and interrupt-map: standard PCI properties
46 - aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
48 - ep-gpios: contain the entry for pre-reset gpio
49 - num-lanes: number of lanes to use
50 - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
51 - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
52 - vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
57 'interrupt-map' property. This node represents the domain at which the four
62 - interrupt-controller: identifies the node as an interrupt controller
63 - #address-cells: specifies the number of cells needed to encode an
65 - #interrupt-cells: specifies the number of cells needed to encode an
66 	interrupt source. The value must be 1.
71 	compatible = "rockchip,rk3399-pcie";
72 	#address-cells = <3>;
73 	#size-cells = <2>;
76 	clock-names = "aclk", "aclk-perf",
78 	bus-range = <0x0 0x1>;
82 	interrupt-names = "sys", "legacy", "client";
83 	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
84 	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
85 	assigned-clock-rates = <100000000>;
86 	ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
89 	num-lanes = <4>;
90 	msi-map = <0x0 &its 0x0 0x1000>;
92 	reg-names = "axi-base", "apb-base";
96 	reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
99 	phy-names = "pcie-phy";
100 	pinctrl-names = "default";
101 	pinctrl-0 = <&pcie_clkreq>;
102 	#interrupt-cells = <1>;
103 	interrupt-map-mask = <0 0 0 7>;
104 	interrupt-map = <0 0 0 1 &pcie0_intc 0>,
108 	pcie0_intc: interrupt-controller {
109 		interrupt-controller;
110 		#address-cells = <0>;
111 		#interrupt-cells = <1>;