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/OK3568_Linux_fs/kernel/drivers/media/pci/cx23885/
H A Dcx23885-cards.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <media/drv-intf/cx25840.h>
18 #include "tuner-xc2028.h"
19 #include "netup-eeprom.h"
20 #include "netup-init.h"
21 #include "altera-ci.h"
24 #include "cx23888-ir.h"
29 "NetUP Dual DVB-T/C CI card revision");
35 "\t\t\tHVR-1250 (reported safe)\n"
41 /* ------------------------------------------------------------------ */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra20-ac97.txt4 - compatible : "nvidia,tegra20-ac97"
5 - reg : Should contain AC97 controller registers location and length
6 - interrupts : Should contain AC97 interrupt
7 - resets : Must contain an entry for each entry in reset-names.
8 See ../reset/reset.txt for details.
9 - reset-names : Must include the following entries:
10 - ac97
11 - dmas : Must contain an entry for each entry in clock-names.
13 - dma-names : Must include the following entries:
14 - rx
[all …]
H A Drt5677.txt7 - compatible : "realtek,rt5677".
9 - reg : The I2C address of the device.
11 - interrupts : The CODEC's interrupt output.
13 - gpio-controller : Indicates this device is a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
20 - realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.
21 - realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. Active low.
23 - realtek,in1-differential
24 - realtek,in2-differential
25 - realtek,lout1-differential
[all …]
H A Dcs4271.txt7 - compatible: "cirrus,cs4271"
10 Documentation/devicetree/bindings/spi/spi-bus.txt
14 - reg: the i2c address
19 - reset-gpio: a GPIO spec to define which pin is connected to the chip's
20 !RESET pin
21 - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag
23 - cirrus,enable-soft-reset:
24 The CS4271 requires its LRCLK and MCLK to be stable before its RESET
25 line is de-asserted. That also means that clocks cannot be changed
26 without putting the chip back into hardware reset, which also requires
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/marvell/
H A Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
34 v_3_3: regulator-3-3v {
35 compatible = "regulator-fixed";
36 regulator-name = "v_3_3";
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Daltera-a10sr.txt4 - compatible : "altr,a10sr"
5 - spi-max-frequency : Maximum SPI frequency.
6 - reg : The SPI Chip Select address for the Arria10
8 - interrupts : The interrupt line the device is connected to.
9 - interrupt-controller : Marks the device node as an interrupt controller.
10 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
13 masks from ../interrupt-controller/interrupts.txt.
15 The A10SR consists of these sub-devices:
18 ------ ----------
19 a10sr_gpio GPIO Controller
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Duniphier-ld4.dtsi4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-ld4";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
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H A Duniphier-sld8.dtsi4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-sld8";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
[all …]
H A Duniphier-pro4.dtsi4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pro4";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
[all …]
H A Dhi3798cv200.dtsi4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
7 * SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/clock/histb-clock.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/ti-syscon.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <2>;
[all …]
H A Duniphier-pro5.dtsi4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
24 enable-method = "psci";
25 next-level-cache = <&l2>;
[all …]
H A Duniphier-pxs2.dtsi4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pxs2";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
24 enable-method = "psci";
25 next-level-cache = <&l2>;
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Darmada-385-clearfog-gtr.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
[all …]
H A Dste-hrefv60plus.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 ST-Ericsson AB
6 #include "ste-href-ab8500.dtsi"
7 #include "ste-href.dtsi"
10 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
11 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
14 /* Name the GPIO muxed rails on the HREF boards */
15 gpio@8012e000 {
16 /* GPIOs 0 - 31 */
17 gpio-line-names =
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H A Dbcm2711-rpi-4-b.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "bcm2835-rpi.dtsi"
5 #include "bcm283x-rpi-usb-peripheral.dtsi"
7 #include <dt-bindings/reset/raspberrypi,firmware-reset.h>
10 compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
15 stdout-path = "serial1:115200n8";
31 led-act {
32 gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
35 led-pwr {
[all …]
H A Dox820.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/oxsemi,ox820.h>
10 #include <dt-bindings/reset/oxsemi,ox820.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "oxsemi,ox820-smp";
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/clock/histb-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/ti-syscon.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
/OK3568_Linux_fs/kernel/sound/soc/
H A Dsoc-ac97.c1 // SPDX-License-Identifier: GPL-2.0+
3 // soc-ac97.c -- ALSA SoC Audio Layer AC97 support
11 // with code, comments and ideas from :-
17 #include <linux/gpio.h>
18 #include <linux/gpio/driver.h>
59 return gpio_priv->component; in gpio_to_component()
65 return -EINVAL; in snd_soc_ac97_gpio_request()
75 dev_dbg(component->dev, "set gpio %d to output\n", offset); in snd_soc_ac97_gpio_direction_in()
87 dev_dbg(component->dev, "get gpio %d : %d\n", offset, in snd_soc_ac97_gpio_get()
99 gpio_priv->gpios_set &= ~(1 << offset); in snd_soc_ac97_gpio_set()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.txt1 Drive a GPIO line that can be used to restart the system from a restart
4 This binding supports level and edge triggered reset. At driver load
5 time, the driver will request the given gpio line and install a restart
6 handler. If the optional properties 'open-source' is not found, the GPIO line
11 priority order. The gpio is configured as an output, and driven active,
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
[all …]
/OK3568_Linux_fs/kernel/drivers/media/pci/cx18/
H A Dcx18-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * cx18 gpio functions
5 * Derived from ivtv-gpio.c
11 #include "cx18-driver.h"
12 #include "cx18-io.h"
13 #include "cx18-cards.h"
14 #include "cx18-gpio.h"
15 #include "tuner-xc2028.h"
17 /********************* GPIO stuffs *********************/
19 /* GPIO registers */
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/OK3568_Linux_fs/u-boot/arch/mips/dts/
H A Dbrcm,bcm3380.dtsi4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/bcm3380-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm3380-reset.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 u-boot,dm-pre-reloc;
22 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
25 u-boot,dm-pre-reloc;
29 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
[all …]
/OK3568_Linux_fs/kernel/drivers/pcmcia/
H A Dpxa2xx_colibri.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/gpio.h>
15 #include <asm/mach-types.h>
39 RESET = 5, enumerator
42 /* Contents of this array are configured on-the-fly in init function */
43 static struct gpio colibri_pcmcia_gpios[] = {
49 { 0, GPIOF_INIT_HIGH,"PCMCIA Reset" },
61 skt->socket.pci_irq = gpio_to_irq(colibri_pcmcia_gpios[READY].gpio); in colibri_pcmcia_hw_init()
62 skt->stat[SOC_STAT_CD].irq = gpio_to_irq(colibri_pcmcia_gpios[DETECT].gpio); in colibri_pcmcia_hw_init()
63 skt->stat[SOC_STAT_CD].name = "PCMCIA CD"; in colibri_pcmcia_hw_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/tty/serial/
H A Difx6x60.c1 // SPDX-License-Identifier: GPL-2.0
19 * o The driver is intended to be big-endian safe but has never been
22 * o Some of the GPIO naming/setup assumptions may need revisiting if
26 #include <linux/dma-mapping.h>
42 #include <linux/gpio/consumer.h>
60 #define IFX_SPI_HEADER_0 (-1)
61 #define IFX_SPI_HEADER_F (-2)
83 gpiod_set_value(ifx_dev->gpio.pmu_reset, 1); in ifx_modem_power_off()
100 /* GPIO/GPE settings */
103 * mrdy_set_high - set MRDY GPIO
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dmmc-pwrseq-emmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple eMMC hardware reset provider binding
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 The purpose of this driver is to perform standard eMMC hw reset
19 doesn't have hardware reset logic connected to emmc card and (limited or
25 const: mmc-pwrseq-emmc
27 reset-gpios:
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/gpio/
H A Dgpio-xra1403.txt1 GPIO Driver for XRA1403 16-BIT GPIO Expander With Reset Input from EXAR
3 The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features available:
4 - Individually programmable inputs:
5 - Internal pull-up resistors
6 - Polarity inversion
7 - Individual interrupt enable
8 - Rising edge and/or Falling edge interrupt
9 - Input filter
10 - Individually programmable outputs
11 - Output Level Control
[all …]

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