1*4882a593SmuzhiyunCirrus Logic CS4271 DT bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis driver supports both the I2C and the SPI bus. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun - compatible: "cirrus,cs4271" 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunFor required properties on SPI, please consult 10*4882a593SmuzhiyunDocumentation/devicetree/bindings/spi/spi-bus.txt 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired properties on I2C: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun - reg: the i2c address 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun - reset-gpio: a GPIO spec to define which pin is connected to the chip's 20*4882a593Smuzhiyun !RESET pin 21*4882a593Smuzhiyun - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag 22*4882a593Smuzhiyun is enabled. 23*4882a593Smuzhiyun - cirrus,enable-soft-reset: 24*4882a593Smuzhiyun The CS4271 requires its LRCLK and MCLK to be stable before its RESET 25*4882a593Smuzhiyun line is de-asserted. That also means that clocks cannot be changed 26*4882a593Smuzhiyun without putting the chip back into hardware reset, which also requires 27*4882a593Smuzhiyun a complete re-initialization of all registers. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun One (undocumented) workaround is to assert and de-assert the PDN bit 30*4882a593Smuzhiyun in the MODE2 register. This workaround can be enabled with this DT 31*4882a593Smuzhiyun property. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun Note that this is not needed in case the clocks are stable 34*4882a593Smuzhiyun throughout the entire runtime of the codec. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun - vd-supply: Digital power 37*4882a593Smuzhiyun - vl-supply: Logic power 38*4882a593Smuzhiyun - va-supply: Analog Power 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExamples: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun codec_i2c: cs4271@10 { 43*4882a593Smuzhiyun compatible = "cirrus,cs4271"; 44*4882a593Smuzhiyun reg = <0x10>; 45*4882a593Smuzhiyun reset-gpio = <&gpio 23 0>; 46*4882a593Smuzhiyun vd-supply = <&vdd_3v3_reg>; 47*4882a593Smuzhiyun vl-supply = <&vdd_3v3_reg>; 48*4882a593Smuzhiyun va-supply = <&vdd_3v3_reg>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun codec_spi: cs4271@0 { 52*4882a593Smuzhiyun compatible = "cirrus,cs4271"; 53*4882a593Smuzhiyun reg = <0x0>; 54*4882a593Smuzhiyun reset-gpio = <&gpio 23 0>; 55*4882a593Smuzhiyun spi-max-frequency = <6000000>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58