Lines Matching +full:reset +full:- +full:gpio
4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-ld4";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,psci-0.2";
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <24576000>;
41 #clock-cells = <0>;
42 compatible = "fixed-clock";
43 clock-frequency = <50000000>;
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
52 interrupt-parent = <&intc>;
53 u-boot,dm-pre-reloc;
55 l2: l2-cache@500c0000 {
56 compatible = "socionext,uniphier-system-cache";
60 cache-unified;
61 cache-size = <(512 * 1024)>;
62 cache-sets = <256>;
63 cache-line-size = <128>;
64 cache-level = <2>;
68 compatible = "socionext,uniphier-uart";
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_uart0>;
75 clock-frequency = <36864000>;
79 compatible = "socionext,uniphier-uart";
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_uart1>;
86 clock-frequency = <36864000>;
90 compatible = "socionext,uniphier-uart";
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_uart2>;
97 clock-frequency = <36864000>;
101 compatible = "socionext,uniphier-uart";
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_uart3>;
108 clock-frequency = <36864000>;
111 port0x: gpio@55000008 {
112 compatible = "socionext,uniphier-gpio";
114 gpio-controller;
115 #gpio-cells = <2>;
118 port1x: gpio@55000010 {
119 compatible = "socionext,uniphier-gpio";
121 gpio-controller;
122 #gpio-cells = <2>;
125 port2x: gpio@55000018 {
126 compatible = "socionext,uniphier-gpio";
128 gpio-controller;
129 #gpio-cells = <2>;
132 port3x: gpio@55000020 {
133 compatible = "socionext,uniphier-gpio";
135 gpio-controller;
136 #gpio-cells = <2>;
139 port4: gpio@55000028 {
140 compatible = "socionext,uniphier-gpio";
142 gpio-controller;
143 #gpio-cells = <2>;
146 port5x: gpio@55000030 {
147 compatible = "socionext,uniphier-gpio";
149 gpio-controller;
150 #gpio-cells = <2>;
153 port6x: gpio@55000038 {
154 compatible = "socionext,uniphier-gpio";
156 gpio-controller;
157 #gpio-cells = <2>;
160 port7x: gpio@55000040 {
161 compatible = "socionext,uniphier-gpio";
163 gpio-controller;
164 #gpio-cells = <2>;
167 port8x: gpio@55000048 {
168 compatible = "socionext,uniphier-gpio";
170 gpio-controller;
171 #gpio-cells = <2>;
174 port9x: gpio@55000050 {
175 compatible = "socionext,uniphier-gpio";
177 gpio-controller;
178 #gpio-cells = <2>;
181 port10x: gpio@55000058 {
182 compatible = "socionext,uniphier-gpio";
184 gpio-controller;
185 #gpio-cells = <2>;
188 port11x: gpio@55000060 {
189 compatible = "socionext,uniphier-gpio";
191 gpio-controller;
192 #gpio-cells = <2>;
195 port12x: gpio@55000068 {
196 compatible = "socionext,uniphier-gpio";
198 gpio-controller;
199 #gpio-cells = <2>;
202 port13x: gpio@55000070 {
203 compatible = "socionext,uniphier-gpio";
205 gpio-controller;
206 #gpio-cells = <2>;
209 port14x: gpio@55000078 {
210 compatible = "socionext,uniphier-gpio";
212 gpio-controller;
213 #gpio-cells = <2>;
216 port16x: gpio@55000088 {
217 compatible = "socionext,uniphier-gpio";
219 gpio-controller;
220 #gpio-cells = <2>;
224 compatible = "socionext,uniphier-i2c";
227 #address-cells = <1>;
228 #size-cells = <0>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_i2c0>;
233 clock-frequency = <100000>;
237 compatible = "socionext,uniphier-i2c";
240 #address-cells = <1>;
241 #size-cells = <0>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_i2c1>;
246 clock-frequency = <100000>;
249 /* chip-internal connection for DMD */
251 compatible = "socionext,uniphier-i2c";
253 #address-cells = <1>;
254 #size-cells = <0>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_i2c2>;
259 clock-frequency = <400000>;
263 compatible = "socionext,uniphier-i2c";
266 #address-cells = <1>;
267 #size-cells = <0>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_i2c3>;
272 clock-frequency = <100000>;
275 system_bus: system-bus@58c00000 {
276 compatible = "socionext,uniphier-system-bus";
279 #address-cells = <2>;
280 #size-cells = <1>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_system_bus>;
286 compatible = "socionext,uniphier-smpctrl";
291 compatible = "socionext,uniphier-ld4-mioctrl",
292 "simple-mfd", "syscon";
296 compatible = "socionext,uniphier-ld4-mio-clock";
297 #clock-cells = <1>;
300 mio_rst: reset {
301 compatible = "socionext,uniphier-ld4-mio-reset";
302 #reset-cells = <1>;
307 compatible = "socionext,uniphier-ld4-perictrl",
308 "simple-mfd", "syscon";
312 compatible = "socionext,uniphier-ld4-peri-clock";
313 #clock-cells = <1>;
316 peri_rst: reset {
317 compatible = "socionext,uniphier-ld4-peri-reset";
318 #reset-cells = <1>;
323 compatible = "socionext,uniphier-sdhc";
327 pinctrl-names = "default", "1.8v";
328 pinctrl-0 = <&pinctrl_sd>;
329 pinctrl-1 = <&pinctrl_sd_1v8>;
331 reset-names = "host", "bridge";
333 bus-width = <4>;
334 cap-sd-highspeed;
335 sd-uhs-sdr12;
336 sd-uhs-sdr25;
337 sd-uhs-sdr50;
341 compatible = "socionext,uniphier-sdhc";
345 pinctrl-names = "default", "1.8v";
346 pinctrl-0 = <&pinctrl_emmc>;
347 pinctrl-1 = <&pinctrl_emmc_1v8>;
349 reset-names = "host", "bridge";
351 bus-width = <8>;
352 non-removable;
353 cap-mmc-highspeed;
354 cap-mmc-hw-reset;
358 compatible = "socionext,uniphier-ehci", "generic-ehci";
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_usb0>;
370 compatible = "socionext,uniphier-ehci", "generic-ehci";
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_usb1>;
382 compatible = "socionext,uniphier-ehci", "generic-ehci";
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_usb2>;
393 soc-glue@5f800000 {
394 compatible = "socionext,uniphier-ld4-soc-glue",
395 "simple-mfd", "syscon";
397 u-boot,dm-pre-reloc;
400 compatible = "socionext,uniphier-ld4-pinctrl";
401 u-boot,dm-pre-reloc;
406 compatible = "arm,cortex-a9-global-timer";
413 compatible = "arm,cortex-a9-twd-timer";
419 intc: interrupt-controller@60001000 {
420 compatible = "arm,cortex-a9-gic";
423 #interrupt-cells = <3>;
424 interrupt-controller;
428 compatible = "socionext,uniphier-ld4-aidet";
430 interrupt-controller;
431 #interrupt-cells = <2>;
435 compatible = "socionext,uniphier-ld4-sysctrl",
436 "simple-mfd", "syscon";
440 compatible = "socionext,uniphier-ld4-clock";
441 #clock-cells = <1>;
444 sys_rst: reset {
445 compatible = "socionext,uniphier-ld4-reset";
446 #reset-cells = <1>;
451 compatible = "socionext,uniphier-denali-nand-v5a";
453 reg-names = "nand_data", "denali_reg";
456 pinctrl-names = "default";
457 pinctrl-0 = <&pinctrl_nand2cs>;
463 #include "uniphier-pinctrl.dtsi"