xref: /OK3568_Linux_fs/u-boot/arch/mips/dts/brcm,bcm3380.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/clock/bcm3380-clock.h>
8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
9*4882a593Smuzhiyun#include <dt-bindings/reset/bcm3380-reset.h>
10*4882a593Smuzhiyun#include "skeleton.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	compatible = "brcm,bcm3380";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	cpus {
16*4882a593Smuzhiyun		reg = <0x14e00000 0x4>;
17*4882a593Smuzhiyun		#address-cells = <1>;
18*4882a593Smuzhiyun		#size-cells = <0>;
19*4882a593Smuzhiyun		u-boot,dm-pre-reloc;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun		cpu@0 {
22*4882a593Smuzhiyun			compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
23*4882a593Smuzhiyun			device_type = "cpu";
24*4882a593Smuzhiyun			reg = <0>;
25*4882a593Smuzhiyun			u-boot,dm-pre-reloc;
26*4882a593Smuzhiyun		};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		cpu@1 {
29*4882a593Smuzhiyun			compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
30*4882a593Smuzhiyun			device_type = "cpu";
31*4882a593Smuzhiyun			reg = <1>;
32*4882a593Smuzhiyun			u-boot,dm-pre-reloc;
33*4882a593Smuzhiyun		};
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	clocks {
37*4882a593Smuzhiyun		compatible = "simple-bus";
38*4882a593Smuzhiyun		#address-cells = <1>;
39*4882a593Smuzhiyun		#size-cells = <1>;
40*4882a593Smuzhiyun		u-boot,dm-pre-reloc;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun		periph_osc: periph-osc {
43*4882a593Smuzhiyun			compatible = "fixed-clock";
44*4882a593Smuzhiyun			#clock-cells = <0>;
45*4882a593Smuzhiyun			clock-frequency = <48000000>;
46*4882a593Smuzhiyun			u-boot,dm-pre-reloc;
47*4882a593Smuzhiyun		};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun		periph_clk0: periph-clk@14e00004 {
50*4882a593Smuzhiyun			compatible = "brcm,bcm6345-clk";
51*4882a593Smuzhiyun			reg = <0x14e00004 0x4>;
52*4882a593Smuzhiyun			#clock-cells = <1>;
53*4882a593Smuzhiyun		};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun		periph_clk1: periph-clk@14e00008 {
56*4882a593Smuzhiyun			compatible = "brcm,bcm6345-clk";
57*4882a593Smuzhiyun			reg = <0x14e00008 0x4>;
58*4882a593Smuzhiyun			#clock-cells = <1>;
59*4882a593Smuzhiyun		};
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	ubus {
63*4882a593Smuzhiyun		compatible = "simple-bus";
64*4882a593Smuzhiyun		#address-cells = <1>;
65*4882a593Smuzhiyun		#size-cells = <1>;
66*4882a593Smuzhiyun		u-boot,dm-pre-reloc;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun		memory-controller@12000000 {
69*4882a593Smuzhiyun			compatible = "brcm,bcm6328-mc";
70*4882a593Smuzhiyun			reg = <0x12000000 0x1000>;
71*4882a593Smuzhiyun			u-boot,dm-pre-reloc;
72*4882a593Smuzhiyun		};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun		periph_rst0: reset-controller@14e0008c {
75*4882a593Smuzhiyun			compatible = "brcm,bcm6345-reset";
76*4882a593Smuzhiyun			reg = <0x14e0008c 0x4>;
77*4882a593Smuzhiyun			#reset-cells = <1>;
78*4882a593Smuzhiyun		};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun		periph_rst1: reset-controller@14e00090 {
81*4882a593Smuzhiyun			compatible = "brcm,bcm6345-reset";
82*4882a593Smuzhiyun			reg = <0x14e00090 0x4>;
83*4882a593Smuzhiyun			#reset-cells = <1>;
84*4882a593Smuzhiyun		};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun		pll_cntl: syscon@14e00094 {
87*4882a593Smuzhiyun			compatible = "syscon";
88*4882a593Smuzhiyun			reg = <0x14e00094 0x4>;
89*4882a593Smuzhiyun		};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun		syscon-reboot {
92*4882a593Smuzhiyun			compatible = "syscon-reboot";
93*4882a593Smuzhiyun			regmap = <&pll_cntl>;
94*4882a593Smuzhiyun			offset = <0x0>;
95*4882a593Smuzhiyun			mask = <0x1>;
96*4882a593Smuzhiyun		};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun		wdt: watchdog@14e000dc {
99*4882a593Smuzhiyun			compatible = "brcm,bcm6345-wdt";
100*4882a593Smuzhiyun			reg = <0x14e000dc 0xc>;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun			clocks = <&periph_osc>;
103*4882a593Smuzhiyun		};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun		wdt-reboot {
106*4882a593Smuzhiyun			compatible = "wdt-reboot";
107*4882a593Smuzhiyun			wdt = <&wdt>;
108*4882a593Smuzhiyun		};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun		gpio0: gpio-controller@14e00100 {
111*4882a593Smuzhiyun			compatible = "brcm,bcm6345-gpio";
112*4882a593Smuzhiyun			reg = <0x14e00100 0x4>, <0x14e00108 0x4>;
113*4882a593Smuzhiyun			gpio-controller;
114*4882a593Smuzhiyun			#gpio-cells = <2>;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun			status = "disabled";
117*4882a593Smuzhiyun		};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun		gpio1: gpio-controller@14e00104 {
120*4882a593Smuzhiyun			compatible = "brcm,bcm6345-gpio";
121*4882a593Smuzhiyun			reg = <0x14e00104 0x4>, <0x14e0010c 0x4>;
122*4882a593Smuzhiyun			gpio-controller;
123*4882a593Smuzhiyun			#gpio-cells = <2>;
124*4882a593Smuzhiyun			ngpios = <3>;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun			status = "disabled";
127*4882a593Smuzhiyun		};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun		uart0: serial@14e00200 {
130*4882a593Smuzhiyun			compatible = "brcm,bcm6345-uart";
131*4882a593Smuzhiyun			reg = <0x14e00200 0x18>;
132*4882a593Smuzhiyun			clocks = <&periph_osc>;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun			status = "disabled";
135*4882a593Smuzhiyun		};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun		uart1: serial@14e00220 {
138*4882a593Smuzhiyun			compatible = "brcm,bcm6345-uart";
139*4882a593Smuzhiyun			reg = <0x14e00220 0x18>;
140*4882a593Smuzhiyun			clocks = <&periph_osc>;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun			status = "disabled";
143*4882a593Smuzhiyun		};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun		leds: led-controller@14e00f00 {
146*4882a593Smuzhiyun			compatible = "brcm,bcm6328-leds";
147*4882a593Smuzhiyun			reg = <0x14e00f00 0x1c>;
148*4882a593Smuzhiyun			#address-cells = <1>;
149*4882a593Smuzhiyun			#size-cells = <0>;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun			status = "disabled";
152*4882a593Smuzhiyun		};
153*4882a593Smuzhiyun	};
154*4882a593Smuzhiyun};
155