xref: /OK3568_Linux_fs/kernel/drivers/media/pci/cx23885/cx23885-cards.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Driver for the Conexant CX23885 PCIe bridge
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include "cx23885.h"
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/pci.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <media/drv-intf/cx25840.h>
15*4882a593Smuzhiyun #include <linux/firmware.h>
16*4882a593Smuzhiyun #include <misc/altera.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include "tuner-xc2028.h"
19*4882a593Smuzhiyun #include "netup-eeprom.h"
20*4882a593Smuzhiyun #include "netup-init.h"
21*4882a593Smuzhiyun #include "altera-ci.h"
22*4882a593Smuzhiyun #include "xc4000.h"
23*4882a593Smuzhiyun #include "xc5000.h"
24*4882a593Smuzhiyun #include "cx23888-ir.h"
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun static unsigned int netup_card_rev = 4;
27*4882a593Smuzhiyun module_param(netup_card_rev, int, 0644);
28*4882a593Smuzhiyun MODULE_PARM_DESC(netup_card_rev,
29*4882a593Smuzhiyun 		"NetUP Dual DVB-T/C CI card revision");
30*4882a593Smuzhiyun static unsigned int enable_885_ir;
31*4882a593Smuzhiyun module_param(enable_885_ir, int, 0644);
32*4882a593Smuzhiyun MODULE_PARM_DESC(enable_885_ir,
33*4882a593Smuzhiyun 		 "Enable integrated IR controller for supported\n"
34*4882a593Smuzhiyun 		 "\t\t    CX2388[57] boards that are wired for it:\n"
35*4882a593Smuzhiyun 		 "\t\t\tHVR-1250 (reported safe)\n"
36*4882a593Smuzhiyun 		 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
37*4882a593Smuzhiyun 		 "\t\t\tTeVii S470 (reported unsafe)\n"
38*4882a593Smuzhiyun 		 "\t\t    This can cause an interrupt storm with some cards.\n"
39*4882a593Smuzhiyun 		 "\t\t    Default: 0 [Disabled]");
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /* ------------------------------------------------------------------ */
42*4882a593Smuzhiyun /* board config info                                                  */
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun struct cx23885_board cx23885_boards[] = {
45*4882a593Smuzhiyun 	[CX23885_BOARD_UNKNOWN] = {
46*4882a593Smuzhiyun 		.name		= "UNKNOWN/GENERIC",
47*4882a593Smuzhiyun 		/* Ensure safe default for unknown boards */
48*4882a593Smuzhiyun 		.clk_freq       = 0,
49*4882a593Smuzhiyun 		.input          = {{
50*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
51*4882a593Smuzhiyun 			.vmux   = 0,
52*4882a593Smuzhiyun 		}, {
53*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE2,
54*4882a593Smuzhiyun 			.vmux   = 1,
55*4882a593Smuzhiyun 		}, {
56*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE3,
57*4882a593Smuzhiyun 			.vmux   = 2,
58*4882a593Smuzhiyun 		}, {
59*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE4,
60*4882a593Smuzhiyun 			.vmux   = 3,
61*4882a593Smuzhiyun 		} },
62*4882a593Smuzhiyun 	},
63*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
64*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1800lp",
65*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
66*4882a593Smuzhiyun 		.input          = {{
67*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
68*4882a593Smuzhiyun 			.vmux   = 0,
69*4882a593Smuzhiyun 			.gpio0  = 0xff00,
70*4882a593Smuzhiyun 		}, {
71*4882a593Smuzhiyun 			.type   = CX23885_VMUX_DEBUG,
72*4882a593Smuzhiyun 			.vmux   = 0,
73*4882a593Smuzhiyun 			.gpio0  = 0xff01,
74*4882a593Smuzhiyun 		}, {
75*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
76*4882a593Smuzhiyun 			.vmux   = 1,
77*4882a593Smuzhiyun 			.gpio0  = 0xff02,
78*4882a593Smuzhiyun 		}, {
79*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
80*4882a593Smuzhiyun 			.vmux   = 2,
81*4882a593Smuzhiyun 			.gpio0  = 0xff02,
82*4882a593Smuzhiyun 		} },
83*4882a593Smuzhiyun 	},
84*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1800] = {
85*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1800",
86*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
87*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_ENCODER,
88*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
89*4882a593Smuzhiyun 		.tuner_type	= TUNER_PHILIPS_TDA8290,
90*4882a593Smuzhiyun 		.tuner_addr	= 0x42, /* 0x84 >> 1 */
91*4882a593Smuzhiyun 		.tuner_bus	= 1,
92*4882a593Smuzhiyun 		.input          = {{
93*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
94*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
95*4882a593Smuzhiyun 					CX25840_VIN5_CH2 |
96*4882a593Smuzhiyun 					CX25840_VIN2_CH1,
97*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO8,
98*4882a593Smuzhiyun 			.gpio0  = 0,
99*4882a593Smuzhiyun 		}, {
100*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
101*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
102*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
103*4882a593Smuzhiyun 					CX25840_VIN6_CH1,
104*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
105*4882a593Smuzhiyun 			.gpio0  = 0,
106*4882a593Smuzhiyun 		}, {
107*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
108*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
109*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
110*4882a593Smuzhiyun 					CX25840_VIN8_CH1 |
111*4882a593Smuzhiyun 					CX25840_SVIDEO_ON,
112*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
113*4882a593Smuzhiyun 			.gpio0  = 0,
114*4882a593Smuzhiyun 		} },
115*4882a593Smuzhiyun 	},
116*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1250] = {
117*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1250",
118*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
119*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
120*4882a593Smuzhiyun #ifdef MT2131_NO_ANALOG_SUPPORT_YET
121*4882a593Smuzhiyun 		.tuner_type	= TUNER_PHILIPS_TDA8290,
122*4882a593Smuzhiyun 		.tuner_addr	= 0x42, /* 0x84 >> 1 */
123*4882a593Smuzhiyun 		.tuner_bus	= 1,
124*4882a593Smuzhiyun #endif
125*4882a593Smuzhiyun 		.force_bff	= 1,
126*4882a593Smuzhiyun 		.input          = {{
127*4882a593Smuzhiyun #ifdef MT2131_NO_ANALOG_SUPPORT_YET
128*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
129*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
130*4882a593Smuzhiyun 					CX25840_VIN5_CH2 |
131*4882a593Smuzhiyun 					CX25840_VIN2_CH1,
132*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO8,
133*4882a593Smuzhiyun 			.gpio0  = 0xff00,
134*4882a593Smuzhiyun 		}, {
135*4882a593Smuzhiyun #endif
136*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
137*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
138*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
139*4882a593Smuzhiyun 					CX25840_VIN6_CH1,
140*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
141*4882a593Smuzhiyun 			.gpio0  = 0xff02,
142*4882a593Smuzhiyun 		}, {
143*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
144*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
145*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
146*4882a593Smuzhiyun 					CX25840_VIN8_CH1 |
147*4882a593Smuzhiyun 					CX25840_SVIDEO_ON,
148*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
149*4882a593Smuzhiyun 			.gpio0  = 0xff02,
150*4882a593Smuzhiyun 		} },
151*4882a593Smuzhiyun 	},
152*4882a593Smuzhiyun 	[CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
153*4882a593Smuzhiyun 		.name		= "DViCO FusionHDTV5 Express",
154*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
155*4882a593Smuzhiyun 	},
156*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
157*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1500Q",
158*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
159*4882a593Smuzhiyun 	},
160*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1500] = {
161*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1500",
162*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
163*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
164*4882a593Smuzhiyun 		.tuner_type	= TUNER_XC2028,
165*4882a593Smuzhiyun 		.tuner_addr	= 0x61, /* 0xc2 >> 1 */
166*4882a593Smuzhiyun 		.input          = {{
167*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
168*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
169*4882a593Smuzhiyun 					CX25840_VIN5_CH2 |
170*4882a593Smuzhiyun 					CX25840_VIN2_CH1,
171*4882a593Smuzhiyun 			.gpio0  = 0,
172*4882a593Smuzhiyun 		}, {
173*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
174*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
175*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
176*4882a593Smuzhiyun 					CX25840_VIN6_CH1,
177*4882a593Smuzhiyun 			.gpio0  = 0,
178*4882a593Smuzhiyun 		}, {
179*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
180*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
181*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
182*4882a593Smuzhiyun 					CX25840_VIN8_CH1 |
183*4882a593Smuzhiyun 					CX25840_SVIDEO_ON,
184*4882a593Smuzhiyun 			.gpio0  = 0,
185*4882a593Smuzhiyun 		} },
186*4882a593Smuzhiyun 	},
187*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1200] = {
188*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1200",
189*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
190*4882a593Smuzhiyun 	},
191*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1700] = {
192*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1700",
193*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
194*4882a593Smuzhiyun 	},
195*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1400] = {
196*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1400",
197*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
198*4882a593Smuzhiyun 	},
199*4882a593Smuzhiyun 	[CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
200*4882a593Smuzhiyun 		.name		= "DViCO FusionHDTV7 Dual Express",
201*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
202*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
203*4882a593Smuzhiyun 	},
204*4882a593Smuzhiyun 	[CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
205*4882a593Smuzhiyun 		.name		= "DViCO FusionHDTV DVB-T Dual Express",
206*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
207*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
208*4882a593Smuzhiyun 	},
209*4882a593Smuzhiyun 	[CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
210*4882a593Smuzhiyun 		.name		= "Leadtek Winfast PxDVR3200 H",
211*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
212*4882a593Smuzhiyun 	},
213*4882a593Smuzhiyun 	[CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = {
214*4882a593Smuzhiyun 		.name		= "Leadtek Winfast PxPVR2200",
215*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
216*4882a593Smuzhiyun 		.tuner_type	= TUNER_XC2028,
217*4882a593Smuzhiyun 		.tuner_addr	= 0x61,
218*4882a593Smuzhiyun 		.tuner_bus	= 1,
219*4882a593Smuzhiyun 		.input		= {{
220*4882a593Smuzhiyun 			.type	= CX23885_VMUX_TELEVISION,
221*4882a593Smuzhiyun 			.vmux	= CX25840_VIN2_CH1 |
222*4882a593Smuzhiyun 				  CX25840_VIN5_CH2,
223*4882a593Smuzhiyun 			.amux	= CX25840_AUDIO8,
224*4882a593Smuzhiyun 			.gpio0	= 0x704040,
225*4882a593Smuzhiyun 		}, {
226*4882a593Smuzhiyun 			.type	= CX23885_VMUX_COMPOSITE1,
227*4882a593Smuzhiyun 			.vmux	= CX25840_COMPOSITE1,
228*4882a593Smuzhiyun 			.amux	= CX25840_AUDIO7,
229*4882a593Smuzhiyun 			.gpio0	= 0x704040,
230*4882a593Smuzhiyun 		}, {
231*4882a593Smuzhiyun 			.type	= CX23885_VMUX_SVIDEO,
232*4882a593Smuzhiyun 			.vmux	= CX25840_SVIDEO_LUMA3 |
233*4882a593Smuzhiyun 				  CX25840_SVIDEO_CHROMA4,
234*4882a593Smuzhiyun 			.amux	= CX25840_AUDIO7,
235*4882a593Smuzhiyun 			.gpio0	= 0x704040,
236*4882a593Smuzhiyun 		}, {
237*4882a593Smuzhiyun 			.type	= CX23885_VMUX_COMPONENT,
238*4882a593Smuzhiyun 			.vmux	= CX25840_VIN7_CH1 |
239*4882a593Smuzhiyun 				  CX25840_VIN6_CH2 |
240*4882a593Smuzhiyun 				  CX25840_VIN8_CH3 |
241*4882a593Smuzhiyun 				  CX25840_COMPONENT_ON,
242*4882a593Smuzhiyun 			.amux	= CX25840_AUDIO7,
243*4882a593Smuzhiyun 			.gpio0	= 0x704040,
244*4882a593Smuzhiyun 		} },
245*4882a593Smuzhiyun 	},
246*4882a593Smuzhiyun 	[CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
247*4882a593Smuzhiyun 		.name		= "Leadtek Winfast PxDVR3200 H XC4000",
248*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
249*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
250*4882a593Smuzhiyun 		.tuner_type	= TUNER_XC4000,
251*4882a593Smuzhiyun 		.tuner_addr	= 0x61,
252*4882a593Smuzhiyun 		.radio_type	= UNSET,
253*4882a593Smuzhiyun 		.radio_addr	= ADDR_UNSET,
254*4882a593Smuzhiyun 		.input		= {{
255*4882a593Smuzhiyun 			.type	= CX23885_VMUX_TELEVISION,
256*4882a593Smuzhiyun 			.vmux	= CX25840_VIN2_CH1 |
257*4882a593Smuzhiyun 				  CX25840_VIN5_CH2 |
258*4882a593Smuzhiyun 				  CX25840_NONE0_CH3,
259*4882a593Smuzhiyun 		}, {
260*4882a593Smuzhiyun 			.type	= CX23885_VMUX_COMPOSITE1,
261*4882a593Smuzhiyun 			.vmux	= CX25840_COMPOSITE1,
262*4882a593Smuzhiyun 		}, {
263*4882a593Smuzhiyun 			.type	= CX23885_VMUX_SVIDEO,
264*4882a593Smuzhiyun 			.vmux	= CX25840_SVIDEO_LUMA3 |
265*4882a593Smuzhiyun 				  CX25840_SVIDEO_CHROMA4,
266*4882a593Smuzhiyun 		}, {
267*4882a593Smuzhiyun 			.type	= CX23885_VMUX_COMPONENT,
268*4882a593Smuzhiyun 			.vmux	= CX25840_VIN7_CH1 |
269*4882a593Smuzhiyun 				  CX25840_VIN6_CH2 |
270*4882a593Smuzhiyun 				  CX25840_VIN8_CH3 |
271*4882a593Smuzhiyun 				  CX25840_COMPONENT_ON,
272*4882a593Smuzhiyun 		} },
273*4882a593Smuzhiyun 	},
274*4882a593Smuzhiyun 	[CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
275*4882a593Smuzhiyun 		.name		= "Compro VideoMate E650F",
276*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
277*4882a593Smuzhiyun 	},
278*4882a593Smuzhiyun 	[CX23885_BOARD_TBS_6920] = {
279*4882a593Smuzhiyun 		.name		= "TurboSight TBS 6920",
280*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
281*4882a593Smuzhiyun 	},
282*4882a593Smuzhiyun 	[CX23885_BOARD_TBS_6980] = {
283*4882a593Smuzhiyun 		.name		= "TurboSight TBS 6980",
284*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
285*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
286*4882a593Smuzhiyun 	},
287*4882a593Smuzhiyun 	[CX23885_BOARD_TBS_6981] = {
288*4882a593Smuzhiyun 		.name		= "TurboSight TBS 6981",
289*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
290*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
291*4882a593Smuzhiyun 	},
292*4882a593Smuzhiyun 	[CX23885_BOARD_TEVII_S470] = {
293*4882a593Smuzhiyun 		.name		= "TeVii S470",
294*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
295*4882a593Smuzhiyun 	},
296*4882a593Smuzhiyun 	[CX23885_BOARD_DVBWORLD_2005] = {
297*4882a593Smuzhiyun 		.name		= "DVBWorld DVB-S2 2005",
298*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
299*4882a593Smuzhiyun 	},
300*4882a593Smuzhiyun 	[CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
301*4882a593Smuzhiyun 		.ci_type	= 1,
302*4882a593Smuzhiyun 		.name		= "NetUP Dual DVB-S2 CI",
303*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
304*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
305*4882a593Smuzhiyun 	},
306*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1270] = {
307*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1270",
308*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
309*4882a593Smuzhiyun 	},
310*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1275] = {
311*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1275",
312*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
313*4882a593Smuzhiyun 	},
314*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1255] = {
315*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1255",
316*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
317*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
318*4882a593Smuzhiyun 		.tuner_type	= TUNER_ABSENT,
319*4882a593Smuzhiyun 		.tuner_addr	= 0x42, /* 0x84 >> 1 */
320*4882a593Smuzhiyun 		.force_bff	= 1,
321*4882a593Smuzhiyun 		.input          = {{
322*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
323*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
324*4882a593Smuzhiyun 					CX25840_VIN5_CH2 |
325*4882a593Smuzhiyun 					CX25840_VIN2_CH1 |
326*4882a593Smuzhiyun 					CX25840_DIF_ON,
327*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO8,
328*4882a593Smuzhiyun 		}, {
329*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
330*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
331*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
332*4882a593Smuzhiyun 					CX25840_VIN6_CH1,
333*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
334*4882a593Smuzhiyun 		}, {
335*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
336*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
337*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
338*4882a593Smuzhiyun 					CX25840_VIN8_CH1 |
339*4882a593Smuzhiyun 					CX25840_SVIDEO_ON,
340*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
341*4882a593Smuzhiyun 		} },
342*4882a593Smuzhiyun 	},
343*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
344*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1255",
345*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
346*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
347*4882a593Smuzhiyun 		.tuner_type	= TUNER_ABSENT,
348*4882a593Smuzhiyun 		.tuner_addr	= 0x42, /* 0x84 >> 1 */
349*4882a593Smuzhiyun 		.force_bff	= 1,
350*4882a593Smuzhiyun 		.input          = {{
351*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
352*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
353*4882a593Smuzhiyun 					CX25840_VIN5_CH2 |
354*4882a593Smuzhiyun 					CX25840_VIN2_CH1 |
355*4882a593Smuzhiyun 					CX25840_DIF_ON,
356*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO8,
357*4882a593Smuzhiyun 		}, {
358*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
359*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
360*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
361*4882a593Smuzhiyun 					CX25840_VIN8_CH1 |
362*4882a593Smuzhiyun 					CX25840_SVIDEO_ON,
363*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
364*4882a593Smuzhiyun 		} },
365*4882a593Smuzhiyun 	},
366*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1210] = {
367*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1210",
368*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
369*4882a593Smuzhiyun 	},
370*4882a593Smuzhiyun 	[CX23885_BOARD_MYGICA_X8506] = {
371*4882a593Smuzhiyun 		.name		= "Mygica X8506 DMB-TH",
372*4882a593Smuzhiyun 		.tuner_type = TUNER_XC5000,
373*4882a593Smuzhiyun 		.tuner_addr = 0x61,
374*4882a593Smuzhiyun 		.tuner_bus	= 1,
375*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
376*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
377*4882a593Smuzhiyun 		.input		= {
378*4882a593Smuzhiyun 			{
379*4882a593Smuzhiyun 				.type   = CX23885_VMUX_TELEVISION,
380*4882a593Smuzhiyun 				.vmux   = CX25840_COMPOSITE2,
381*4882a593Smuzhiyun 			},
382*4882a593Smuzhiyun 			{
383*4882a593Smuzhiyun 				.type   = CX23885_VMUX_COMPOSITE1,
384*4882a593Smuzhiyun 				.vmux   = CX25840_COMPOSITE8,
385*4882a593Smuzhiyun 			},
386*4882a593Smuzhiyun 			{
387*4882a593Smuzhiyun 				.type   = CX23885_VMUX_SVIDEO,
388*4882a593Smuzhiyun 				.vmux   = CX25840_SVIDEO_LUMA3 |
389*4882a593Smuzhiyun 						CX25840_SVIDEO_CHROMA4,
390*4882a593Smuzhiyun 			},
391*4882a593Smuzhiyun 			{
392*4882a593Smuzhiyun 				.type   = CX23885_VMUX_COMPONENT,
393*4882a593Smuzhiyun 				.vmux   = CX25840_COMPONENT_ON |
394*4882a593Smuzhiyun 					CX25840_VIN1_CH1 |
395*4882a593Smuzhiyun 					CX25840_VIN6_CH2 |
396*4882a593Smuzhiyun 					CX25840_VIN7_CH3,
397*4882a593Smuzhiyun 			},
398*4882a593Smuzhiyun 		},
399*4882a593Smuzhiyun 	},
400*4882a593Smuzhiyun 	[CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
401*4882a593Smuzhiyun 		.name		= "Magic-Pro ProHDTV Extreme 2",
402*4882a593Smuzhiyun 		.tuner_type = TUNER_XC5000,
403*4882a593Smuzhiyun 		.tuner_addr = 0x61,
404*4882a593Smuzhiyun 		.tuner_bus	= 1,
405*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
406*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
407*4882a593Smuzhiyun 		.input		= {
408*4882a593Smuzhiyun 			{
409*4882a593Smuzhiyun 				.type   = CX23885_VMUX_TELEVISION,
410*4882a593Smuzhiyun 				.vmux   = CX25840_COMPOSITE2,
411*4882a593Smuzhiyun 			},
412*4882a593Smuzhiyun 			{
413*4882a593Smuzhiyun 				.type   = CX23885_VMUX_COMPOSITE1,
414*4882a593Smuzhiyun 				.vmux   = CX25840_COMPOSITE8,
415*4882a593Smuzhiyun 			},
416*4882a593Smuzhiyun 			{
417*4882a593Smuzhiyun 				.type   = CX23885_VMUX_SVIDEO,
418*4882a593Smuzhiyun 				.vmux   = CX25840_SVIDEO_LUMA3 |
419*4882a593Smuzhiyun 						CX25840_SVIDEO_CHROMA4,
420*4882a593Smuzhiyun 			},
421*4882a593Smuzhiyun 			{
422*4882a593Smuzhiyun 				.type   = CX23885_VMUX_COMPONENT,
423*4882a593Smuzhiyun 				.vmux   = CX25840_COMPONENT_ON |
424*4882a593Smuzhiyun 					CX25840_VIN1_CH1 |
425*4882a593Smuzhiyun 					CX25840_VIN6_CH2 |
426*4882a593Smuzhiyun 					CX25840_VIN7_CH3,
427*4882a593Smuzhiyun 			},
428*4882a593Smuzhiyun 		},
429*4882a593Smuzhiyun 	},
430*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1850] = {
431*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1850",
432*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
433*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_ENCODER,
434*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
435*4882a593Smuzhiyun 		.tuner_type	= TUNER_ABSENT,
436*4882a593Smuzhiyun 		.tuner_addr	= 0x42, /* 0x84 >> 1 */
437*4882a593Smuzhiyun 		.force_bff	= 1,
438*4882a593Smuzhiyun 		.input          = {{
439*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
440*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
441*4882a593Smuzhiyun 					CX25840_VIN5_CH2 |
442*4882a593Smuzhiyun 					CX25840_VIN2_CH1 |
443*4882a593Smuzhiyun 					CX25840_DIF_ON,
444*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO8,
445*4882a593Smuzhiyun 		}, {
446*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
447*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
448*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
449*4882a593Smuzhiyun 					CX25840_VIN6_CH1,
450*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
451*4882a593Smuzhiyun 		}, {
452*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
453*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
454*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
455*4882a593Smuzhiyun 					CX25840_VIN8_CH1 |
456*4882a593Smuzhiyun 					CX25840_SVIDEO_ON,
457*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
458*4882a593Smuzhiyun 		} },
459*4882a593Smuzhiyun 	},
460*4882a593Smuzhiyun 	[CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
461*4882a593Smuzhiyun 		.name		= "Compro VideoMate E800",
462*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
463*4882a593Smuzhiyun 	},
464*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1290] = {
465*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR1290",
466*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
467*4882a593Smuzhiyun 	},
468*4882a593Smuzhiyun 	[CX23885_BOARD_MYGICA_X8558PRO] = {
469*4882a593Smuzhiyun 		.name		= "Mygica X8558 PRO DMB-TH",
470*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
471*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
472*4882a593Smuzhiyun 	},
473*4882a593Smuzhiyun 	[CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
474*4882a593Smuzhiyun 		.name           = "LEADTEK WinFast PxTV1200",
475*4882a593Smuzhiyun 		.porta          = CX23885_ANALOG_VIDEO,
476*4882a593Smuzhiyun 		.tuner_type     = TUNER_XC2028,
477*4882a593Smuzhiyun 		.tuner_addr     = 0x61,
478*4882a593Smuzhiyun 		.tuner_bus	= 1,
479*4882a593Smuzhiyun 		.input          = {{
480*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
481*4882a593Smuzhiyun 			.vmux   = CX25840_VIN2_CH1 |
482*4882a593Smuzhiyun 				  CX25840_VIN5_CH2 |
483*4882a593Smuzhiyun 				  CX25840_NONE0_CH3,
484*4882a593Smuzhiyun 		}, {
485*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
486*4882a593Smuzhiyun 			.vmux   = CX25840_COMPOSITE1,
487*4882a593Smuzhiyun 		}, {
488*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
489*4882a593Smuzhiyun 			.vmux   = CX25840_SVIDEO_LUMA3 |
490*4882a593Smuzhiyun 				  CX25840_SVIDEO_CHROMA4,
491*4882a593Smuzhiyun 		}, {
492*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPONENT,
493*4882a593Smuzhiyun 			.vmux   = CX25840_VIN7_CH1 |
494*4882a593Smuzhiyun 				  CX25840_VIN6_CH2 |
495*4882a593Smuzhiyun 				  CX25840_VIN8_CH3 |
496*4882a593Smuzhiyun 				  CX25840_COMPONENT_ON,
497*4882a593Smuzhiyun 		} },
498*4882a593Smuzhiyun 	},
499*4882a593Smuzhiyun 	[CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
500*4882a593Smuzhiyun 		.name		= "GoTView X5 3D Hybrid",
501*4882a593Smuzhiyun 		.tuner_type	= TUNER_XC5000,
502*4882a593Smuzhiyun 		.tuner_addr	= 0x64,
503*4882a593Smuzhiyun 		.tuner_bus	= 1,
504*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
505*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
506*4882a593Smuzhiyun 		.input          = {{
507*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
508*4882a593Smuzhiyun 			.vmux   = CX25840_VIN2_CH1 |
509*4882a593Smuzhiyun 				  CX25840_VIN5_CH2,
510*4882a593Smuzhiyun 			.gpio0	= 0x02,
511*4882a593Smuzhiyun 		}, {
512*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
513*4882a593Smuzhiyun 			.vmux   = CX23885_VMUX_COMPOSITE1,
514*4882a593Smuzhiyun 		}, {
515*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
516*4882a593Smuzhiyun 			.vmux   = CX25840_SVIDEO_LUMA3 |
517*4882a593Smuzhiyun 				  CX25840_SVIDEO_CHROMA4,
518*4882a593Smuzhiyun 		} },
519*4882a593Smuzhiyun 	},
520*4882a593Smuzhiyun 	[CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
521*4882a593Smuzhiyun 		.ci_type	= 2,
522*4882a593Smuzhiyun 		.name		= "NetUP Dual DVB-T/C-CI RF",
523*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
524*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
525*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
526*4882a593Smuzhiyun 		.num_fds_portb	= 2,
527*4882a593Smuzhiyun 		.num_fds_portc	= 2,
528*4882a593Smuzhiyun 		.tuner_type	= TUNER_XC5000,
529*4882a593Smuzhiyun 		.tuner_addr	= 0x64,
530*4882a593Smuzhiyun 		.input          = { {
531*4882a593Smuzhiyun 				.type   = CX23885_VMUX_TELEVISION,
532*4882a593Smuzhiyun 				.vmux   = CX25840_COMPOSITE1,
533*4882a593Smuzhiyun 		} },
534*4882a593Smuzhiyun 	},
535*4882a593Smuzhiyun 	[CX23885_BOARD_MPX885] = {
536*4882a593Smuzhiyun 		.name		= "MPX-885",
537*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
538*4882a593Smuzhiyun 		.input          = {{
539*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
540*4882a593Smuzhiyun 			.vmux   = CX25840_COMPOSITE1,
541*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO6,
542*4882a593Smuzhiyun 			.gpio0  = 0,
543*4882a593Smuzhiyun 		}, {
544*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE2,
545*4882a593Smuzhiyun 			.vmux   = CX25840_COMPOSITE2,
546*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO6,
547*4882a593Smuzhiyun 			.gpio0  = 0,
548*4882a593Smuzhiyun 		}, {
549*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE3,
550*4882a593Smuzhiyun 			.vmux   = CX25840_COMPOSITE3,
551*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
552*4882a593Smuzhiyun 			.gpio0  = 0,
553*4882a593Smuzhiyun 		}, {
554*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE4,
555*4882a593Smuzhiyun 			.vmux   = CX25840_COMPOSITE4,
556*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
557*4882a593Smuzhiyun 			.gpio0  = 0,
558*4882a593Smuzhiyun 		} },
559*4882a593Smuzhiyun 	},
560*4882a593Smuzhiyun 	[CX23885_BOARD_MYGICA_X8507] = {
561*4882a593Smuzhiyun 		.name		= "Mygica X8502/X8507 ISDB-T",
562*4882a593Smuzhiyun 		.tuner_type = TUNER_XC5000,
563*4882a593Smuzhiyun 		.tuner_addr = 0x61,
564*4882a593Smuzhiyun 		.tuner_bus	= 1,
565*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
566*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
567*4882a593Smuzhiyun 		.input		= {
568*4882a593Smuzhiyun 			{
569*4882a593Smuzhiyun 				.type   = CX23885_VMUX_TELEVISION,
570*4882a593Smuzhiyun 				.vmux   = CX25840_COMPOSITE2,
571*4882a593Smuzhiyun 				.amux   = CX25840_AUDIO8,
572*4882a593Smuzhiyun 			},
573*4882a593Smuzhiyun 			{
574*4882a593Smuzhiyun 				.type   = CX23885_VMUX_COMPOSITE1,
575*4882a593Smuzhiyun 				.vmux   = CX25840_COMPOSITE8,
576*4882a593Smuzhiyun 				.amux   = CX25840_AUDIO7,
577*4882a593Smuzhiyun 			},
578*4882a593Smuzhiyun 			{
579*4882a593Smuzhiyun 				.type   = CX23885_VMUX_SVIDEO,
580*4882a593Smuzhiyun 				.vmux   = CX25840_SVIDEO_LUMA3 |
581*4882a593Smuzhiyun 						CX25840_SVIDEO_CHROMA4,
582*4882a593Smuzhiyun 				.amux   = CX25840_AUDIO7,
583*4882a593Smuzhiyun 			},
584*4882a593Smuzhiyun 			{
585*4882a593Smuzhiyun 				.type   = CX23885_VMUX_COMPONENT,
586*4882a593Smuzhiyun 				.vmux   = CX25840_COMPONENT_ON |
587*4882a593Smuzhiyun 					CX25840_VIN1_CH1 |
588*4882a593Smuzhiyun 					CX25840_VIN6_CH2 |
589*4882a593Smuzhiyun 					CX25840_VIN7_CH3,
590*4882a593Smuzhiyun 				.amux   = CX25840_AUDIO7,
591*4882a593Smuzhiyun 			},
592*4882a593Smuzhiyun 		},
593*4882a593Smuzhiyun 	},
594*4882a593Smuzhiyun 	[CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
595*4882a593Smuzhiyun 		.name		= "TerraTec Cinergy T PCIe Dual",
596*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
597*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
598*4882a593Smuzhiyun 	},
599*4882a593Smuzhiyun 	[CX23885_BOARD_TEVII_S471] = {
600*4882a593Smuzhiyun 		.name		= "TeVii S471",
601*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
602*4882a593Smuzhiyun 	},
603*4882a593Smuzhiyun 	[CX23885_BOARD_PROF_8000] = {
604*4882a593Smuzhiyun 		.name		= "Prof Revolution DVB-S2 8000",
605*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
606*4882a593Smuzhiyun 	},
607*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR4400] = {
608*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR4400/HVR5500",
609*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
610*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
611*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
612*4882a593Smuzhiyun 		.tuner_type	= TUNER_NXP_TDA18271,
613*4882a593Smuzhiyun 		.tuner_addr	= 0x60, /* 0xc0 >> 1 */
614*4882a593Smuzhiyun 		.tuner_bus	= 1,
615*4882a593Smuzhiyun 	},
616*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_STARBURST] = {
617*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV Starburst",
618*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
619*4882a593Smuzhiyun 	},
620*4882a593Smuzhiyun 	[CX23885_BOARD_AVERMEDIA_HC81R] = {
621*4882a593Smuzhiyun 		.name		= "AVerTV Hybrid Express Slim HC81R",
622*4882a593Smuzhiyun 		.tuner_type	= TUNER_XC2028,
623*4882a593Smuzhiyun 		.tuner_addr	= 0x61, /* 0xc2 >> 1 */
624*4882a593Smuzhiyun 		.tuner_bus	= 1,
625*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
626*4882a593Smuzhiyun 		.input          = {{
627*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
628*4882a593Smuzhiyun 			.vmux   = CX25840_VIN2_CH1 |
629*4882a593Smuzhiyun 				  CX25840_VIN5_CH2 |
630*4882a593Smuzhiyun 				  CX25840_NONE0_CH3 |
631*4882a593Smuzhiyun 				  CX25840_NONE1_CH3,
632*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO8,
633*4882a593Smuzhiyun 		}, {
634*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
635*4882a593Smuzhiyun 			.vmux   = CX25840_VIN8_CH1 |
636*4882a593Smuzhiyun 				  CX25840_NONE_CH2 |
637*4882a593Smuzhiyun 				  CX25840_VIN7_CH3 |
638*4882a593Smuzhiyun 				  CX25840_SVIDEO_ON,
639*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO6,
640*4882a593Smuzhiyun 		}, {
641*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPONENT,
642*4882a593Smuzhiyun 			.vmux   = CX25840_VIN1_CH1 |
643*4882a593Smuzhiyun 				  CX25840_NONE_CH2 |
644*4882a593Smuzhiyun 				  CX25840_NONE0_CH3 |
645*4882a593Smuzhiyun 				  CX25840_NONE1_CH3,
646*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO6,
647*4882a593Smuzhiyun 		} },
648*4882a593Smuzhiyun 	},
649*4882a593Smuzhiyun 	[CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = {
650*4882a593Smuzhiyun 		.name		= "DViCO FusionHDTV DVB-T Dual Express2",
651*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
652*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
653*4882a593Smuzhiyun 	},
654*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = {
655*4882a593Smuzhiyun 		.name		= "Hauppauge ImpactVCB-e",
656*4882a593Smuzhiyun 		.tuner_type	= TUNER_ABSENT,
657*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
658*4882a593Smuzhiyun 		.input          = {{
659*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
660*4882a593Smuzhiyun 			.vmux   = CX25840_VIN7_CH3 |
661*4882a593Smuzhiyun 				  CX25840_VIN4_CH2 |
662*4882a593Smuzhiyun 				  CX25840_VIN6_CH1,
663*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
664*4882a593Smuzhiyun 		}, {
665*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
666*4882a593Smuzhiyun 			.vmux   = CX25840_VIN7_CH3 |
667*4882a593Smuzhiyun 				  CX25840_VIN4_CH2 |
668*4882a593Smuzhiyun 				  CX25840_VIN8_CH1 |
669*4882a593Smuzhiyun 				  CX25840_SVIDEO_ON,
670*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
671*4882a593Smuzhiyun 		} },
672*4882a593Smuzhiyun 	},
673*4882a593Smuzhiyun 	[CX23885_BOARD_DVBSKY_T9580] = {
674*4882a593Smuzhiyun 		.name		= "DVBSky T9580",
675*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
676*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
677*4882a593Smuzhiyun 	},
678*4882a593Smuzhiyun 	[CX23885_BOARD_DVBSKY_T980C] = {
679*4882a593Smuzhiyun 		.name		= "DVBSky T980C",
680*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
681*4882a593Smuzhiyun 	},
682*4882a593Smuzhiyun 	[CX23885_BOARD_DVBSKY_S950C] = {
683*4882a593Smuzhiyun 		.name		= "DVBSky S950C",
684*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
685*4882a593Smuzhiyun 	},
686*4882a593Smuzhiyun 	[CX23885_BOARD_TT_CT2_4500_CI] = {
687*4882a593Smuzhiyun 		.name		= "Technotrend TT-budget CT2-4500 CI",
688*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
689*4882a593Smuzhiyun 	},
690*4882a593Smuzhiyun 	[CX23885_BOARD_DVBSKY_S950] = {
691*4882a593Smuzhiyun 		.name		= "DVBSky S950",
692*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
693*4882a593Smuzhiyun 	},
694*4882a593Smuzhiyun 	[CX23885_BOARD_DVBSKY_S952] = {
695*4882a593Smuzhiyun 		.name		= "DVBSky S952",
696*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
697*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
698*4882a593Smuzhiyun 	},
699*4882a593Smuzhiyun 	[CX23885_BOARD_DVBSKY_T982] = {
700*4882a593Smuzhiyun 		.name		= "DVBSky T982",
701*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
702*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
703*4882a593Smuzhiyun 	},
704*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR5525] = {
705*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR5525",
706*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
707*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
708*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
709*4882a593Smuzhiyun 		.tuner_type	= TUNER_ABSENT,
710*4882a593Smuzhiyun 		.force_bff	= 1,
711*4882a593Smuzhiyun 		.input		= {{
712*4882a593Smuzhiyun 			.type	= CX23885_VMUX_TELEVISION,
713*4882a593Smuzhiyun 			.vmux	=	CX25840_VIN7_CH3 |
714*4882a593Smuzhiyun 					CX25840_VIN5_CH2 |
715*4882a593Smuzhiyun 					CX25840_VIN2_CH1 |
716*4882a593Smuzhiyun 					CX25840_DIF_ON,
717*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO8,
718*4882a593Smuzhiyun 		} },
719*4882a593Smuzhiyun 	},
720*4882a593Smuzhiyun 	[CX23885_BOARD_VIEWCAST_260E] = {
721*4882a593Smuzhiyun 		.name		= "ViewCast 260e",
722*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
723*4882a593Smuzhiyun 		.force_bff	= 1,
724*4882a593Smuzhiyun 		.input          = {{
725*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
726*4882a593Smuzhiyun 			.vmux   = CX25840_VIN6_CH1,
727*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
728*4882a593Smuzhiyun 		}, {
729*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
730*4882a593Smuzhiyun 			.vmux   = CX25840_VIN7_CH3 |
731*4882a593Smuzhiyun 					CX25840_VIN5_CH1 |
732*4882a593Smuzhiyun 					CX25840_SVIDEO_ON,
733*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
734*4882a593Smuzhiyun 		}, {
735*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPONENT,
736*4882a593Smuzhiyun 			.vmux   = CX25840_VIN7_CH3 |
737*4882a593Smuzhiyun 					CX25840_VIN6_CH2 |
738*4882a593Smuzhiyun 					CX25840_VIN5_CH1 |
739*4882a593Smuzhiyun 					CX25840_COMPONENT_ON,
740*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
741*4882a593Smuzhiyun 		} },
742*4882a593Smuzhiyun 	},
743*4882a593Smuzhiyun 	[CX23885_BOARD_VIEWCAST_460E] = {
744*4882a593Smuzhiyun 		.name		= "ViewCast 460e",
745*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
746*4882a593Smuzhiyun 		.force_bff	= 1,
747*4882a593Smuzhiyun 		.input          = {{
748*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
749*4882a593Smuzhiyun 			.vmux   = CX25840_VIN4_CH1,
750*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
751*4882a593Smuzhiyun 		}, {
752*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
753*4882a593Smuzhiyun 			.vmux   = CX25840_VIN7_CH3 |
754*4882a593Smuzhiyun 					CX25840_VIN6_CH1 |
755*4882a593Smuzhiyun 					CX25840_SVIDEO_ON,
756*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
757*4882a593Smuzhiyun 		}, {
758*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPONENT,
759*4882a593Smuzhiyun 			.vmux   = CX25840_VIN7_CH3 |
760*4882a593Smuzhiyun 					CX25840_VIN6_CH1 |
761*4882a593Smuzhiyun 					CX25840_VIN5_CH2 |
762*4882a593Smuzhiyun 					CX25840_COMPONENT_ON,
763*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
764*4882a593Smuzhiyun 		}, {
765*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE2,
766*4882a593Smuzhiyun 			.vmux   = CX25840_VIN6_CH1,
767*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
768*4882a593Smuzhiyun 		} },
769*4882a593Smuzhiyun 	},
770*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_QUADHD_DVB] = {
771*4882a593Smuzhiyun 		.name         = "Hauppauge WinTV-QuadHD-DVB",
772*4882a593Smuzhiyun 		.porta        = CX23885_ANALOG_VIDEO,
773*4882a593Smuzhiyun 		.portb        = CX23885_MPEG_DVB,
774*4882a593Smuzhiyun 		.portc        = CX23885_MPEG_DVB,
775*4882a593Smuzhiyun 		.tuner_type	= TUNER_ABSENT,
776*4882a593Smuzhiyun 		.force_bff	= 1,
777*4882a593Smuzhiyun 		.input          = {{
778*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
779*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
780*4882a593Smuzhiyun 					CX25840_VIN5_CH2 |
781*4882a593Smuzhiyun 					CX25840_VIN2_CH1 |
782*4882a593Smuzhiyun 					CX25840_DIF_ON,
783*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO8,
784*4882a593Smuzhiyun 		} },
785*4882a593Smuzhiyun 	},
786*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885] = {
787*4882a593Smuzhiyun 		.name         = "Hauppauge WinTV-QuadHD-DVB(885)",
788*4882a593Smuzhiyun 		.portb        = CX23885_MPEG_DVB,
789*4882a593Smuzhiyun 		.portc        = CX23885_MPEG_DVB,
790*4882a593Smuzhiyun 		.tuner_type   = TUNER_ABSENT,
791*4882a593Smuzhiyun 	},
792*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC] = {
793*4882a593Smuzhiyun 		.name         = "Hauppauge WinTV-QuadHD-ATSC",
794*4882a593Smuzhiyun 		.porta        = CX23885_ANALOG_VIDEO,
795*4882a593Smuzhiyun 		.portb        = CX23885_MPEG_DVB,
796*4882a593Smuzhiyun 		.portc        = CX23885_MPEG_DVB,
797*4882a593Smuzhiyun 		.tuner_type	= TUNER_ABSENT,
798*4882a593Smuzhiyun 		.input          = {{
799*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
800*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
801*4882a593Smuzhiyun 					CX25840_VIN5_CH2 |
802*4882a593Smuzhiyun 					CX25840_VIN2_CH1 |
803*4882a593Smuzhiyun 					CX25840_DIF_ON,
804*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO8,
805*4882a593Smuzhiyun 		} },
806*4882a593Smuzhiyun 	},
807*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885] = {
808*4882a593Smuzhiyun 		.name         = "Hauppauge WinTV-QuadHD-ATSC(885)",
809*4882a593Smuzhiyun 		.portb        = CX23885_MPEG_DVB,
810*4882a593Smuzhiyun 		.portc        = CX23885_MPEG_DVB,
811*4882a593Smuzhiyun 		.tuner_type   = TUNER_ABSENT,
812*4882a593Smuzhiyun 	},
813*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_HVR1265_K4] = {
814*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-HVR-1265(161111)",
815*4882a593Smuzhiyun 		.porta          = CX23885_ANALOG_VIDEO,
816*4882a593Smuzhiyun 		.portc		= CX23885_MPEG_DVB,
817*4882a593Smuzhiyun 		.tuner_type     = TUNER_ABSENT,
818*4882a593Smuzhiyun 		.input          = {{
819*4882a593Smuzhiyun 			.type   = CX23885_VMUX_TELEVISION,
820*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
821*4882a593Smuzhiyun 					CX25840_VIN5_CH2 |
822*4882a593Smuzhiyun 					CX25840_VIN2_CH1 |
823*4882a593Smuzhiyun 					CX25840_DIF_ON,
824*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO8,
825*4882a593Smuzhiyun 		}, {
826*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
827*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
828*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
829*4882a593Smuzhiyun 					CX25840_VIN6_CH1,
830*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
831*4882a593Smuzhiyun 		}, {
832*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
833*4882a593Smuzhiyun 			.vmux   =	CX25840_VIN7_CH3 |
834*4882a593Smuzhiyun 					CX25840_VIN4_CH2 |
835*4882a593Smuzhiyun 					CX25840_VIN8_CH1 |
836*4882a593Smuzhiyun 					CX25840_SVIDEO_ON,
837*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
838*4882a593Smuzhiyun 		} },
839*4882a593Smuzhiyun 	},
840*4882a593Smuzhiyun 	[CX23885_BOARD_HAUPPAUGE_STARBURST2] = {
841*4882a593Smuzhiyun 		.name		= "Hauppauge WinTV-Starburst2",
842*4882a593Smuzhiyun 		.portb		= CX23885_MPEG_DVB,
843*4882a593Smuzhiyun 	},
844*4882a593Smuzhiyun 	[CX23885_BOARD_AVERMEDIA_CE310B] = {
845*4882a593Smuzhiyun 		.name		= "AVerMedia CE310B",
846*4882a593Smuzhiyun 		.porta		= CX23885_ANALOG_VIDEO,
847*4882a593Smuzhiyun 		.force_bff	= 1,
848*4882a593Smuzhiyun 		.input          = {{
849*4882a593Smuzhiyun 			.type   = CX23885_VMUX_COMPOSITE1,
850*4882a593Smuzhiyun 			.vmux   = CX25840_VIN1_CH1 |
851*4882a593Smuzhiyun 				  CX25840_NONE_CH2 |
852*4882a593Smuzhiyun 				  CX25840_NONE0_CH3,
853*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
854*4882a593Smuzhiyun 		}, {
855*4882a593Smuzhiyun 			.type   = CX23885_VMUX_SVIDEO,
856*4882a593Smuzhiyun 			.vmux   = CX25840_VIN8_CH1 |
857*4882a593Smuzhiyun 				  CX25840_NONE_CH2 |
858*4882a593Smuzhiyun 				  CX25840_VIN7_CH3 |
859*4882a593Smuzhiyun 				  CX25840_SVIDEO_ON,
860*4882a593Smuzhiyun 			.amux   = CX25840_AUDIO7,
861*4882a593Smuzhiyun 		} },
862*4882a593Smuzhiyun 	},
863*4882a593Smuzhiyun };
864*4882a593Smuzhiyun const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
865*4882a593Smuzhiyun 
866*4882a593Smuzhiyun /* ------------------------------------------------------------------ */
867*4882a593Smuzhiyun /* PCI subsystem IDs                                                  */
868*4882a593Smuzhiyun 
869*4882a593Smuzhiyun struct cx23885_subid cx23885_subids[] = {
870*4882a593Smuzhiyun 	{
871*4882a593Smuzhiyun 		.subvendor = 0x0070,
872*4882a593Smuzhiyun 		.subdevice = 0x3400,
873*4882a593Smuzhiyun 		.card      = CX23885_BOARD_UNKNOWN,
874*4882a593Smuzhiyun 	}, {
875*4882a593Smuzhiyun 		.subvendor = 0x0070,
876*4882a593Smuzhiyun 		.subdevice = 0x7600,
877*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
878*4882a593Smuzhiyun 	}, {
879*4882a593Smuzhiyun 		.subvendor = 0x0070,
880*4882a593Smuzhiyun 		.subdevice = 0x7800,
881*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1800,
882*4882a593Smuzhiyun 	}, {
883*4882a593Smuzhiyun 		.subvendor = 0x0070,
884*4882a593Smuzhiyun 		.subdevice = 0x7801,
885*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1800,
886*4882a593Smuzhiyun 	}, {
887*4882a593Smuzhiyun 		.subvendor = 0x0070,
888*4882a593Smuzhiyun 		.subdevice = 0x7809,
889*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1800,
890*4882a593Smuzhiyun 	}, {
891*4882a593Smuzhiyun 		.subvendor = 0x0070,
892*4882a593Smuzhiyun 		.subdevice = 0x7911,
893*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1250,
894*4882a593Smuzhiyun 	}, {
895*4882a593Smuzhiyun 		.subvendor = 0x18ac,
896*4882a593Smuzhiyun 		.subdevice = 0xd500,
897*4882a593Smuzhiyun 		.card      = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
898*4882a593Smuzhiyun 	}, {
899*4882a593Smuzhiyun 		.subvendor = 0x0070,
900*4882a593Smuzhiyun 		.subdevice = 0x7790,
901*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
902*4882a593Smuzhiyun 	}, {
903*4882a593Smuzhiyun 		.subvendor = 0x0070,
904*4882a593Smuzhiyun 		.subdevice = 0x7797,
905*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
906*4882a593Smuzhiyun 	}, {
907*4882a593Smuzhiyun 		.subvendor = 0x0070,
908*4882a593Smuzhiyun 		.subdevice = 0x7710,
909*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1500,
910*4882a593Smuzhiyun 	}, {
911*4882a593Smuzhiyun 		.subvendor = 0x0070,
912*4882a593Smuzhiyun 		.subdevice = 0x7717,
913*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1500,
914*4882a593Smuzhiyun 	}, {
915*4882a593Smuzhiyun 		.subvendor = 0x0070,
916*4882a593Smuzhiyun 		.subdevice = 0x71d1,
917*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1200,
918*4882a593Smuzhiyun 	}, {
919*4882a593Smuzhiyun 		.subvendor = 0x0070,
920*4882a593Smuzhiyun 		.subdevice = 0x71d3,
921*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1200,
922*4882a593Smuzhiyun 	}, {
923*4882a593Smuzhiyun 		.subvendor = 0x0070,
924*4882a593Smuzhiyun 		.subdevice = 0x8101,
925*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1700,
926*4882a593Smuzhiyun 	}, {
927*4882a593Smuzhiyun 		.subvendor = 0x0070,
928*4882a593Smuzhiyun 		.subdevice = 0x8010,
929*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1400,
930*4882a593Smuzhiyun 	}, {
931*4882a593Smuzhiyun 		.subvendor = 0x18ac,
932*4882a593Smuzhiyun 		.subdevice = 0xd618,
933*4882a593Smuzhiyun 		.card      = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
934*4882a593Smuzhiyun 	}, {
935*4882a593Smuzhiyun 		.subvendor = 0x18ac,
936*4882a593Smuzhiyun 		.subdevice = 0xdb78,
937*4882a593Smuzhiyun 		.card      = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
938*4882a593Smuzhiyun 	}, {
939*4882a593Smuzhiyun 		.subvendor = 0x107d,
940*4882a593Smuzhiyun 		.subdevice = 0x6681,
941*4882a593Smuzhiyun 		.card      = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
942*4882a593Smuzhiyun 	}, {
943*4882a593Smuzhiyun 		.subvendor = 0x107d,
944*4882a593Smuzhiyun 		.subdevice = 0x6f21,
945*4882a593Smuzhiyun 		.card      = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200,
946*4882a593Smuzhiyun 	}, {
947*4882a593Smuzhiyun 		.subvendor = 0x107d,
948*4882a593Smuzhiyun 		.subdevice = 0x6f39,
949*4882a593Smuzhiyun 		.card	   = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
950*4882a593Smuzhiyun 	}, {
951*4882a593Smuzhiyun 		.subvendor = 0x185b,
952*4882a593Smuzhiyun 		.subdevice = 0xe800,
953*4882a593Smuzhiyun 		.card      = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
954*4882a593Smuzhiyun 	}, {
955*4882a593Smuzhiyun 		.subvendor = 0x6920,
956*4882a593Smuzhiyun 		.subdevice = 0x8888,
957*4882a593Smuzhiyun 		.card      = CX23885_BOARD_TBS_6920,
958*4882a593Smuzhiyun 	}, {
959*4882a593Smuzhiyun 		.subvendor = 0x6980,
960*4882a593Smuzhiyun 		.subdevice = 0x8888,
961*4882a593Smuzhiyun 		.card      = CX23885_BOARD_TBS_6980,
962*4882a593Smuzhiyun 	}, {
963*4882a593Smuzhiyun 		.subvendor = 0x6981,
964*4882a593Smuzhiyun 		.subdevice = 0x8888,
965*4882a593Smuzhiyun 		.card      = CX23885_BOARD_TBS_6981,
966*4882a593Smuzhiyun 	}, {
967*4882a593Smuzhiyun 		.subvendor = 0xd470,
968*4882a593Smuzhiyun 		.subdevice = 0x9022,
969*4882a593Smuzhiyun 		.card      = CX23885_BOARD_TEVII_S470,
970*4882a593Smuzhiyun 	}, {
971*4882a593Smuzhiyun 		.subvendor = 0x0001,
972*4882a593Smuzhiyun 		.subdevice = 0x2005,
973*4882a593Smuzhiyun 		.card      = CX23885_BOARD_DVBWORLD_2005,
974*4882a593Smuzhiyun 	}, {
975*4882a593Smuzhiyun 		.subvendor = 0x1b55,
976*4882a593Smuzhiyun 		.subdevice = 0x2a2c,
977*4882a593Smuzhiyun 		.card      = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
978*4882a593Smuzhiyun 	}, {
979*4882a593Smuzhiyun 		.subvendor = 0x0070,
980*4882a593Smuzhiyun 		.subdevice = 0x2211,
981*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1270,
982*4882a593Smuzhiyun 	}, {
983*4882a593Smuzhiyun 		.subvendor = 0x0070,
984*4882a593Smuzhiyun 		.subdevice = 0x2215,
985*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1275,
986*4882a593Smuzhiyun 	}, {
987*4882a593Smuzhiyun 		.subvendor = 0x0070,
988*4882a593Smuzhiyun 		.subdevice = 0x221d,
989*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1275,
990*4882a593Smuzhiyun 	}, {
991*4882a593Smuzhiyun 		.subvendor = 0x0070,
992*4882a593Smuzhiyun 		.subdevice = 0x2251,
993*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1255,
994*4882a593Smuzhiyun 	}, {
995*4882a593Smuzhiyun 		.subvendor = 0x0070,
996*4882a593Smuzhiyun 		.subdevice = 0x2259,
997*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
998*4882a593Smuzhiyun 	}, {
999*4882a593Smuzhiyun 		.subvendor = 0x0070,
1000*4882a593Smuzhiyun 		.subdevice = 0x2291,
1001*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1210,
1002*4882a593Smuzhiyun 	}, {
1003*4882a593Smuzhiyun 		.subvendor = 0x0070,
1004*4882a593Smuzhiyun 		.subdevice = 0x2295,
1005*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1210,
1006*4882a593Smuzhiyun 	}, {
1007*4882a593Smuzhiyun 		.subvendor = 0x0070,
1008*4882a593Smuzhiyun 		.subdevice = 0x2299,
1009*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1210,
1010*4882a593Smuzhiyun 	}, {
1011*4882a593Smuzhiyun 		.subvendor = 0x0070,
1012*4882a593Smuzhiyun 		.subdevice = 0x229d,
1013*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
1014*4882a593Smuzhiyun 	}, {
1015*4882a593Smuzhiyun 		.subvendor = 0x0070,
1016*4882a593Smuzhiyun 		.subdevice = 0x22f0,
1017*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1210,
1018*4882a593Smuzhiyun 	}, {
1019*4882a593Smuzhiyun 		.subvendor = 0x0070,
1020*4882a593Smuzhiyun 		.subdevice = 0x22f1,
1021*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1255,
1022*4882a593Smuzhiyun 	}, {
1023*4882a593Smuzhiyun 		.subvendor = 0x0070,
1024*4882a593Smuzhiyun 		.subdevice = 0x22f2,
1025*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1275,
1026*4882a593Smuzhiyun 	}, {
1027*4882a593Smuzhiyun 		.subvendor = 0x0070,
1028*4882a593Smuzhiyun 		.subdevice = 0x22f3,
1029*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
1030*4882a593Smuzhiyun 	}, {
1031*4882a593Smuzhiyun 		.subvendor = 0x0070,
1032*4882a593Smuzhiyun 		.subdevice = 0x22f4,
1033*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1210,
1034*4882a593Smuzhiyun 	}, {
1035*4882a593Smuzhiyun 		.subvendor = 0x0070,
1036*4882a593Smuzhiyun 		.subdevice = 0x22f5,
1037*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
1038*4882a593Smuzhiyun 	}, {
1039*4882a593Smuzhiyun 		.subvendor = 0x14f1,
1040*4882a593Smuzhiyun 		.subdevice = 0x8651,
1041*4882a593Smuzhiyun 		.card      = CX23885_BOARD_MYGICA_X8506,
1042*4882a593Smuzhiyun 	}, {
1043*4882a593Smuzhiyun 		.subvendor = 0x14f1,
1044*4882a593Smuzhiyun 		.subdevice = 0x8657,
1045*4882a593Smuzhiyun 		.card      = CX23885_BOARD_MAGICPRO_PROHDTVE2,
1046*4882a593Smuzhiyun 	}, {
1047*4882a593Smuzhiyun 		.subvendor = 0x0070,
1048*4882a593Smuzhiyun 		.subdevice = 0x8541,
1049*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1850,
1050*4882a593Smuzhiyun 	}, {
1051*4882a593Smuzhiyun 		.subvendor = 0x1858,
1052*4882a593Smuzhiyun 		.subdevice = 0xe800,
1053*4882a593Smuzhiyun 		.card      = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
1054*4882a593Smuzhiyun 	}, {
1055*4882a593Smuzhiyun 		.subvendor = 0x0070,
1056*4882a593Smuzhiyun 		.subdevice = 0x8551,
1057*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1290,
1058*4882a593Smuzhiyun 	}, {
1059*4882a593Smuzhiyun 		.subvendor = 0x14f1,
1060*4882a593Smuzhiyun 		.subdevice = 0x8578,
1061*4882a593Smuzhiyun 		.card      = CX23885_BOARD_MYGICA_X8558PRO,
1062*4882a593Smuzhiyun 	}, {
1063*4882a593Smuzhiyun 		.subvendor = 0x107d,
1064*4882a593Smuzhiyun 		.subdevice = 0x6f22,
1065*4882a593Smuzhiyun 		.card      = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
1066*4882a593Smuzhiyun 	}, {
1067*4882a593Smuzhiyun 		.subvendor = 0x5654,
1068*4882a593Smuzhiyun 		.subdevice = 0x2390,
1069*4882a593Smuzhiyun 		.card      = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
1070*4882a593Smuzhiyun 	}, {
1071*4882a593Smuzhiyun 		.subvendor = 0x1b55,
1072*4882a593Smuzhiyun 		.subdevice = 0xe2e4,
1073*4882a593Smuzhiyun 		.card      = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
1074*4882a593Smuzhiyun 	}, {
1075*4882a593Smuzhiyun 		.subvendor = 0x14f1,
1076*4882a593Smuzhiyun 		.subdevice = 0x8502,
1077*4882a593Smuzhiyun 		.card      = CX23885_BOARD_MYGICA_X8507,
1078*4882a593Smuzhiyun 	}, {
1079*4882a593Smuzhiyun 		.subvendor = 0x153b,
1080*4882a593Smuzhiyun 		.subdevice = 0x117e,
1081*4882a593Smuzhiyun 		.card      = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
1082*4882a593Smuzhiyun 	}, {
1083*4882a593Smuzhiyun 		.subvendor = 0xd471,
1084*4882a593Smuzhiyun 		.subdevice = 0x9022,
1085*4882a593Smuzhiyun 		.card      = CX23885_BOARD_TEVII_S471,
1086*4882a593Smuzhiyun 	}, {
1087*4882a593Smuzhiyun 		.subvendor = 0x8000,
1088*4882a593Smuzhiyun 		.subdevice = 0x3034,
1089*4882a593Smuzhiyun 		.card      = CX23885_BOARD_PROF_8000,
1090*4882a593Smuzhiyun 	}, {
1091*4882a593Smuzhiyun 		.subvendor = 0x0070,
1092*4882a593Smuzhiyun 		.subdevice = 0xc108,
1093*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-4400 (Model 121xxx, Hybrid DVB-T/S2, IR) */
1094*4882a593Smuzhiyun 	}, {
1095*4882a593Smuzhiyun 		.subvendor = 0x0070,
1096*4882a593Smuzhiyun 		.subdevice = 0xc138,
1097*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */
1098*4882a593Smuzhiyun 	}, {
1099*4882a593Smuzhiyun 		.subvendor = 0x0070,
1100*4882a593Smuzhiyun 		.subdevice = 0xc12a,
1101*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_STARBURST, /* Hauppauge WinTV Starburst (Model 121x00, DVB-S2, IR) */
1102*4882a593Smuzhiyun 	}, {
1103*4882a593Smuzhiyun 		.subvendor = 0x0070,
1104*4882a593Smuzhiyun 		.subdevice = 0xc1f8,
1105*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */
1106*4882a593Smuzhiyun 	}, {
1107*4882a593Smuzhiyun 		.subvendor = 0x1461,
1108*4882a593Smuzhiyun 		.subdevice = 0xd939,
1109*4882a593Smuzhiyun 		.card      = CX23885_BOARD_AVERMEDIA_HC81R,
1110*4882a593Smuzhiyun 	}, {
1111*4882a593Smuzhiyun 		.subvendor = 0x0070,
1112*4882a593Smuzhiyun 		.subdevice = 0x7133,
1113*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE,
1114*4882a593Smuzhiyun 	}, {
1115*4882a593Smuzhiyun 		.subvendor = 0x0070,
1116*4882a593Smuzhiyun 		.subdevice = 0x7137,
1117*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE,
1118*4882a593Smuzhiyun 	}, {
1119*4882a593Smuzhiyun 		.subvendor = 0x18ac,
1120*4882a593Smuzhiyun 		.subdevice = 0xdb98,
1121*4882a593Smuzhiyun 		.card      = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2,
1122*4882a593Smuzhiyun 	}, {
1123*4882a593Smuzhiyun 		.subvendor = 0x4254,
1124*4882a593Smuzhiyun 		.subdevice = 0x9580,
1125*4882a593Smuzhiyun 		.card      = CX23885_BOARD_DVBSKY_T9580,
1126*4882a593Smuzhiyun 	}, {
1127*4882a593Smuzhiyun 		.subvendor = 0x4254,
1128*4882a593Smuzhiyun 		.subdevice = 0x980c,
1129*4882a593Smuzhiyun 		.card      = CX23885_BOARD_DVBSKY_T980C,
1130*4882a593Smuzhiyun 	}, {
1131*4882a593Smuzhiyun 		.subvendor = 0x4254,
1132*4882a593Smuzhiyun 		.subdevice = 0x950c,
1133*4882a593Smuzhiyun 		.card      = CX23885_BOARD_DVBSKY_S950C,
1134*4882a593Smuzhiyun 	}, {
1135*4882a593Smuzhiyun 		.subvendor = 0x13c2,
1136*4882a593Smuzhiyun 		.subdevice = 0x3013,
1137*4882a593Smuzhiyun 		.card      = CX23885_BOARD_TT_CT2_4500_CI,
1138*4882a593Smuzhiyun 	}, {
1139*4882a593Smuzhiyun 		.subvendor = 0x4254,
1140*4882a593Smuzhiyun 		.subdevice = 0x0950,
1141*4882a593Smuzhiyun 		.card      = CX23885_BOARD_DVBSKY_S950,
1142*4882a593Smuzhiyun 	}, {
1143*4882a593Smuzhiyun 		.subvendor = 0x4254,
1144*4882a593Smuzhiyun 		.subdevice = 0x0952,
1145*4882a593Smuzhiyun 		.card      = CX23885_BOARD_DVBSKY_S952,
1146*4882a593Smuzhiyun 	}, {
1147*4882a593Smuzhiyun 		.subvendor = 0x4254,
1148*4882a593Smuzhiyun 		.subdevice = 0x0982,
1149*4882a593Smuzhiyun 		.card      = CX23885_BOARD_DVBSKY_T982,
1150*4882a593Smuzhiyun 	}, {
1151*4882a593Smuzhiyun 		.subvendor = 0x0070,
1152*4882a593Smuzhiyun 		.subdevice = 0xf038,
1153*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR5525,
1154*4882a593Smuzhiyun 	}, {
1155*4882a593Smuzhiyun 		.subvendor = 0x1576,
1156*4882a593Smuzhiyun 		.subdevice = 0x0260,
1157*4882a593Smuzhiyun 		.card      = CX23885_BOARD_VIEWCAST_260E,
1158*4882a593Smuzhiyun 	}, {
1159*4882a593Smuzhiyun 		.subvendor = 0x1576,
1160*4882a593Smuzhiyun 		.subdevice = 0x0460,
1161*4882a593Smuzhiyun 		.card      = CX23885_BOARD_VIEWCAST_460E,
1162*4882a593Smuzhiyun 	}, {
1163*4882a593Smuzhiyun 		.subvendor = 0x0070,
1164*4882a593Smuzhiyun 		.subdevice = 0x6a28,
1165*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 1 */
1166*4882a593Smuzhiyun 	}, {
1167*4882a593Smuzhiyun 		.subvendor = 0x0070,
1168*4882a593Smuzhiyun 		.subdevice = 0x6b28,
1169*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 2 */
1170*4882a593Smuzhiyun 	}, {
1171*4882a593Smuzhiyun 		.subvendor = 0x0070,
1172*4882a593Smuzhiyun 		.subdevice = 0x6a18,
1173*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 1 */
1174*4882a593Smuzhiyun 	}, {
1175*4882a593Smuzhiyun 		.subvendor = 0x0070,
1176*4882a593Smuzhiyun 		.subdevice = 0x6b18,
1177*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 2 */
1178*4882a593Smuzhiyun 	}, {
1179*4882a593Smuzhiyun 		.subvendor = 0x0070,
1180*4882a593Smuzhiyun 		.subdevice = 0x2a18,
1181*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_HVR1265_K4, /* Hauppauge WinTV HVR-1265 (Model 161xx1, Hybrid ATSC/QAM-B) */
1182*4882a593Smuzhiyun 	}, {
1183*4882a593Smuzhiyun 		.subvendor = 0x0070,
1184*4882a593Smuzhiyun 		.subdevice = 0xf02a,
1185*4882a593Smuzhiyun 		.card      = CX23885_BOARD_HAUPPAUGE_STARBURST2,
1186*4882a593Smuzhiyun 	}, {
1187*4882a593Smuzhiyun 		.subvendor = 0x1461,
1188*4882a593Smuzhiyun 		.subdevice = 0x3100,
1189*4882a593Smuzhiyun 		.card      = CX23885_BOARD_AVERMEDIA_CE310B,
1190*4882a593Smuzhiyun 	},
1191*4882a593Smuzhiyun };
1192*4882a593Smuzhiyun const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
1193*4882a593Smuzhiyun 
cx23885_card_list(struct cx23885_dev * dev)1194*4882a593Smuzhiyun void cx23885_card_list(struct cx23885_dev *dev)
1195*4882a593Smuzhiyun {
1196*4882a593Smuzhiyun 	int i;
1197*4882a593Smuzhiyun 
1198*4882a593Smuzhiyun 	if (0 == dev->pci->subsystem_vendor &&
1199*4882a593Smuzhiyun 	    0 == dev->pci->subsystem_device) {
1200*4882a593Smuzhiyun 		pr_info("%s: Board has no valid PCIe Subsystem ID and can't\n"
1201*4882a593Smuzhiyun 			"%s: be autodetected. Pass card=<n> insmod option\n"
1202*4882a593Smuzhiyun 			"%s: to workaround that. Redirect complaints to the\n"
1203*4882a593Smuzhiyun 			"%s: vendor of the TV card.  Best regards,\n"
1204*4882a593Smuzhiyun 			"%s:         -- tux\n",
1205*4882a593Smuzhiyun 			dev->name, dev->name, dev->name, dev->name, dev->name);
1206*4882a593Smuzhiyun 	} else {
1207*4882a593Smuzhiyun 		pr_info("%s: Your board isn't known (yet) to the driver.\n"
1208*4882a593Smuzhiyun 			"%s: Try to pick one of the existing card configs via\n"
1209*4882a593Smuzhiyun 			"%s: card=<n> insmod option.  Updating to the latest\n"
1210*4882a593Smuzhiyun 			"%s: version might help as well.\n",
1211*4882a593Smuzhiyun 			dev->name, dev->name, dev->name, dev->name);
1212*4882a593Smuzhiyun 	}
1213*4882a593Smuzhiyun 	pr_info("%s: Here is a list of valid choices for the card=<n> insmod option:\n",
1214*4882a593Smuzhiyun 	       dev->name);
1215*4882a593Smuzhiyun 	for (i = 0; i < cx23885_bcount; i++)
1216*4882a593Smuzhiyun 		pr_info("%s:    card=%d -> %s\n",
1217*4882a593Smuzhiyun 			dev->name, i, cx23885_boards[i].name);
1218*4882a593Smuzhiyun }
1219*4882a593Smuzhiyun 
viewcast_eeprom(struct cx23885_dev * dev,u8 * eeprom_data)1220*4882a593Smuzhiyun static void viewcast_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
1221*4882a593Smuzhiyun {
1222*4882a593Smuzhiyun 	u32 sn;
1223*4882a593Smuzhiyun 
1224*4882a593Smuzhiyun 	/* The serial number record begins with tag 0x59 */
1225*4882a593Smuzhiyun 	if (*(eeprom_data + 0x00) != 0x59) {
1226*4882a593Smuzhiyun 		pr_info("%s() eeprom records are undefined, no serial number\n",
1227*4882a593Smuzhiyun 			__func__);
1228*4882a593Smuzhiyun 		return;
1229*4882a593Smuzhiyun 	}
1230*4882a593Smuzhiyun 
1231*4882a593Smuzhiyun 	sn =	(*(eeprom_data + 0x06) << 24) |
1232*4882a593Smuzhiyun 		(*(eeprom_data + 0x05) << 16) |
1233*4882a593Smuzhiyun 		(*(eeprom_data + 0x04) << 8) |
1234*4882a593Smuzhiyun 		(*(eeprom_data + 0x03));
1235*4882a593Smuzhiyun 
1236*4882a593Smuzhiyun 	pr_info("%s: card '%s' sn# MM%d\n",
1237*4882a593Smuzhiyun 		dev->name,
1238*4882a593Smuzhiyun 		cx23885_boards[dev->board].name,
1239*4882a593Smuzhiyun 		sn);
1240*4882a593Smuzhiyun }
1241*4882a593Smuzhiyun 
hauppauge_eeprom(struct cx23885_dev * dev,u8 * eeprom_data)1242*4882a593Smuzhiyun static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
1243*4882a593Smuzhiyun {
1244*4882a593Smuzhiyun 	struct tveeprom tv;
1245*4882a593Smuzhiyun 
1246*4882a593Smuzhiyun 	tveeprom_hauppauge_analog(&tv, eeprom_data);
1247*4882a593Smuzhiyun 
1248*4882a593Smuzhiyun 	/* Make sure we support the board model */
1249*4882a593Smuzhiyun 	switch (tv.model) {
1250*4882a593Smuzhiyun 	case 22001:
1251*4882a593Smuzhiyun 		/* WinTV-HVR1270 (PCIe, Retail, half height)
1252*4882a593Smuzhiyun 		 * ATSC/QAM and basic analog, IR Blast */
1253*4882a593Smuzhiyun 	case 22009:
1254*4882a593Smuzhiyun 		/* WinTV-HVR1210 (PCIe, Retail, half height)
1255*4882a593Smuzhiyun 		 * DVB-T and basic analog, IR Blast */
1256*4882a593Smuzhiyun 	case 22011:
1257*4882a593Smuzhiyun 		/* WinTV-HVR1270 (PCIe, Retail, half height)
1258*4882a593Smuzhiyun 		 * ATSC/QAM and basic analog, IR Recv */
1259*4882a593Smuzhiyun 	case 22019:
1260*4882a593Smuzhiyun 		/* WinTV-HVR1210 (PCIe, Retail, half height)
1261*4882a593Smuzhiyun 		 * DVB-T and basic analog, IR Recv */
1262*4882a593Smuzhiyun 	case 22021:
1263*4882a593Smuzhiyun 		/* WinTV-HVR1275 (PCIe, Retail, half height)
1264*4882a593Smuzhiyun 		 * ATSC/QAM and basic analog, IR Recv */
1265*4882a593Smuzhiyun 	case 22029:
1266*4882a593Smuzhiyun 		/* WinTV-HVR1210 (PCIe, Retail, half height)
1267*4882a593Smuzhiyun 		 * DVB-T and basic analog, IR Recv */
1268*4882a593Smuzhiyun 	case 22101:
1269*4882a593Smuzhiyun 		/* WinTV-HVR1270 (PCIe, Retail, full height)
1270*4882a593Smuzhiyun 		 * ATSC/QAM and basic analog, IR Blast */
1271*4882a593Smuzhiyun 	case 22109:
1272*4882a593Smuzhiyun 		/* WinTV-HVR1210 (PCIe, Retail, full height)
1273*4882a593Smuzhiyun 		 * DVB-T and basic analog, IR Blast */
1274*4882a593Smuzhiyun 	case 22111:
1275*4882a593Smuzhiyun 		/* WinTV-HVR1270 (PCIe, Retail, full height)
1276*4882a593Smuzhiyun 		 * ATSC/QAM and basic analog, IR Recv */
1277*4882a593Smuzhiyun 	case 22119:
1278*4882a593Smuzhiyun 		/* WinTV-HVR1210 (PCIe, Retail, full height)
1279*4882a593Smuzhiyun 		 * DVB-T and basic analog, IR Recv */
1280*4882a593Smuzhiyun 	case 22121:
1281*4882a593Smuzhiyun 		/* WinTV-HVR1275 (PCIe, Retail, full height)
1282*4882a593Smuzhiyun 		 * ATSC/QAM and basic analog, IR Recv */
1283*4882a593Smuzhiyun 	case 22129:
1284*4882a593Smuzhiyun 		/* WinTV-HVR1210 (PCIe, Retail, full height)
1285*4882a593Smuzhiyun 		 * DVB-T and basic analog, IR Recv */
1286*4882a593Smuzhiyun 	case 71009:
1287*4882a593Smuzhiyun 		/* WinTV-HVR1200 (PCIe, Retail, full height)
1288*4882a593Smuzhiyun 		 * DVB-T and basic analog */
1289*4882a593Smuzhiyun 	case 71100:
1290*4882a593Smuzhiyun 		/* WinTV-ImpactVCB-e (PCIe, Retail, half height)
1291*4882a593Smuzhiyun 		 * Basic analog */
1292*4882a593Smuzhiyun 	case 71359:
1293*4882a593Smuzhiyun 		/* WinTV-HVR1200 (PCIe, OEM, half height)
1294*4882a593Smuzhiyun 		 * DVB-T and basic analog */
1295*4882a593Smuzhiyun 	case 71439:
1296*4882a593Smuzhiyun 		/* WinTV-HVR1200 (PCIe, OEM, half height)
1297*4882a593Smuzhiyun 		 * DVB-T and basic analog */
1298*4882a593Smuzhiyun 	case 71449:
1299*4882a593Smuzhiyun 		/* WinTV-HVR1200 (PCIe, OEM, full height)
1300*4882a593Smuzhiyun 		 * DVB-T and basic analog */
1301*4882a593Smuzhiyun 	case 71939:
1302*4882a593Smuzhiyun 		/* WinTV-HVR1200 (PCIe, OEM, half height)
1303*4882a593Smuzhiyun 		 * DVB-T and basic analog */
1304*4882a593Smuzhiyun 	case 71949:
1305*4882a593Smuzhiyun 		/* WinTV-HVR1200 (PCIe, OEM, full height)
1306*4882a593Smuzhiyun 		 * DVB-T and basic analog */
1307*4882a593Smuzhiyun 	case 71959:
1308*4882a593Smuzhiyun 		/* WinTV-HVR1200 (PCIe, OEM, full height)
1309*4882a593Smuzhiyun 		 * DVB-T and basic analog */
1310*4882a593Smuzhiyun 	case 71979:
1311*4882a593Smuzhiyun 		/* WinTV-HVR1200 (PCIe, OEM, half height)
1312*4882a593Smuzhiyun 		 * DVB-T and basic analog */
1313*4882a593Smuzhiyun 	case 71999:
1314*4882a593Smuzhiyun 		/* WinTV-HVR1200 (PCIe, OEM, full height)
1315*4882a593Smuzhiyun 		 * DVB-T and basic analog */
1316*4882a593Smuzhiyun 	case 76601:
1317*4882a593Smuzhiyun 		/* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
1318*4882a593Smuzhiyun 			channel ATSC and MPEG2 HW Encoder */
1319*4882a593Smuzhiyun 	case 77001:
1320*4882a593Smuzhiyun 		/* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
1321*4882a593Smuzhiyun 			and Basic analog */
1322*4882a593Smuzhiyun 	case 77011:
1323*4882a593Smuzhiyun 		/* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
1324*4882a593Smuzhiyun 			and Basic analog */
1325*4882a593Smuzhiyun 	case 77041:
1326*4882a593Smuzhiyun 		/* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
1327*4882a593Smuzhiyun 			and Basic analog */
1328*4882a593Smuzhiyun 	case 77051:
1329*4882a593Smuzhiyun 		/* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
1330*4882a593Smuzhiyun 			and Basic analog */
1331*4882a593Smuzhiyun 	case 78011:
1332*4882a593Smuzhiyun 		/* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
1333*4882a593Smuzhiyun 			Dual channel ATSC and MPEG2 HW Encoder */
1334*4882a593Smuzhiyun 	case 78501:
1335*4882a593Smuzhiyun 		/* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
1336*4882a593Smuzhiyun 			Dual channel ATSC and MPEG2 HW Encoder */
1337*4882a593Smuzhiyun 	case 78521:
1338*4882a593Smuzhiyun 		/* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
1339*4882a593Smuzhiyun 			Dual channel ATSC and MPEG2 HW Encoder */
1340*4882a593Smuzhiyun 	case 78531:
1341*4882a593Smuzhiyun 		/* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
1342*4882a593Smuzhiyun 			Dual channel ATSC and MPEG2 HW Encoder */
1343*4882a593Smuzhiyun 	case 78631:
1344*4882a593Smuzhiyun 		/* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
1345*4882a593Smuzhiyun 			Dual channel ATSC and MPEG2 HW Encoder */
1346*4882a593Smuzhiyun 	case 79001:
1347*4882a593Smuzhiyun 		/* WinTV-HVR1250 (PCIe, Retail, IR, full height,
1348*4882a593Smuzhiyun 			ATSC and Basic analog */
1349*4882a593Smuzhiyun 	case 79101:
1350*4882a593Smuzhiyun 		/* WinTV-HVR1250 (PCIe, Retail, IR, half height,
1351*4882a593Smuzhiyun 			ATSC and Basic analog */
1352*4882a593Smuzhiyun 	case 79501:
1353*4882a593Smuzhiyun 		/* WinTV-HVR1250 (PCIe, No IR, half height,
1354*4882a593Smuzhiyun 			ATSC [at least] and Basic analog) */
1355*4882a593Smuzhiyun 	case 79561:
1356*4882a593Smuzhiyun 		/* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
1357*4882a593Smuzhiyun 			ATSC and Basic analog */
1358*4882a593Smuzhiyun 	case 79571:
1359*4882a593Smuzhiyun 		/* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
1360*4882a593Smuzhiyun 		 ATSC and Basic analog */
1361*4882a593Smuzhiyun 	case 79671:
1362*4882a593Smuzhiyun 		/* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
1363*4882a593Smuzhiyun 			ATSC and Basic analog */
1364*4882a593Smuzhiyun 	case 80019:
1365*4882a593Smuzhiyun 		/* WinTV-HVR1400 (Express Card, Retail, IR,
1366*4882a593Smuzhiyun 		 * DVB-T and Basic analog */
1367*4882a593Smuzhiyun 	case 81509:
1368*4882a593Smuzhiyun 		/* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
1369*4882a593Smuzhiyun 		 * DVB-T and MPEG2 HW Encoder */
1370*4882a593Smuzhiyun 	case 81519:
1371*4882a593Smuzhiyun 		/* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
1372*4882a593Smuzhiyun 		 * DVB-T and MPEG2 HW Encoder */
1373*4882a593Smuzhiyun 		break;
1374*4882a593Smuzhiyun 	case 85021:
1375*4882a593Smuzhiyun 		/* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
1376*4882a593Smuzhiyun 			Dual channel ATSC and MPEG2 HW Encoder */
1377*4882a593Smuzhiyun 		break;
1378*4882a593Smuzhiyun 	case 85721:
1379*4882a593Smuzhiyun 		/* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
1380*4882a593Smuzhiyun 			Dual channel ATSC and Basic analog */
1381*4882a593Smuzhiyun 	case 121019:
1382*4882a593Smuzhiyun 		/* WinTV-HVR4400 (PCIe, DVB-S2, DVB-C/T) */
1383*4882a593Smuzhiyun 		break;
1384*4882a593Smuzhiyun 	case 121029:
1385*4882a593Smuzhiyun 		/* WinTV-HVR5500 (PCIe, DVB-S2, DVB-C/T) */
1386*4882a593Smuzhiyun 		break;
1387*4882a593Smuzhiyun 	case 150329:
1388*4882a593Smuzhiyun 		/* WinTV-HVR5525 (PCIe, DVB-S/S2, DVB-T/T2/C) */
1389*4882a593Smuzhiyun 		break;
1390*4882a593Smuzhiyun 	case 161111:
1391*4882a593Smuzhiyun 		/* WinTV-HVR-1265 K4 (PCIe, Analog/ATSC/QAM-B) */
1392*4882a593Smuzhiyun 		break;
1393*4882a593Smuzhiyun 	case 166100: /* 888 version, hybrid */
1394*4882a593Smuzhiyun 	case 166200: /* 885 version, DVB only */
1395*4882a593Smuzhiyun 		/* WinTV-QuadHD (DVB) Tuner Pair 1 (PCIe, IR, half height,
1396*4882a593Smuzhiyun 		   DVB-T/T2/C, DVB-T/T2/C */
1397*4882a593Smuzhiyun 		break;
1398*4882a593Smuzhiyun 	case 166101: /* 888 version, hybrid */
1399*4882a593Smuzhiyun 	case 166201: /* 885 version, DVB only */
1400*4882a593Smuzhiyun 		/* WinTV-QuadHD (DVB) Tuner Pair 2 (PCIe, IR, half height,
1401*4882a593Smuzhiyun 		   DVB-T/T2/C, DVB-T/T2/C */
1402*4882a593Smuzhiyun 		break;
1403*4882a593Smuzhiyun 	case 165100: /* 888 version, hybrid */
1404*4882a593Smuzhiyun 	case 165200: /* 885 version, digital only */
1405*4882a593Smuzhiyun 		/* WinTV-QuadHD (ATSC) Tuner Pair 1 (PCIe, IR, half height,
1406*4882a593Smuzhiyun 		 * ATSC/QAM-B, ATSC/QAM-B */
1407*4882a593Smuzhiyun 		break;
1408*4882a593Smuzhiyun 	case 165101: /* 888 version, hybrid */
1409*4882a593Smuzhiyun 	case 165201: /* 885 version, digital only */
1410*4882a593Smuzhiyun 		/* WinTV-QuadHD (ATSC) Tuner Pair 2 (PCIe, IR, half height,
1411*4882a593Smuzhiyun 		 * ATSC/QAM-B, ATSC/QAM-B */
1412*4882a593Smuzhiyun 		break;
1413*4882a593Smuzhiyun 	default:
1414*4882a593Smuzhiyun 		pr_warn("%s: warning: unknown hauppauge model #%d\n",
1415*4882a593Smuzhiyun 			dev->name, tv.model);
1416*4882a593Smuzhiyun 		break;
1417*4882a593Smuzhiyun 	}
1418*4882a593Smuzhiyun 
1419*4882a593Smuzhiyun 	pr_info("%s: hauppauge eeprom: model=%d\n",
1420*4882a593Smuzhiyun 		dev->name, tv.model);
1421*4882a593Smuzhiyun }
1422*4882a593Smuzhiyun 
1423*4882a593Smuzhiyun /* Some TBS cards require initing a chip using a bitbanged SPI attached
1424*4882a593Smuzhiyun    to the cx23885 gpio's. If this chip doesn't get init'ed the demod
1425*4882a593Smuzhiyun    doesn't respond to any command. */
tbs_card_init(struct cx23885_dev * dev)1426*4882a593Smuzhiyun static void tbs_card_init(struct cx23885_dev *dev)
1427*4882a593Smuzhiyun {
1428*4882a593Smuzhiyun 	int i;
1429*4882a593Smuzhiyun 	static const u8 buf[] = {
1430*4882a593Smuzhiyun 		0xe0, 0x06, 0x66, 0x33, 0x65,
1431*4882a593Smuzhiyun 		0x01, 0x17, 0x06, 0xde};
1432*4882a593Smuzhiyun 
1433*4882a593Smuzhiyun 	switch (dev->board) {
1434*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6980:
1435*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6981:
1436*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00070007);
1437*4882a593Smuzhiyun 		usleep_range(1000, 10000);
1438*4882a593Smuzhiyun 		cx_clear(GP0_IO, 2);
1439*4882a593Smuzhiyun 		usleep_range(1000, 10000);
1440*4882a593Smuzhiyun 		for (i = 0; i < 9 * 8; i++) {
1441*4882a593Smuzhiyun 			cx_clear(GP0_IO, 7);
1442*4882a593Smuzhiyun 			usleep_range(1000, 10000);
1443*4882a593Smuzhiyun 			cx_set(GP0_IO,
1444*4882a593Smuzhiyun 				((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4);
1445*4882a593Smuzhiyun 			usleep_range(1000, 10000);
1446*4882a593Smuzhiyun 		}
1447*4882a593Smuzhiyun 		cx_set(GP0_IO, 7);
1448*4882a593Smuzhiyun 		break;
1449*4882a593Smuzhiyun 	}
1450*4882a593Smuzhiyun }
1451*4882a593Smuzhiyun 
cx23885_tuner_callback(void * priv,int component,int command,int arg)1452*4882a593Smuzhiyun int cx23885_tuner_callback(void *priv, int component, int command, int arg)
1453*4882a593Smuzhiyun {
1454*4882a593Smuzhiyun 	struct cx23885_tsport *port = priv;
1455*4882a593Smuzhiyun 	struct cx23885_dev *dev = port->dev;
1456*4882a593Smuzhiyun 	u32 bitmask = 0;
1457*4882a593Smuzhiyun 
1458*4882a593Smuzhiyun 	if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
1459*4882a593Smuzhiyun 		return 0;
1460*4882a593Smuzhiyun 
1461*4882a593Smuzhiyun 	if (command != 0) {
1462*4882a593Smuzhiyun 		pr_err("%s(): Unknown command 0x%x.\n",
1463*4882a593Smuzhiyun 		       __func__, command);
1464*4882a593Smuzhiyun 		return -EINVAL;
1465*4882a593Smuzhiyun 	}
1466*4882a593Smuzhiyun 
1467*4882a593Smuzhiyun 	switch (dev->board) {
1468*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1400:
1469*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1500:
1470*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1471*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1472*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1473*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1474*4882a593Smuzhiyun 	case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1475*4882a593Smuzhiyun 	case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1476*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1477*4882a593Smuzhiyun 		/* Tuner Reset Command */
1478*4882a593Smuzhiyun 		bitmask = 0x04;
1479*4882a593Smuzhiyun 		break;
1480*4882a593Smuzhiyun 	case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1481*4882a593Smuzhiyun 	case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1482*4882a593Smuzhiyun 	case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1483*4882a593Smuzhiyun 		/* Two identical tuners on two different i2c buses,
1484*4882a593Smuzhiyun 		 * we need to reset the correct gpio. */
1485*4882a593Smuzhiyun 		if (port->nr == 1)
1486*4882a593Smuzhiyun 			bitmask = 0x01;
1487*4882a593Smuzhiyun 		else if (port->nr == 2)
1488*4882a593Smuzhiyun 			bitmask = 0x04;
1489*4882a593Smuzhiyun 		break;
1490*4882a593Smuzhiyun 	case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1491*4882a593Smuzhiyun 		/* Tuner Reset Command */
1492*4882a593Smuzhiyun 		bitmask = 0x02;
1493*4882a593Smuzhiyun 		break;
1494*4882a593Smuzhiyun 	case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1495*4882a593Smuzhiyun 		altera_ci_tuner_reset(dev, port->nr);
1496*4882a593Smuzhiyun 		break;
1497*4882a593Smuzhiyun 	case CX23885_BOARD_AVERMEDIA_HC81R:
1498*4882a593Smuzhiyun 		/* XC3028L Reset Command */
1499*4882a593Smuzhiyun 		bitmask = 1 << 2;
1500*4882a593Smuzhiyun 		break;
1501*4882a593Smuzhiyun 	}
1502*4882a593Smuzhiyun 
1503*4882a593Smuzhiyun 	if (bitmask) {
1504*4882a593Smuzhiyun 		/* Drive the tuner into reset and back out */
1505*4882a593Smuzhiyun 		cx_clear(GP0_IO, bitmask);
1506*4882a593Smuzhiyun 		mdelay(200);
1507*4882a593Smuzhiyun 		cx_set(GP0_IO, bitmask);
1508*4882a593Smuzhiyun 	}
1509*4882a593Smuzhiyun 
1510*4882a593Smuzhiyun 	return 0;
1511*4882a593Smuzhiyun }
1512*4882a593Smuzhiyun 
cx23885_gpio_setup(struct cx23885_dev * dev)1513*4882a593Smuzhiyun void cx23885_gpio_setup(struct cx23885_dev *dev)
1514*4882a593Smuzhiyun {
1515*4882a593Smuzhiyun 	switch (dev->board) {
1516*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1250:
1517*4882a593Smuzhiyun 		/* GPIO-0 cx24227 demodulator reset */
1518*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1519*4882a593Smuzhiyun 		break;
1520*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1500:
1521*4882a593Smuzhiyun 		/* GPIO-0 cx24227 demodulator */
1522*4882a593Smuzhiyun 		/* GPIO-2 xc3028 tuner */
1523*4882a593Smuzhiyun 
1524*4882a593Smuzhiyun 		/* Put the parts into reset */
1525*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00050000);
1526*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00000005);
1527*4882a593Smuzhiyun 		msleep(5);
1528*4882a593Smuzhiyun 
1529*4882a593Smuzhiyun 		/* Bring the parts out of reset */
1530*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00050005);
1531*4882a593Smuzhiyun 		break;
1532*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1533*4882a593Smuzhiyun 		/* GPIO-0 cx24227 demodulator reset */
1534*4882a593Smuzhiyun 		/* GPIO-2 xc5000 tuner reset */
1535*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
1536*4882a593Smuzhiyun 		break;
1537*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1800:
1538*4882a593Smuzhiyun 		/* GPIO-0 656_CLK */
1539*4882a593Smuzhiyun 		/* GPIO-1 656_D0 */
1540*4882a593Smuzhiyun 		/* GPIO-2 8295A Reset */
1541*4882a593Smuzhiyun 		/* GPIO-3-10 cx23417 data0-7 */
1542*4882a593Smuzhiyun 		/* GPIO-11-14 cx23417 addr0-3 */
1543*4882a593Smuzhiyun 		/* GPIO-15-18 cx23417 READY, CS, RD, WR */
1544*4882a593Smuzhiyun 		/* GPIO-19 IR_RX */
1545*4882a593Smuzhiyun 
1546*4882a593Smuzhiyun 		/* CX23417 GPIO's */
1547*4882a593Smuzhiyun 		/* EIO15 Zilog Reset */
1548*4882a593Smuzhiyun 		/* EIO14 S5H1409/CX24227 Reset */
1549*4882a593Smuzhiyun 		mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
1550*4882a593Smuzhiyun 
1551*4882a593Smuzhiyun 		/* Put the demod into reset and protect the eeprom */
1552*4882a593Smuzhiyun 		mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
1553*4882a593Smuzhiyun 		msleep(100);
1554*4882a593Smuzhiyun 
1555*4882a593Smuzhiyun 		/* Bring the demod and blaster out of reset */
1556*4882a593Smuzhiyun 		mc417_gpio_set(dev, GPIO_15 | GPIO_14);
1557*4882a593Smuzhiyun 		msleep(100);
1558*4882a593Smuzhiyun 
1559*4882a593Smuzhiyun 		/* Force the TDA8295A into reset and back */
1560*4882a593Smuzhiyun 		cx23885_gpio_enable(dev, GPIO_2, 1);
1561*4882a593Smuzhiyun 		cx23885_gpio_set(dev, GPIO_2);
1562*4882a593Smuzhiyun 		msleep(20);
1563*4882a593Smuzhiyun 		cx23885_gpio_clear(dev, GPIO_2);
1564*4882a593Smuzhiyun 		msleep(20);
1565*4882a593Smuzhiyun 		cx23885_gpio_set(dev, GPIO_2);
1566*4882a593Smuzhiyun 		msleep(20);
1567*4882a593Smuzhiyun 		break;
1568*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1200:
1569*4882a593Smuzhiyun 		/* GPIO-0 tda10048 demodulator reset */
1570*4882a593Smuzhiyun 		/* GPIO-2 tda18271 tuner reset */
1571*4882a593Smuzhiyun 
1572*4882a593Smuzhiyun 		/* Put the parts into reset and back */
1573*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00050000);
1574*4882a593Smuzhiyun 		msleep(20);
1575*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00000005);
1576*4882a593Smuzhiyun 		msleep(20);
1577*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00050005);
1578*4882a593Smuzhiyun 		break;
1579*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1700:
1580*4882a593Smuzhiyun 		/* GPIO-0 TDA10048 demodulator reset */
1581*4882a593Smuzhiyun 		/* GPIO-2 TDA8295A Reset */
1582*4882a593Smuzhiyun 		/* GPIO-3-10 cx23417 data0-7 */
1583*4882a593Smuzhiyun 		/* GPIO-11-14 cx23417 addr0-3 */
1584*4882a593Smuzhiyun 		/* GPIO-15-18 cx23417 READY, CS, RD, WR */
1585*4882a593Smuzhiyun 
1586*4882a593Smuzhiyun 		/* The following GPIO's are on the interna AVCore (cx25840) */
1587*4882a593Smuzhiyun 		/* GPIO-19 IR_RX */
1588*4882a593Smuzhiyun 		/* GPIO-20 IR_TX 416/DVBT Select */
1589*4882a593Smuzhiyun 		/* GPIO-21 IIS DAT */
1590*4882a593Smuzhiyun 		/* GPIO-22 IIS WCLK */
1591*4882a593Smuzhiyun 		/* GPIO-23 IIS BCLK */
1592*4882a593Smuzhiyun 
1593*4882a593Smuzhiyun 		/* Put the parts into reset and back */
1594*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00050000);
1595*4882a593Smuzhiyun 		msleep(20);
1596*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00000005);
1597*4882a593Smuzhiyun 		msleep(20);
1598*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00050005);
1599*4882a593Smuzhiyun 		break;
1600*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1400:
1601*4882a593Smuzhiyun 		/* GPIO-0  Dibcom7000p demodulator reset */
1602*4882a593Smuzhiyun 		/* GPIO-2  xc3028L tuner reset */
1603*4882a593Smuzhiyun 		/* GPIO-13 LED */
1604*4882a593Smuzhiyun 
1605*4882a593Smuzhiyun 		/* Put the parts into reset and back */
1606*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00050000);
1607*4882a593Smuzhiyun 		msleep(20);
1608*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00000005);
1609*4882a593Smuzhiyun 		msleep(20);
1610*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00050005);
1611*4882a593Smuzhiyun 		break;
1612*4882a593Smuzhiyun 	case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1613*4882a593Smuzhiyun 		/* GPIO-0 xc5000 tuner reset i2c bus 0 */
1614*4882a593Smuzhiyun 		/* GPIO-1 s5h1409 demod reset i2c bus 0 */
1615*4882a593Smuzhiyun 		/* GPIO-2 xc5000 tuner reset i2c bus 1 */
1616*4882a593Smuzhiyun 		/* GPIO-3 s5h1409 demod reset i2c bus 0 */
1617*4882a593Smuzhiyun 
1618*4882a593Smuzhiyun 		/* Put the parts into reset and back */
1619*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x000f0000);
1620*4882a593Smuzhiyun 		msleep(20);
1621*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x0000000f);
1622*4882a593Smuzhiyun 		msleep(20);
1623*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x000f000f);
1624*4882a593Smuzhiyun 		break;
1625*4882a593Smuzhiyun 	case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1626*4882a593Smuzhiyun 	case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1627*4882a593Smuzhiyun 		/* GPIO-0 portb xc3028 reset */
1628*4882a593Smuzhiyun 		/* GPIO-1 portb zl10353 reset */
1629*4882a593Smuzhiyun 		/* GPIO-2 portc xc3028 reset */
1630*4882a593Smuzhiyun 		/* GPIO-3 portc zl10353 reset */
1631*4882a593Smuzhiyun 
1632*4882a593Smuzhiyun 		/* Put the parts into reset and back */
1633*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x000f0000);
1634*4882a593Smuzhiyun 		msleep(20);
1635*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x0000000f);
1636*4882a593Smuzhiyun 		msleep(20);
1637*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x000f000f);
1638*4882a593Smuzhiyun 		break;
1639*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1640*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1641*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1642*4882a593Smuzhiyun 	case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1643*4882a593Smuzhiyun 	case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1644*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1645*4882a593Smuzhiyun 		/* GPIO-2  xc3028 tuner reset */
1646*4882a593Smuzhiyun 
1647*4882a593Smuzhiyun 		/* The following GPIO's are on the internal AVCore (cx25840) */
1648*4882a593Smuzhiyun 		/* GPIO-?  zl10353 demod reset */
1649*4882a593Smuzhiyun 
1650*4882a593Smuzhiyun 		/* Put the parts into reset and back */
1651*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00040000);
1652*4882a593Smuzhiyun 		msleep(20);
1653*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00000004);
1654*4882a593Smuzhiyun 		msleep(20);
1655*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00040004);
1656*4882a593Smuzhiyun 		break;
1657*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6920:
1658*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6980:
1659*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6981:
1660*4882a593Smuzhiyun 	case CX23885_BOARD_PROF_8000:
1661*4882a593Smuzhiyun 		cx_write(MC417_CTL, 0x00000036);
1662*4882a593Smuzhiyun 		cx_write(MC417_OEN, 0x00001000);
1663*4882a593Smuzhiyun 		cx_set(MC417_RWD, 0x00000002);
1664*4882a593Smuzhiyun 		msleep(200);
1665*4882a593Smuzhiyun 		cx_clear(MC417_RWD, 0x00000800);
1666*4882a593Smuzhiyun 		msleep(200);
1667*4882a593Smuzhiyun 		cx_set(MC417_RWD, 0x00000800);
1668*4882a593Smuzhiyun 		msleep(200);
1669*4882a593Smuzhiyun 		break;
1670*4882a593Smuzhiyun 	case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1671*4882a593Smuzhiyun 		/* GPIO-0 INTA from CiMax1
1672*4882a593Smuzhiyun 		   GPIO-1 INTB from CiMax2
1673*4882a593Smuzhiyun 		   GPIO-2 reset chips
1674*4882a593Smuzhiyun 		   GPIO-3 to GPIO-10 data/addr for CA
1675*4882a593Smuzhiyun 		   GPIO-11 ~CS0 to CiMax1
1676*4882a593Smuzhiyun 		   GPIO-12 ~CS1 to CiMax2
1677*4882a593Smuzhiyun 		   GPIO-13 ADL0 load LSB addr
1678*4882a593Smuzhiyun 		   GPIO-14 ADL1 load MSB addr
1679*4882a593Smuzhiyun 		   GPIO-15 ~RDY from CiMax
1680*4882a593Smuzhiyun 		   GPIO-17 ~RD to CiMax
1681*4882a593Smuzhiyun 		   GPIO-18 ~WR to CiMax
1682*4882a593Smuzhiyun 		 */
1683*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00040000); /* GPIO as out */
1684*4882a593Smuzhiyun 		/* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
1685*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00030004);
1686*4882a593Smuzhiyun 		msleep(100);/* reset delay */
1687*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
1688*4882a593Smuzhiyun 		cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
1689*4882a593Smuzhiyun 		/* GPIO-15 IN as ~ACK, rest as OUT */
1690*4882a593Smuzhiyun 		cx_write(MC417_OEN, 0x00001000);
1691*4882a593Smuzhiyun 		/* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1692*4882a593Smuzhiyun 		cx_write(MC417_RWD, 0x0000c300);
1693*4882a593Smuzhiyun 		/* enable irq */
1694*4882a593Smuzhiyun 		cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1695*4882a593Smuzhiyun 		break;
1696*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1270:
1697*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1275:
1698*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1255:
1699*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1700*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1210:
1701*4882a593Smuzhiyun 		/* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
1702*4882a593Smuzhiyun 		/* GPIO-6 I2C Gate which can isolate the demod from the bus */
1703*4882a593Smuzhiyun 		/* GPIO-9 Demod reset */
1704*4882a593Smuzhiyun 
1705*4882a593Smuzhiyun 		/* Put the parts into reset and back */
1706*4882a593Smuzhiyun 		cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
1707*4882a593Smuzhiyun 		cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
1708*4882a593Smuzhiyun 		cx23885_gpio_clear(dev, GPIO_9);
1709*4882a593Smuzhiyun 		msleep(20);
1710*4882a593Smuzhiyun 		cx23885_gpio_set(dev, GPIO_9);
1711*4882a593Smuzhiyun 		break;
1712*4882a593Smuzhiyun 	case CX23885_BOARD_MYGICA_X8506:
1713*4882a593Smuzhiyun 	case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1714*4882a593Smuzhiyun 	case CX23885_BOARD_MYGICA_X8507:
1715*4882a593Smuzhiyun 		/* GPIO-0 (0)Analog / (1)Digital TV */
1716*4882a593Smuzhiyun 		/* GPIO-1 reset XC5000 */
1717*4882a593Smuzhiyun 		/* GPIO-2 demod reset */
1718*4882a593Smuzhiyun 		cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
1719*4882a593Smuzhiyun 		cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
1720*4882a593Smuzhiyun 		msleep(100);
1721*4882a593Smuzhiyun 		cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
1722*4882a593Smuzhiyun 		msleep(100);
1723*4882a593Smuzhiyun 		break;
1724*4882a593Smuzhiyun 	case CX23885_BOARD_MYGICA_X8558PRO:
1725*4882a593Smuzhiyun 		/* GPIO-0 reset first ATBM8830 */
1726*4882a593Smuzhiyun 		/* GPIO-1 reset second ATBM8830 */
1727*4882a593Smuzhiyun 		cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
1728*4882a593Smuzhiyun 		cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
1729*4882a593Smuzhiyun 		msleep(100);
1730*4882a593Smuzhiyun 		cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
1731*4882a593Smuzhiyun 		msleep(100);
1732*4882a593Smuzhiyun 		break;
1733*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1850:
1734*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1290:
1735*4882a593Smuzhiyun 		/* GPIO-0 656_CLK */
1736*4882a593Smuzhiyun 		/* GPIO-1 656_D0 */
1737*4882a593Smuzhiyun 		/* GPIO-2 Wake# */
1738*4882a593Smuzhiyun 		/* GPIO-3-10 cx23417 data0-7 */
1739*4882a593Smuzhiyun 		/* GPIO-11-14 cx23417 addr0-3 */
1740*4882a593Smuzhiyun 		/* GPIO-15-18 cx23417 READY, CS, RD, WR */
1741*4882a593Smuzhiyun 		/* GPIO-19 IR_RX */
1742*4882a593Smuzhiyun 		/* GPIO-20 C_IR_TX */
1743*4882a593Smuzhiyun 		/* GPIO-21 I2S DAT */
1744*4882a593Smuzhiyun 		/* GPIO-22 I2S WCLK */
1745*4882a593Smuzhiyun 		/* GPIO-23 I2S BCLK */
1746*4882a593Smuzhiyun 		/* ALT GPIO: EXP GPIO LATCH */
1747*4882a593Smuzhiyun 
1748*4882a593Smuzhiyun 		/* CX23417 GPIO's */
1749*4882a593Smuzhiyun 		/* GPIO-14 S5H1411/CX24228 Reset */
1750*4882a593Smuzhiyun 		/* GPIO-13 EEPROM write protect */
1751*4882a593Smuzhiyun 		mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1752*4882a593Smuzhiyun 
1753*4882a593Smuzhiyun 		/* Put the demod into reset and protect the eeprom */
1754*4882a593Smuzhiyun 		mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1755*4882a593Smuzhiyun 		msleep(100);
1756*4882a593Smuzhiyun 
1757*4882a593Smuzhiyun 		/* Bring the demod out of reset */
1758*4882a593Smuzhiyun 		mc417_gpio_set(dev, GPIO_14);
1759*4882a593Smuzhiyun 		msleep(100);
1760*4882a593Smuzhiyun 
1761*4882a593Smuzhiyun 		/* CX24228 GPIO */
1762*4882a593Smuzhiyun 		/* Connected to IF / Mux */
1763*4882a593Smuzhiyun 		break;
1764*4882a593Smuzhiyun 	case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1765*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1766*4882a593Smuzhiyun 		break;
1767*4882a593Smuzhiyun 	case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1768*4882a593Smuzhiyun 		/* GPIO-0 ~INT in
1769*4882a593Smuzhiyun 		   GPIO-1 TMS out
1770*4882a593Smuzhiyun 		   GPIO-2 ~reset chips out
1771*4882a593Smuzhiyun 		   GPIO-3 to GPIO-10 data/addr for CA in/out
1772*4882a593Smuzhiyun 		   GPIO-11 ~CS out
1773*4882a593Smuzhiyun 		   GPIO-12 ADDR out
1774*4882a593Smuzhiyun 		   GPIO-13 ~WR out
1775*4882a593Smuzhiyun 		   GPIO-14 ~RD out
1776*4882a593Smuzhiyun 		   GPIO-15 ~RDY in
1777*4882a593Smuzhiyun 		   GPIO-16 TCK out
1778*4882a593Smuzhiyun 		   GPIO-17 TDO in
1779*4882a593Smuzhiyun 		   GPIO-18 TDI out
1780*4882a593Smuzhiyun 		 */
1781*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1782*4882a593Smuzhiyun 		/* GPIO-0 as INT, reset & TMS low */
1783*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00010006);
1784*4882a593Smuzhiyun 		msleep(100);/* reset delay */
1785*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00000004); /* reset high */
1786*4882a593Smuzhiyun 		cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1787*4882a593Smuzhiyun 		/* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1788*4882a593Smuzhiyun 		cx_write(MC417_OEN, 0x00005000);
1789*4882a593Smuzhiyun 		/* ~RD, ~WR high; ADDR low; ~CS high */
1790*4882a593Smuzhiyun 		cx_write(MC417_RWD, 0x00000d00);
1791*4882a593Smuzhiyun 		/* enable irq */
1792*4882a593Smuzhiyun 		cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1793*4882a593Smuzhiyun 		break;
1794*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR4400:
1795*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_STARBURST:
1796*4882a593Smuzhiyun 		/* GPIO-8 tda10071 demod reset */
1797*4882a593Smuzhiyun 		/* GPIO-9 si2165 demod reset (only HVR4400/HVR5500)*/
1798*4882a593Smuzhiyun 
1799*4882a593Smuzhiyun 		/* Put the parts into reset and back */
1800*4882a593Smuzhiyun 		cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
1801*4882a593Smuzhiyun 
1802*4882a593Smuzhiyun 		cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
1803*4882a593Smuzhiyun 		msleep(100);
1804*4882a593Smuzhiyun 		cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
1805*4882a593Smuzhiyun 		msleep(100);
1806*4882a593Smuzhiyun 
1807*4882a593Smuzhiyun 		break;
1808*4882a593Smuzhiyun 	case CX23885_BOARD_AVERMEDIA_HC81R:
1809*4882a593Smuzhiyun 		cx_clear(MC417_CTL, 1);
1810*4882a593Smuzhiyun 		/* GPIO-0,1,2 setup direction as output */
1811*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00070000);
1812*4882a593Smuzhiyun 		usleep_range(10000, 11000);
1813*4882a593Smuzhiyun 		/* AF9013 demod reset */
1814*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00010001);
1815*4882a593Smuzhiyun 		usleep_range(10000, 11000);
1816*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00010001);
1817*4882a593Smuzhiyun 		usleep_range(10000, 11000);
1818*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00010001);
1819*4882a593Smuzhiyun 		usleep_range(10000, 11000);
1820*4882a593Smuzhiyun 		/* demod tune? */
1821*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00030003);
1822*4882a593Smuzhiyun 		usleep_range(10000, 11000);
1823*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00020002);
1824*4882a593Smuzhiyun 		usleep_range(10000, 11000);
1825*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00010001);
1826*4882a593Smuzhiyun 		usleep_range(10000, 11000);
1827*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00020002);
1828*4882a593Smuzhiyun 		/* XC3028L tuner reset */
1829*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00040004);
1830*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00040004);
1831*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00040004);
1832*4882a593Smuzhiyun 		msleep(60);
1833*4882a593Smuzhiyun 		break;
1834*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T9580:
1835*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S952:
1836*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T982:
1837*4882a593Smuzhiyun 		/* enable GPIO3-18 pins */
1838*4882a593Smuzhiyun 		cx_write(MC417_CTL, 0x00000037);
1839*4882a593Smuzhiyun 		cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1);
1840*4882a593Smuzhiyun 		cx23885_gpio_clear(dev, GPIO_2 | GPIO_11);
1841*4882a593Smuzhiyun 		msleep(100);
1842*4882a593Smuzhiyun 		cx23885_gpio_set(dev, GPIO_2 | GPIO_11);
1843*4882a593Smuzhiyun 		break;
1844*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T980C:
1845*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S950C:
1846*4882a593Smuzhiyun 	case CX23885_BOARD_TT_CT2_4500_CI:
1847*4882a593Smuzhiyun 		/*
1848*4882a593Smuzhiyun 		 * GPIO-0 INTA from CiMax, input
1849*4882a593Smuzhiyun 		 * GPIO-1 reset CiMax, output, high active
1850*4882a593Smuzhiyun 		 * GPIO-2 reset demod, output, low active
1851*4882a593Smuzhiyun 		 * GPIO-3 to GPIO-10 data/addr for CAM
1852*4882a593Smuzhiyun 		 * GPIO-11 ~CS0 to CiMax1
1853*4882a593Smuzhiyun 		 * GPIO-12 ~CS1 to CiMax2
1854*4882a593Smuzhiyun 		 * GPIO-13 ADL0 load LSB addr
1855*4882a593Smuzhiyun 		 * GPIO-14 ADL1 load MSB addr
1856*4882a593Smuzhiyun 		 * GPIO-15 ~RDY from CiMax
1857*4882a593Smuzhiyun 		 * GPIO-17 ~RD to CiMax
1858*4882a593Smuzhiyun 		 * GPIO-18 ~WR to CiMax
1859*4882a593Smuzhiyun 		 */
1860*4882a593Smuzhiyun 
1861*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */
1862*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00010004); /* GPIO 0 as input */
1863*4882a593Smuzhiyun 		msleep(100); /* reset delay */
1864*4882a593Smuzhiyun 		cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */
1865*4882a593Smuzhiyun 		cx_clear(GP0_IO, 0x00010002);
1866*4882a593Smuzhiyun 		cx_write(MC417_CTL, 0x00000037); /* enable GPIO3-18 pins */
1867*4882a593Smuzhiyun 
1868*4882a593Smuzhiyun 		/* GPIO-15 IN as ~ACK, rest as OUT */
1869*4882a593Smuzhiyun 		cx_write(MC417_OEN, 0x00001000);
1870*4882a593Smuzhiyun 
1871*4882a593Smuzhiyun 		/* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1872*4882a593Smuzhiyun 		cx_write(MC417_RWD, 0x0000c300);
1873*4882a593Smuzhiyun 
1874*4882a593Smuzhiyun 		/* enable irq */
1875*4882a593Smuzhiyun 		cx_write(GPIO_ISM, 0x00000000); /* INTERRUPTS active low */
1876*4882a593Smuzhiyun 		break;
1877*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S950:
1878*4882a593Smuzhiyun 		cx23885_gpio_enable(dev, GPIO_2, 1);
1879*4882a593Smuzhiyun 		cx23885_gpio_clear(dev, GPIO_2);
1880*4882a593Smuzhiyun 		msleep(100);
1881*4882a593Smuzhiyun 		cx23885_gpio_set(dev, GPIO_2);
1882*4882a593Smuzhiyun 		break;
1883*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR5525:
1884*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_STARBURST2:
1885*4882a593Smuzhiyun 		/*
1886*4882a593Smuzhiyun 		 * HVR5525 GPIO Details:
1887*4882a593Smuzhiyun 		 *  GPIO-00 IR_WIDE
1888*4882a593Smuzhiyun 		 *  GPIO-02 wake#
1889*4882a593Smuzhiyun 		 *  GPIO-03 VAUX Pres.
1890*4882a593Smuzhiyun 		 *  GPIO-07 PROG#
1891*4882a593Smuzhiyun 		 *  GPIO-08 SAT_RESN
1892*4882a593Smuzhiyun 		 *  GPIO-09 TER_RESN
1893*4882a593Smuzhiyun 		 *  GPIO-10 B2_SENSE
1894*4882a593Smuzhiyun 		 *  GPIO-11 B1_SENSE
1895*4882a593Smuzhiyun 		 *  GPIO-15 IR_LED_STATUS
1896*4882a593Smuzhiyun 		 *  GPIO-19 IR_NARROW
1897*4882a593Smuzhiyun 		 *  GPIO-20 Blauster1
1898*4882a593Smuzhiyun 		 *  ALTGPIO VAUX_SWITCH
1899*4882a593Smuzhiyun 		 *  AUX_PLL_CLK : Blaster2
1900*4882a593Smuzhiyun 		 */
1901*4882a593Smuzhiyun 		/* Put the parts into reset and back */
1902*4882a593Smuzhiyun 		cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
1903*4882a593Smuzhiyun 		cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
1904*4882a593Smuzhiyun 		msleep(100);
1905*4882a593Smuzhiyun 		cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
1906*4882a593Smuzhiyun 		msleep(100);
1907*4882a593Smuzhiyun 		break;
1908*4882a593Smuzhiyun 	case CX23885_BOARD_VIEWCAST_260E:
1909*4882a593Smuzhiyun 	case CX23885_BOARD_VIEWCAST_460E:
1910*4882a593Smuzhiyun 		/* For documentation purposes, it's worth noting that this
1911*4882a593Smuzhiyun 		 * card does not have any GPIO's connected to subcomponents.
1912*4882a593Smuzhiyun 		 */
1913*4882a593Smuzhiyun 		break;
1914*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
1915*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
1916*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885:
1917*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
1918*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885:
1919*4882a593Smuzhiyun 		/*
1920*4882a593Smuzhiyun 		 * GPIO-08 TER1_RESN
1921*4882a593Smuzhiyun 		 * GPIO-09 TER2_RESN
1922*4882a593Smuzhiyun 		 */
1923*4882a593Smuzhiyun 		/* Put the parts into reset and back */
1924*4882a593Smuzhiyun 		cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
1925*4882a593Smuzhiyun 		cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
1926*4882a593Smuzhiyun 		msleep(100);
1927*4882a593Smuzhiyun 		cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
1928*4882a593Smuzhiyun 		msleep(100);
1929*4882a593Smuzhiyun 		break;
1930*4882a593Smuzhiyun 	}
1931*4882a593Smuzhiyun }
1932*4882a593Smuzhiyun 
cx23885_ir_init(struct cx23885_dev * dev)1933*4882a593Smuzhiyun int cx23885_ir_init(struct cx23885_dev *dev)
1934*4882a593Smuzhiyun {
1935*4882a593Smuzhiyun 	static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
1936*4882a593Smuzhiyun 		{
1937*4882a593Smuzhiyun 			.flags	  = BIT(V4L2_SUBDEV_IO_PIN_INPUT),
1938*4882a593Smuzhiyun 			.pin	  = CX23885_PIN_IR_RX_GPIO19,
1939*4882a593Smuzhiyun 			.function = CX23885_PAD_IR_RX,
1940*4882a593Smuzhiyun 			.value	  = 0,
1941*4882a593Smuzhiyun 			.strength = CX25840_PIN_DRIVE_MEDIUM,
1942*4882a593Smuzhiyun 		}, {
1943*4882a593Smuzhiyun 			.flags	  = BIT(V4L2_SUBDEV_IO_PIN_OUTPUT),
1944*4882a593Smuzhiyun 			.pin	  = CX23885_PIN_IR_TX_GPIO20,
1945*4882a593Smuzhiyun 			.function = CX23885_PAD_IR_TX,
1946*4882a593Smuzhiyun 			.value	  = 0,
1947*4882a593Smuzhiyun 			.strength = CX25840_PIN_DRIVE_MEDIUM,
1948*4882a593Smuzhiyun 		}
1949*4882a593Smuzhiyun 	};
1950*4882a593Smuzhiyun 	const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1951*4882a593Smuzhiyun 
1952*4882a593Smuzhiyun 	static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1953*4882a593Smuzhiyun 		{
1954*4882a593Smuzhiyun 			.flags	  = BIT(V4L2_SUBDEV_IO_PIN_INPUT),
1955*4882a593Smuzhiyun 			.pin	  = CX23885_PIN_IR_RX_GPIO19,
1956*4882a593Smuzhiyun 			.function = CX23885_PAD_IR_RX,
1957*4882a593Smuzhiyun 			.value	  = 0,
1958*4882a593Smuzhiyun 			.strength = CX25840_PIN_DRIVE_MEDIUM,
1959*4882a593Smuzhiyun 		}
1960*4882a593Smuzhiyun 	};
1961*4882a593Smuzhiyun 	const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
1962*4882a593Smuzhiyun 
1963*4882a593Smuzhiyun 	struct v4l2_subdev_ir_parameters params;
1964*4882a593Smuzhiyun 	int ret = 0;
1965*4882a593Smuzhiyun 	switch (dev->board) {
1966*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1500:
1967*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1968*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1800:
1969*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1200:
1970*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1400:
1971*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1275:
1972*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1255:
1973*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1974*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1210:
1975*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
1976*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
1977*4882a593Smuzhiyun 		/* FIXME: Implement me */
1978*4882a593Smuzhiyun 		break;
1979*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1270:
1980*4882a593Smuzhiyun 		ret = cx23888_ir_probe(dev);
1981*4882a593Smuzhiyun 		if (ret)
1982*4882a593Smuzhiyun 			break;
1983*4882a593Smuzhiyun 		dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1984*4882a593Smuzhiyun 		v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1985*4882a593Smuzhiyun 				 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1986*4882a593Smuzhiyun 		break;
1987*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1850:
1988*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1290:
1989*4882a593Smuzhiyun 		ret = cx23888_ir_probe(dev);
1990*4882a593Smuzhiyun 		if (ret)
1991*4882a593Smuzhiyun 			break;
1992*4882a593Smuzhiyun 		dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1993*4882a593Smuzhiyun 		v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1994*4882a593Smuzhiyun 				 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1995*4882a593Smuzhiyun 		/*
1996*4882a593Smuzhiyun 		 * For these boards we need to invert the Tx output via the
1997*4882a593Smuzhiyun 		 * IR controller to have the LED off while idle
1998*4882a593Smuzhiyun 		 */
1999*4882a593Smuzhiyun 		v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
2000*4882a593Smuzhiyun 		params.enable = false;
2001*4882a593Smuzhiyun 		params.shutdown = false;
2002*4882a593Smuzhiyun 		params.invert_level = true;
2003*4882a593Smuzhiyun 		v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
2004*4882a593Smuzhiyun 		params.shutdown = true;
2005*4882a593Smuzhiyun 		v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
2006*4882a593Smuzhiyun 		break;
2007*4882a593Smuzhiyun 	case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
2008*4882a593Smuzhiyun 	case CX23885_BOARD_TEVII_S470:
2009*4882a593Smuzhiyun 	case CX23885_BOARD_MYGICA_X8507:
2010*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6980:
2011*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6981:
2012*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T9580:
2013*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T980C:
2014*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S950C:
2015*4882a593Smuzhiyun 	case CX23885_BOARD_TT_CT2_4500_CI:
2016*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S950:
2017*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S952:
2018*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T982:
2019*4882a593Smuzhiyun 		if (!enable_885_ir)
2020*4882a593Smuzhiyun 			break;
2021*4882a593Smuzhiyun 		dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
2022*4882a593Smuzhiyun 		if (dev->sd_ir == NULL) {
2023*4882a593Smuzhiyun 			ret = -ENODEV;
2024*4882a593Smuzhiyun 			break;
2025*4882a593Smuzhiyun 		}
2026*4882a593Smuzhiyun 		v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
2027*4882a593Smuzhiyun 				 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
2028*4882a593Smuzhiyun 		break;
2029*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1250:
2030*4882a593Smuzhiyun 		if (!enable_885_ir)
2031*4882a593Smuzhiyun 			break;
2032*4882a593Smuzhiyun 		dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
2033*4882a593Smuzhiyun 		if (dev->sd_ir == NULL) {
2034*4882a593Smuzhiyun 			ret = -ENODEV;
2035*4882a593Smuzhiyun 			break;
2036*4882a593Smuzhiyun 		}
2037*4882a593Smuzhiyun 		v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
2038*4882a593Smuzhiyun 				 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
2039*4882a593Smuzhiyun 		break;
2040*4882a593Smuzhiyun 	case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
2041*4882a593Smuzhiyun 	case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
2042*4882a593Smuzhiyun 		request_module("ir-kbd-i2c");
2043*4882a593Smuzhiyun 		break;
2044*4882a593Smuzhiyun 	}
2045*4882a593Smuzhiyun 
2046*4882a593Smuzhiyun 	return ret;
2047*4882a593Smuzhiyun }
2048*4882a593Smuzhiyun 
cx23885_ir_fini(struct cx23885_dev * dev)2049*4882a593Smuzhiyun void cx23885_ir_fini(struct cx23885_dev *dev)
2050*4882a593Smuzhiyun {
2051*4882a593Smuzhiyun 	switch (dev->board) {
2052*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1270:
2053*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1850:
2054*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1290:
2055*4882a593Smuzhiyun 		cx23885_irq_remove(dev, PCI_MSK_IR);
2056*4882a593Smuzhiyun 		cx23888_ir_remove(dev);
2057*4882a593Smuzhiyun 		dev->sd_ir = NULL;
2058*4882a593Smuzhiyun 		break;
2059*4882a593Smuzhiyun 	case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
2060*4882a593Smuzhiyun 	case CX23885_BOARD_TEVII_S470:
2061*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1250:
2062*4882a593Smuzhiyun 	case CX23885_BOARD_MYGICA_X8507:
2063*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6980:
2064*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6981:
2065*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T9580:
2066*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T980C:
2067*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S950C:
2068*4882a593Smuzhiyun 	case CX23885_BOARD_TT_CT2_4500_CI:
2069*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S950:
2070*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S952:
2071*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T982:
2072*4882a593Smuzhiyun 		cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
2073*4882a593Smuzhiyun 		/* sd_ir is a duplicate pointer to the AV Core, just clear it */
2074*4882a593Smuzhiyun 		dev->sd_ir = NULL;
2075*4882a593Smuzhiyun 		break;
2076*4882a593Smuzhiyun 	}
2077*4882a593Smuzhiyun }
2078*4882a593Smuzhiyun 
netup_jtag_io(void * device,int tms,int tdi,int read_tdo)2079*4882a593Smuzhiyun static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
2080*4882a593Smuzhiyun {
2081*4882a593Smuzhiyun 	int data;
2082*4882a593Smuzhiyun 	int tdo = 0;
2083*4882a593Smuzhiyun 	struct cx23885_dev *dev = (struct cx23885_dev *)device;
2084*4882a593Smuzhiyun 	/*TMS*/
2085*4882a593Smuzhiyun 	data = ((cx_read(GP0_IO)) & (~0x00000002));
2086*4882a593Smuzhiyun 	data |= (tms ? 0x00020002 : 0x00020000);
2087*4882a593Smuzhiyun 	cx_write(GP0_IO, data);
2088*4882a593Smuzhiyun 
2089*4882a593Smuzhiyun 	/*TDI*/
2090*4882a593Smuzhiyun 	data = ((cx_read(MC417_RWD)) & (~0x0000a000));
2091*4882a593Smuzhiyun 	data |= (tdi ? 0x00008000 : 0);
2092*4882a593Smuzhiyun 	cx_write(MC417_RWD, data);
2093*4882a593Smuzhiyun 	if (read_tdo)
2094*4882a593Smuzhiyun 		tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
2095*4882a593Smuzhiyun 
2096*4882a593Smuzhiyun 	cx_write(MC417_RWD, data | 0x00002000);
2097*4882a593Smuzhiyun 	udelay(1);
2098*4882a593Smuzhiyun 	/*TCK*/
2099*4882a593Smuzhiyun 	cx_write(MC417_RWD, data);
2100*4882a593Smuzhiyun 
2101*4882a593Smuzhiyun 	return tdo;
2102*4882a593Smuzhiyun }
2103*4882a593Smuzhiyun 
cx23885_ir_pci_int_enable(struct cx23885_dev * dev)2104*4882a593Smuzhiyun void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
2105*4882a593Smuzhiyun {
2106*4882a593Smuzhiyun 	switch (dev->board) {
2107*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1270:
2108*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1850:
2109*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1290:
2110*4882a593Smuzhiyun 		if (dev->sd_ir)
2111*4882a593Smuzhiyun 			cx23885_irq_add_enable(dev, PCI_MSK_IR);
2112*4882a593Smuzhiyun 		break;
2113*4882a593Smuzhiyun 	case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
2114*4882a593Smuzhiyun 	case CX23885_BOARD_TEVII_S470:
2115*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1250:
2116*4882a593Smuzhiyun 	case CX23885_BOARD_MYGICA_X8507:
2117*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6980:
2118*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6981:
2119*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T9580:
2120*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T980C:
2121*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S950C:
2122*4882a593Smuzhiyun 	case CX23885_BOARD_TT_CT2_4500_CI:
2123*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S950:
2124*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S952:
2125*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T982:
2126*4882a593Smuzhiyun 		if (dev->sd_ir)
2127*4882a593Smuzhiyun 			cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
2128*4882a593Smuzhiyun 		break;
2129*4882a593Smuzhiyun 	}
2130*4882a593Smuzhiyun }
2131*4882a593Smuzhiyun 
cx23885_card_setup(struct cx23885_dev * dev)2132*4882a593Smuzhiyun void cx23885_card_setup(struct cx23885_dev *dev)
2133*4882a593Smuzhiyun {
2134*4882a593Smuzhiyun 	struct cx23885_tsport *ts1 = &dev->ts1;
2135*4882a593Smuzhiyun 	struct cx23885_tsport *ts2 = &dev->ts2;
2136*4882a593Smuzhiyun 
2137*4882a593Smuzhiyun 	static u8 eeprom[256];
2138*4882a593Smuzhiyun 
2139*4882a593Smuzhiyun 	if (dev->i2c_bus[0].i2c_rc == 0) {
2140*4882a593Smuzhiyun 		dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
2141*4882a593Smuzhiyun 		tveeprom_read(&dev->i2c_bus[0].i2c_client,
2142*4882a593Smuzhiyun 			      eeprom, sizeof(eeprom));
2143*4882a593Smuzhiyun 	}
2144*4882a593Smuzhiyun 
2145*4882a593Smuzhiyun 	switch (dev->board) {
2146*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1250:
2147*4882a593Smuzhiyun 		if (dev->i2c_bus[0].i2c_rc == 0) {
2148*4882a593Smuzhiyun 			if (eeprom[0x80] != 0x84)
2149*4882a593Smuzhiyun 				hauppauge_eeprom(dev, eeprom+0xc0);
2150*4882a593Smuzhiyun 			else
2151*4882a593Smuzhiyun 				hauppauge_eeprom(dev, eeprom+0x80);
2152*4882a593Smuzhiyun 		}
2153*4882a593Smuzhiyun 		break;
2154*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1500:
2155*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
2156*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1400:
2157*4882a593Smuzhiyun 		if (dev->i2c_bus[0].i2c_rc == 0)
2158*4882a593Smuzhiyun 			hauppauge_eeprom(dev, eeprom+0x80);
2159*4882a593Smuzhiyun 		break;
2160*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1800:
2161*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
2162*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1200:
2163*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1700:
2164*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1270:
2165*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1275:
2166*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1255:
2167*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
2168*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1210:
2169*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1850:
2170*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1290:
2171*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR4400:
2172*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_STARBURST:
2173*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
2174*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR5525:
2175*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
2176*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_STARBURST2:
2177*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
2178*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885:
2179*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
2180*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885:
2181*4882a593Smuzhiyun 		if (dev->i2c_bus[0].i2c_rc == 0)
2182*4882a593Smuzhiyun 			hauppauge_eeprom(dev, eeprom+0xc0);
2183*4882a593Smuzhiyun 		break;
2184*4882a593Smuzhiyun 	case CX23885_BOARD_VIEWCAST_260E:
2185*4882a593Smuzhiyun 	case CX23885_BOARD_VIEWCAST_460E:
2186*4882a593Smuzhiyun 		dev->i2c_bus[1].i2c_client.addr = 0xa0 >> 1;
2187*4882a593Smuzhiyun 		tveeprom_read(&dev->i2c_bus[1].i2c_client,
2188*4882a593Smuzhiyun 			      eeprom, sizeof(eeprom));
2189*4882a593Smuzhiyun 		if (dev->i2c_bus[0].i2c_rc == 0)
2190*4882a593Smuzhiyun 			viewcast_eeprom(dev, eeprom);
2191*4882a593Smuzhiyun 		break;
2192*4882a593Smuzhiyun 	}
2193*4882a593Smuzhiyun 
2194*4882a593Smuzhiyun 	switch (dev->board) {
2195*4882a593Smuzhiyun 	case CX23885_BOARD_AVERMEDIA_HC81R:
2196*4882a593Smuzhiyun 		/* Defaults for VID B */
2197*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0x4; /* Parallel */
2198*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2199*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2200*4882a593Smuzhiyun 		/* Defaults for VID C */
2201*4882a593Smuzhiyun 		/* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
2202*4882a593Smuzhiyun 		ts2->gen_ctrl_val  = 0x10e;
2203*4882a593Smuzhiyun 		ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2204*4882a593Smuzhiyun 		ts2->src_sel_val     = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2205*4882a593Smuzhiyun 		break;
2206*4882a593Smuzhiyun 	case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
2207*4882a593Smuzhiyun 	case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
2208*4882a593Smuzhiyun 	case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
2209*4882a593Smuzhiyun 		ts2->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2210*4882a593Smuzhiyun 		ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2211*4882a593Smuzhiyun 		ts2->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2212*4882a593Smuzhiyun 		fallthrough;
2213*4882a593Smuzhiyun 	case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
2214*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2215*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2216*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2217*4882a593Smuzhiyun 		break;
2218*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1850:
2219*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1800:
2220*4882a593Smuzhiyun 		/* Defaults for VID B - Analog encoder */
2221*4882a593Smuzhiyun 		/* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
2222*4882a593Smuzhiyun 		ts1->gen_ctrl_val    = 0x10e;
2223*4882a593Smuzhiyun 		ts1->ts_clk_en_val   = 0x1; /* Enable TS_CLK */
2224*4882a593Smuzhiyun 		ts1->src_sel_val     = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2225*4882a593Smuzhiyun 
2226*4882a593Smuzhiyun 		/* APB_TSVALERR_POL (active low)*/
2227*4882a593Smuzhiyun 		ts1->vld_misc_val    = 0x2000;
2228*4882a593Smuzhiyun 		ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
2229*4882a593Smuzhiyun 		cx_write(0x130184, 0xc);
2230*4882a593Smuzhiyun 
2231*4882a593Smuzhiyun 		/* Defaults for VID C */
2232*4882a593Smuzhiyun 		ts2->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2233*4882a593Smuzhiyun 		ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2234*4882a593Smuzhiyun 		ts2->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2235*4882a593Smuzhiyun 		break;
2236*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6920:
2237*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0x4; /* Parallel */
2238*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2239*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2240*4882a593Smuzhiyun 		break;
2241*4882a593Smuzhiyun 	case CX23885_BOARD_TEVII_S470:
2242*4882a593Smuzhiyun 	case CX23885_BOARD_TEVII_S471:
2243*4882a593Smuzhiyun 	case CX23885_BOARD_DVBWORLD_2005:
2244*4882a593Smuzhiyun 	case CX23885_BOARD_PROF_8000:
2245*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T980C:
2246*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S950C:
2247*4882a593Smuzhiyun 	case CX23885_BOARD_TT_CT2_4500_CI:
2248*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S950:
2249*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0x5; /* Parallel */
2250*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2251*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2252*4882a593Smuzhiyun 		break;
2253*4882a593Smuzhiyun 	case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2254*4882a593Smuzhiyun 	case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
2255*4882a593Smuzhiyun 	case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
2256*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2257*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2258*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2259*4882a593Smuzhiyun 		ts2->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2260*4882a593Smuzhiyun 		ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2261*4882a593Smuzhiyun 		ts2->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2262*4882a593Smuzhiyun 		break;
2263*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6980:
2264*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6981:
2265*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2266*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2267*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2268*4882a593Smuzhiyun 		ts2->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2269*4882a593Smuzhiyun 		ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2270*4882a593Smuzhiyun 		ts2->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2271*4882a593Smuzhiyun 		tbs_card_init(dev);
2272*4882a593Smuzhiyun 		break;
2273*4882a593Smuzhiyun 	case CX23885_BOARD_MYGICA_X8506:
2274*4882a593Smuzhiyun 	case CX23885_BOARD_MAGICPRO_PROHDTVE2:
2275*4882a593Smuzhiyun 	case CX23885_BOARD_MYGICA_X8507:
2276*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0x5; /* Parallel */
2277*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2278*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2279*4882a593Smuzhiyun 		break;
2280*4882a593Smuzhiyun 	case CX23885_BOARD_MYGICA_X8558PRO:
2281*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0x5; /* Parallel */
2282*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2283*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2284*4882a593Smuzhiyun 		ts2->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2285*4882a593Smuzhiyun 		ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2286*4882a593Smuzhiyun 		ts2->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2287*4882a593Smuzhiyun 		break;
2288*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR4400:
2289*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2290*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2291*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2292*4882a593Smuzhiyun 		ts2->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2293*4882a593Smuzhiyun 		ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2294*4882a593Smuzhiyun 		ts2->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2295*4882a593Smuzhiyun 		break;
2296*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_STARBURST:
2297*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2298*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2299*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2300*4882a593Smuzhiyun 		break;
2301*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T9580:
2302*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T982:
2303*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0x5; /* Parallel */
2304*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2305*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2306*4882a593Smuzhiyun 		ts2->gen_ctrl_val  = 0x8; /* Serial bus */
2307*4882a593Smuzhiyun 		ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2308*4882a593Smuzhiyun 		ts2->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2309*4882a593Smuzhiyun 		break;
2310*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S952:
2311*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0x5; /* Parallel */
2312*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2313*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2314*4882a593Smuzhiyun 		ts2->gen_ctrl_val  = 0xe; /* Serial bus */
2315*4882a593Smuzhiyun 		ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2316*4882a593Smuzhiyun 		ts2->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2317*4882a593Smuzhiyun 		break;
2318*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR5525:
2319*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_STARBURST2:
2320*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0x5; /* Parallel */
2321*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2322*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2323*4882a593Smuzhiyun 		ts2->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2324*4882a593Smuzhiyun 		ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2325*4882a593Smuzhiyun 		ts2->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2326*4882a593Smuzhiyun 		break;
2327*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
2328*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
2329*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885:
2330*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
2331*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885:
2332*4882a593Smuzhiyun 		ts1->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2333*4882a593Smuzhiyun 		ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2334*4882a593Smuzhiyun 		ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2335*4882a593Smuzhiyun 		ts2->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2336*4882a593Smuzhiyun 		ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2337*4882a593Smuzhiyun 		ts2->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2338*4882a593Smuzhiyun 		break;
2339*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1250:
2340*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1500:
2341*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
2342*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
2343*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1200:
2344*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1700:
2345*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1400:
2346*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
2347*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
2348*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
2349*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
2350*4882a593Smuzhiyun 	case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
2351*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1270:
2352*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1275:
2353*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1255:
2354*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
2355*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1210:
2356*4882a593Smuzhiyun 	case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
2357*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1290:
2358*4882a593Smuzhiyun 	case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
2359*4882a593Smuzhiyun 	default:
2360*4882a593Smuzhiyun 		ts2->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
2361*4882a593Smuzhiyun 		ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2362*4882a593Smuzhiyun 		ts2->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2363*4882a593Smuzhiyun 	}
2364*4882a593Smuzhiyun 
2365*4882a593Smuzhiyun 	/* Certain boards support analog, or require the avcore to be
2366*4882a593Smuzhiyun 	 * loaded, ensure this happens.
2367*4882a593Smuzhiyun 	 */
2368*4882a593Smuzhiyun 	switch (dev->board) {
2369*4882a593Smuzhiyun 	case CX23885_BOARD_TEVII_S470:
2370*4882a593Smuzhiyun 		/* Currently only enabled for the integrated IR controller */
2371*4882a593Smuzhiyun 		if (!enable_885_ir)
2372*4882a593Smuzhiyun 			break;
2373*4882a593Smuzhiyun 		fallthrough;
2374*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1250:
2375*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1800:
2376*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
2377*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
2378*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1700:
2379*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
2380*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
2381*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
2382*4882a593Smuzhiyun 	case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
2383*4882a593Smuzhiyun 	case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2384*4882a593Smuzhiyun 	case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
2385*4882a593Smuzhiyun 	case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
2386*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1255:
2387*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
2388*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
2389*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
2390*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
2391*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1270:
2392*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1850:
2393*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR5525:
2394*4882a593Smuzhiyun 	case CX23885_BOARD_MYGICA_X8506:
2395*4882a593Smuzhiyun 	case CX23885_BOARD_MAGICPRO_PROHDTVE2:
2396*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1290:
2397*4882a593Smuzhiyun 	case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
2398*4882a593Smuzhiyun 	case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
2399*4882a593Smuzhiyun 	case CX23885_BOARD_HAUPPAUGE_HVR1500:
2400*4882a593Smuzhiyun 	case CX23885_BOARD_MPX885:
2401*4882a593Smuzhiyun 	case CX23885_BOARD_MYGICA_X8507:
2402*4882a593Smuzhiyun 	case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
2403*4882a593Smuzhiyun 	case CX23885_BOARD_AVERMEDIA_HC81R:
2404*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6980:
2405*4882a593Smuzhiyun 	case CX23885_BOARD_TBS_6981:
2406*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T9580:
2407*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T980C:
2408*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S950C:
2409*4882a593Smuzhiyun 	case CX23885_BOARD_TT_CT2_4500_CI:
2410*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S950:
2411*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_S952:
2412*4882a593Smuzhiyun 	case CX23885_BOARD_DVBSKY_T982:
2413*4882a593Smuzhiyun 	case CX23885_BOARD_VIEWCAST_260E:
2414*4882a593Smuzhiyun 	case CX23885_BOARD_VIEWCAST_460E:
2415*4882a593Smuzhiyun 	case CX23885_BOARD_AVERMEDIA_CE310B:
2416*4882a593Smuzhiyun 		dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
2417*4882a593Smuzhiyun 				&dev->i2c_bus[2].i2c_adap,
2418*4882a593Smuzhiyun 				"cx25840", 0x88 >> 1, NULL);
2419*4882a593Smuzhiyun 		if (dev->sd_cx25840) {
2420*4882a593Smuzhiyun 			/* set host data for clk_freq configuration */
2421*4882a593Smuzhiyun 			v4l2_set_subdev_hostdata(dev->sd_cx25840,
2422*4882a593Smuzhiyun 						&dev->clk_freq);
2423*4882a593Smuzhiyun 
2424*4882a593Smuzhiyun 			dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
2425*4882a593Smuzhiyun 			v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
2426*4882a593Smuzhiyun 		}
2427*4882a593Smuzhiyun 		break;
2428*4882a593Smuzhiyun 	}
2429*4882a593Smuzhiyun 
2430*4882a593Smuzhiyun 	switch (dev->board) {
2431*4882a593Smuzhiyun 	case CX23885_BOARD_VIEWCAST_260E:
2432*4882a593Smuzhiyun 		v4l2_i2c_new_subdev(&dev->v4l2_dev,
2433*4882a593Smuzhiyun 				&dev->i2c_bus[0].i2c_adap,
2434*4882a593Smuzhiyun 				"cs3308", 0x82 >> 1, NULL);
2435*4882a593Smuzhiyun 		break;
2436*4882a593Smuzhiyun 	case CX23885_BOARD_VIEWCAST_460E:
2437*4882a593Smuzhiyun 		/* This cs3308 controls the audio from the breakout cable */
2438*4882a593Smuzhiyun 		v4l2_i2c_new_subdev(&dev->v4l2_dev,
2439*4882a593Smuzhiyun 				&dev->i2c_bus[0].i2c_adap,
2440*4882a593Smuzhiyun 				"cs3308", 0x80 >> 1, NULL);
2441*4882a593Smuzhiyun 		/* This cs3308 controls the audio from the onboard header */
2442*4882a593Smuzhiyun 		v4l2_i2c_new_subdev(&dev->v4l2_dev,
2443*4882a593Smuzhiyun 				&dev->i2c_bus[0].i2c_adap,
2444*4882a593Smuzhiyun 				"cs3308", 0x82 >> 1, NULL);
2445*4882a593Smuzhiyun 		break;
2446*4882a593Smuzhiyun 	}
2447*4882a593Smuzhiyun 
2448*4882a593Smuzhiyun 	/* AUX-PLL 27MHz CLK */
2449*4882a593Smuzhiyun 	switch (dev->board) {
2450*4882a593Smuzhiyun 	case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2451*4882a593Smuzhiyun 		netup_initialize(dev);
2452*4882a593Smuzhiyun 		break;
2453*4882a593Smuzhiyun 	case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
2454*4882a593Smuzhiyun 		int ret;
2455*4882a593Smuzhiyun 		const struct firmware *fw;
2456*4882a593Smuzhiyun 		const char *filename = "dvb-netup-altera-01.fw";
2457*4882a593Smuzhiyun 		char *action = "configure";
2458*4882a593Smuzhiyun 		static struct netup_card_info cinfo;
2459*4882a593Smuzhiyun 		struct altera_config netup_config = {
2460*4882a593Smuzhiyun 			.dev = dev,
2461*4882a593Smuzhiyun 			.action = action,
2462*4882a593Smuzhiyun 			.jtag_io = netup_jtag_io,
2463*4882a593Smuzhiyun 		};
2464*4882a593Smuzhiyun 
2465*4882a593Smuzhiyun 		netup_initialize(dev);
2466*4882a593Smuzhiyun 
2467*4882a593Smuzhiyun 		netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
2468*4882a593Smuzhiyun 		if (netup_card_rev)
2469*4882a593Smuzhiyun 			cinfo.rev = netup_card_rev;
2470*4882a593Smuzhiyun 
2471*4882a593Smuzhiyun 		switch (cinfo.rev) {
2472*4882a593Smuzhiyun 		case 0x4:
2473*4882a593Smuzhiyun 			filename = "dvb-netup-altera-04.fw";
2474*4882a593Smuzhiyun 			break;
2475*4882a593Smuzhiyun 		default:
2476*4882a593Smuzhiyun 			filename = "dvb-netup-altera-01.fw";
2477*4882a593Smuzhiyun 			break;
2478*4882a593Smuzhiyun 		}
2479*4882a593Smuzhiyun 		pr_info("NetUP card rev=0x%x fw_filename=%s\n",
2480*4882a593Smuzhiyun 			cinfo.rev, filename);
2481*4882a593Smuzhiyun 
2482*4882a593Smuzhiyun 		ret = request_firmware(&fw, filename, &dev->pci->dev);
2483*4882a593Smuzhiyun 		if (ret != 0)
2484*4882a593Smuzhiyun 			pr_err("did not find the firmware file '%s'. You can use <kernel_dir>/scripts/get_dvb_firmware to get the firmware.",
2485*4882a593Smuzhiyun 			       filename);
2486*4882a593Smuzhiyun 		else
2487*4882a593Smuzhiyun 			altera_init(&netup_config, fw);
2488*4882a593Smuzhiyun 
2489*4882a593Smuzhiyun 		release_firmware(fw);
2490*4882a593Smuzhiyun 		break;
2491*4882a593Smuzhiyun 	}
2492*4882a593Smuzhiyun 	}
2493*4882a593Smuzhiyun }
2494