1*4882a593Smuzhiyun* Altera Arria10 Development Kit System Resource Chip 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired parent device properties: 4*4882a593Smuzhiyun- compatible : "altr,a10sr" 5*4882a593Smuzhiyun- spi-max-frequency : Maximum SPI frequency. 6*4882a593Smuzhiyun- reg : The SPI Chip Select address for the Arria10 7*4882a593Smuzhiyun System Resource chip 8*4882a593Smuzhiyun- interrupts : The interrupt line the device is connected to. 9*4882a593Smuzhiyun- interrupt-controller : Marks the device node as an interrupt controller. 10*4882a593Smuzhiyun- #interrupt-cells : The number of cells to describe an IRQ, should be 2. 11*4882a593Smuzhiyun The first cell is the IRQ number. 12*4882a593Smuzhiyun The second cell is the flags, encoded as trigger 13*4882a593Smuzhiyun masks from ../interrupt-controller/interrupts.txt. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunThe A10SR consists of these sub-devices: 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunDevice Description 18*4882a593Smuzhiyun------ ---------- 19*4882a593Smuzhiyuna10sr_gpio GPIO Controller 20*4882a593Smuzhiyuna10sr_rst Reset Controller 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunArria10 GPIO 23*4882a593SmuzhiyunRequired Properties: 24*4882a593Smuzhiyun- compatible : Should be "altr,a10sr-gpio" 25*4882a593Smuzhiyun- gpio-controller : Marks the device node as a GPIO Controller. 26*4882a593Smuzhiyun- #gpio-cells : Should be two. The first cell is the pin number and 27*4882a593Smuzhiyun the second cell is used to specify flags. 28*4882a593Smuzhiyun See ../gpio/gpio.txt for more information. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunArria10 Peripheral PHY Reset 31*4882a593SmuzhiyunRequired Properties: 32*4882a593Smuzhiyun- compatible : Should be "altr,a10sr-reset" 33*4882a593Smuzhiyun- #reset-cells : Should be one. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunExample: 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun resource-manager@0 { 38*4882a593Smuzhiyun compatible = "altr,a10sr"; 39*4882a593Smuzhiyun reg = <0>; 40*4882a593Smuzhiyun spi-max-frequency = <100000>; 41*4882a593Smuzhiyun interrupt-parent = <&portb>; 42*4882a593Smuzhiyun interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 43*4882a593Smuzhiyun interrupt-controller; 44*4882a593Smuzhiyun #interrupt-cells = <2>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun a10sr_gpio: gpio-controller { 47*4882a593Smuzhiyun compatible = "altr,a10sr-gpio"; 48*4882a593Smuzhiyun gpio-controller; 49*4882a593Smuzhiyun #gpio-cells = <2>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun a10sr_rst: reset-controller { 53*4882a593Smuzhiyun compatible = "altr,a10sr-reset"; 54*4882a593Smuzhiyun #reset-cells = <1>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57