mips/dts/brcm%2Cbcm3380.dtsi

4  * SPDX-License-Identifier:	GPL-2.0+
7 #include <dt-bindings/clock/bcm3380-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm3380-reset.h>
17 		#address-cells = <1>;
18 		#size-cells = <0>;
19 		u-boot,dm-pre-reloc;
22 			compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
25 			u-boot,dm-pre-reloc;
29 			compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
32 			u-boot,dm-pre-reloc;
37 		compatible = "simple-bus";
38 		#address-cells = <1>;
39 		#size-cells = <1>;
40 		u-boot,dm-pre-reloc;
42 		periph_osc: periph-osc {
43 			compatible = "fixed-clock";
44 			#clock-cells = <0>;
45 			clock-frequency = <48000000>;
46 			u-boot,dm-pre-reloc;
49 		periph_clk0: periph-clk@14e00004 {
50 			compatible = "brcm,bcm6345-clk";
52 			#clock-cells = <1>;
55 		periph_clk1: periph-clk@14e00008 {
56 			compatible = "brcm,bcm6345-clk";
58 			#clock-cells = <1>;
63 		compatible = "simple-bus";
64 		#address-cells = <1>;
65 		#size-cells = <1>;
66 		u-boot,dm-pre-reloc;
68 		memory-controller@12000000 {
69 			compatible = "brcm,bcm6328-mc";
71 			u-boot,dm-pre-reloc;
74 		periph_rst0: reset-controller@14e0008c {
75 			compatible = "brcm,bcm6345-reset";
77 			#reset-cells = <1>;
80 		periph_rst1: reset-controller@14e00090 {
81 			compatible = "brcm,bcm6345-reset";
83 			#reset-cells = <1>;
91 		syscon-reboot {
92 			compatible = "syscon-reboot";
99 			compatible = "brcm,bcm6345-wdt";
105 		wdt-reboot {
106 			compatible = "wdt-reboot";
110 		gpio0: gpio-controller@14e00100 {
111 			compatible = "brcm,bcm6345-gpio";
113 			gpio-controller;
114 			#gpio-cells = <2>;
119 		gpio1: gpio-controller@14e00104 {
120 			compatible = "brcm,bcm6345-gpio";
122 			gpio-controller;
123 			#gpio-cells = <2>;
130 			compatible = "brcm,bcm6345-uart";
138 			compatible = "brcm,bcm6345-uart";
145 		leds: led-controller@14e00f00 {
146 			compatible = "brcm,bcm6328-leds";
148 			#address-cells = <1>;
149 			#size-cells = <0>;