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Searched full:pll7 (Results 1 – 18 of 18) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun4i-a10.dtsi265 pll7: clk@01c20030 { label
270 clock-output-names = "pll7";
278 clocks = <&pll7>;
279 clock-output-names = "pll7-2x";
586 clocks = <&pll3>, <&pll7>, <&pll5 1>;
595 clocks = <&pll3>, <&pll7>, <&pll5 1>;
604 clocks = <&pll3>, <&pll7>, <&pll5 1>;
613 clocks = <&pll3>, <&pll7>, <&pll5 1>;
623 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
633 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
[all …]
H A Dsun5i-a13.dtsi179 clocks = <&pll3>, <&pll7>, <&pll5 1>;
188 clocks = <&pll3>, <&pll7>, <&pll5 1>;
197 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
205 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
H A Dsun7i-a20.dtsi268 pll7: clk@01c20030 { label
273 clock-output-names = "pll7";
279 clocks = <&pll7>;
282 clock-output-names = "pll7-2x";
637 clocks = <&pll3>, <&pll7>, <&pll5 1>;
646 clocks = <&pll3>, <&pll7>, <&pll5 1>;
655 clocks = <&pll3>, <&pll7>, <&pll5 1>;
664 clocks = <&pll3>, <&pll7>, <&pll5 1>;
673 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
683 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
[all …]
H A Dsun5i-gr8.dtsi165 pll7: clk@01c20030 { label
170 clock-output-names = "pll7";
178 clocks = <&pll7>;
179 clock-output-names = "pll7-2x";
439 clocks = <&pll3>, <&pll7>, <&pll5 1>;
448 clocks = <&pll3>, <&pll7>, <&pll5 1>;
457 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
465 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
H A Dsun5i.dtsi165 pll7: clk@01c20030 { label
170 clock-output-names = "pll7";
178 clocks = <&pll7>;
179 clock-output-names = "pll7-2x";
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-tcon-ch0-clk.yaml64 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
73 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
H A Dallwinner,sun4i-a10-display-clk.yaml53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun8i_a83t.h29 u32 pll7_cfg; /* 0x38 pll7 gpu control */
102 u32 pll8_bias_cfg; /* 0x23c PLL7 Bias config */
H A Dclock_sun6i.h27 u32 pll7_cfg; /* 0x30 pll7 control */
129 u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */
143 u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */
H A Dclock_sun4i.h27 u32 pll7_cfg; /* 0x30 pll7 control */
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-milbeaut.c26 #define M10V_PLL7 "pll7"
27 #define M10V_PLL7DIV2 "pll7-2"
28 #define M10V_PLL7DIV5 "pll7-5"
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-imx6sll.c29 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
129 …hws[IMX6SLL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0… in imx6sll_clocks_init()
H A Dclk-vf610.c83 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
225 …clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll7", "pll7_bypass_src", PLL7_CTRL,… in vf610_clocks_init()
H A Dclk-imx6sl.c69 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
222 hws[IMX6SL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); in imx6sl_clocks_init()
H A Dclk-imx6ul.c27 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
155 hws[IMX6UL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); in imx6ul_clocks_init()
H A Dclk-imx6sx.c83 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
166 hws[IMX6SX_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); in imx6sx_clocks_init()
H A Dclk-imx6q.c90 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
483 hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); in imx6q_clocks_init()
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/include/gaudi/
H A Dgaudi_async_ids_map_extended.h272 { .fc_id = 246, .cpu_id = 119, .valid = 1, .name = "PLL7" },