1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2014 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <dt-bindings/clock/imx6sx-clock.h>
7*4882a593Smuzhiyun #include <linux/bits.h>
8*4882a593Smuzhiyun #include <linux/clk.h>
9*4882a593Smuzhiyun #include <linux/clkdev.h>
10*4882a593Smuzhiyun #include <linux/clk-provider.h>
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/of_address.h>
16*4882a593Smuzhiyun #include <linux/of_irq.h>
17*4882a593Smuzhiyun #include <linux/types.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "clk.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
22*4882a593Smuzhiyun static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
23*4882a593Smuzhiyun static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
24*4882a593Smuzhiyun static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
25*4882a593Smuzhiyun static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
26*4882a593Smuzhiyun static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
27*4882a593Smuzhiyun static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
28*4882a593Smuzhiyun static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
29*4882a593Smuzhiyun static const char *ocram_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
30*4882a593Smuzhiyun static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
31*4882a593Smuzhiyun static const char *gpu_axi_sels[] = { "pll2_pfd2_396m", "pll3_pfd0_720m", "pll3_pfd1_540m", "pll2_bus", };
32*4882a593Smuzhiyun static const char *gpu_core_sels[] = { "pll3_pfd1_540m", "pll3_pfd0_720m", "pll2_bus", "pll2_pfd2_396m", };
33*4882a593Smuzhiyun static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
34*4882a593Smuzhiyun static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
35*4882a593Smuzhiyun static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
36*4882a593Smuzhiyun static const char *ldb_di1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
37*4882a593Smuzhiyun static const char *pcie_axi_sels[] = { "axi", "ahb", };
38*4882a593Smuzhiyun static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", };
39*4882a593Smuzhiyun static const char *qspi1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
40*4882a593Smuzhiyun static const char *perclk_sels[] = { "ipg", "osc", };
41*4882a593Smuzhiyun static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
42*4882a593Smuzhiyun static const char *vid_sels[] = { "pll3_pfd1_540m", "pll3_usb_otg", "pll3_pfd3_454m", "pll4_audio_div", "pll5_video_div", };
43*4882a593Smuzhiyun static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", "dummy", };
44*4882a593Smuzhiyun static const char *uart_sels[] = { "pll3_80m", "osc", };
45*4882a593Smuzhiyun static const char *qspi2_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", };
46*4882a593Smuzhiyun static const char *enet_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
47*4882a593Smuzhiyun static const char *enet_sels[] = { "enet_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
48*4882a593Smuzhiyun static const char *m4_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "osc", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd3_454m", };
49*4882a593Smuzhiyun static const char *m4_sels[] = { "m4_pre_sel", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
50*4882a593Smuzhiyun static const char *eim_slow_sels[] = { "ocram", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
51*4882a593Smuzhiyun static const char *ecspi_sels[] = { "pll3_60m", "osc", };
52*4882a593Smuzhiyun static const char *lcdif1_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
53*4882a593Smuzhiyun static const char *lcdif1_sels[] = { "lcdif1_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
54*4882a593Smuzhiyun static const char *lcdif2_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd3_594m", "pll3_pfd1_540m", };
55*4882a593Smuzhiyun static const char *lcdif2_sels[] = { "lcdif2_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
56*4882a593Smuzhiyun static const char *display_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll3_usb_otg", "pll3_pfd1_540m", };
57*4882a593Smuzhiyun static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
58*4882a593Smuzhiyun static const char *cko1_sels[] = {
59*4882a593Smuzhiyun "dummy", "dummy", "dummy", "dummy",
60*4882a593Smuzhiyun "vadc", "ocram", "qspi2", "m4", "enet_ahb", "lcdif2_pix",
61*4882a593Smuzhiyun "lcdif1_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun static const char *cko2_sels[] = {
64*4882a593Smuzhiyun "dummy", "mmdc_p0_fast", "usdhc4", "usdhc1", "dummy", "wrck",
65*4882a593Smuzhiyun "ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",
66*4882a593Smuzhiyun "display_axi", "dummy", "osc", "dummy", "dummy",
67*4882a593Smuzhiyun "usdhc2", "ssi1", "ssi2", "ssi3", "gpu_axi_podf", "dummy",
68*4882a593Smuzhiyun "can_podf", "lvds1_out", "qspi1", "esai_extal", "eim_slow",
69*4882a593Smuzhiyun "uart_serial", "spdif", "audio", "dummy",
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun static const char *cko_sels[] = { "cko1", "cko2", };
72*4882a593Smuzhiyun static const char *lvds_sels[] = {
73*4882a593Smuzhiyun "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
74*4882a593Smuzhiyun "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
77*4882a593Smuzhiyun static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
78*4882a593Smuzhiyun static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
79*4882a593Smuzhiyun static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
80*4882a593Smuzhiyun static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
81*4882a593Smuzhiyun static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
82*4882a593Smuzhiyun static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
83*4882a593Smuzhiyun static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static struct clk_hw **hws;
86*4882a593Smuzhiyun static struct clk_hw_onecell_data *clk_hw_data;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static const struct clk_div_table clk_enet_ref_table[] = {
89*4882a593Smuzhiyun { .val = 0, .div = 20, },
90*4882a593Smuzhiyun { .val = 1, .div = 10, },
91*4882a593Smuzhiyun { .val = 2, .div = 5, },
92*4882a593Smuzhiyun { .val = 3, .div = 4, },
93*4882a593Smuzhiyun { }
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static const struct clk_div_table post_div_table[] = {
97*4882a593Smuzhiyun { .val = 2, .div = 1, },
98*4882a593Smuzhiyun { .val = 1, .div = 2, },
99*4882a593Smuzhiyun { .val = 0, .div = 4, },
100*4882a593Smuzhiyun { }
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static const struct clk_div_table video_div_table[] = {
104*4882a593Smuzhiyun { .val = 0, .div = 1, },
105*4882a593Smuzhiyun { .val = 1, .div = 2, },
106*4882a593Smuzhiyun { .val = 2, .div = 1, },
107*4882a593Smuzhiyun { .val = 3, .div = 4, },
108*4882a593Smuzhiyun { }
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun static u32 share_count_asrc;
112*4882a593Smuzhiyun static u32 share_count_audio;
113*4882a593Smuzhiyun static u32 share_count_esai;
114*4882a593Smuzhiyun static u32 share_count_ssi1;
115*4882a593Smuzhiyun static u32 share_count_ssi2;
116*4882a593Smuzhiyun static u32 share_count_ssi3;
117*4882a593Smuzhiyun static u32 share_count_sai1;
118*4882a593Smuzhiyun static u32 share_count_sai2;
119*4882a593Smuzhiyun
imx6sx_clocks_init(struct device_node * ccm_node)120*4882a593Smuzhiyun static void __init imx6sx_clocks_init(struct device_node *ccm_node)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun struct device_node *np;
123*4882a593Smuzhiyun void __iomem *base;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
126*4882a593Smuzhiyun IMX6SX_CLK_CLK_END), GFP_KERNEL);
127*4882a593Smuzhiyun if (WARN_ON(!clk_hw_data))
128*4882a593Smuzhiyun return;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun clk_hw_data->num = IMX6SX_CLK_CLK_END;
131*4882a593Smuzhiyun hws = clk_hw_data->hws;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun hws[IMX6SX_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
136*4882a593Smuzhiyun hws[IMX6SX_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /* ipp_di clock is external input */
139*4882a593Smuzhiyun hws[IMX6SX_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");
140*4882a593Smuzhiyun hws[IMX6SX_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* Clock source from external clock via CLK1/2 PAD */
143*4882a593Smuzhiyun hws[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk1");
144*4882a593Smuzhiyun hws[IMX6SX_CLK_ANACLK2] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk2");
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
147*4882a593Smuzhiyun base = of_iomap(np, 0);
148*4882a593Smuzhiyun WARN_ON(!base);
149*4882a593Smuzhiyun of_node_put(np);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun hws[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
152*4882a593Smuzhiyun hws[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
153*4882a593Smuzhiyun hws[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
154*4882a593Smuzhiyun hws[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
155*4882a593Smuzhiyun hws[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
156*4882a593Smuzhiyun hws[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
157*4882a593Smuzhiyun hws[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /* type name parent_name base div_mask */
160*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
161*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
162*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
163*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
164*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
165*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
166*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun hws[IMX6SX_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
169*4882a593Smuzhiyun hws[IMX6SX_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
170*4882a593Smuzhiyun hws[IMX6SX_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
171*4882a593Smuzhiyun hws[IMX6SX_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
172*4882a593Smuzhiyun hws[IMX6SX_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
173*4882a593Smuzhiyun hws[IMX6SX_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
174*4882a593Smuzhiyun hws[IMX6SX_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /* Do not bypass PLLs initially */
177*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk);
178*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk);
179*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk);
180*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk);
181*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_PLL5_BYPASS]->clk, hws[IMX6SX_CLK_PLL5]->clk);
182*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk);
183*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
186*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
187*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
188*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
189*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
190*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
191*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /*
194*4882a593Smuzhiyun * Bit 20 is the reserved and read-only bit, we do this only for:
195*4882a593Smuzhiyun * - Do nothing for usbphy clk_enable/disable
196*4882a593Smuzhiyun * - Keep refcount when do usbphy clk_enable/disable, in that case,
197*4882a593Smuzhiyun * the clk framework may need to enable/disable usbphy's parent
198*4882a593Smuzhiyun */
199*4882a593Smuzhiyun hws[IMX6SX_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
200*4882a593Smuzhiyun hws[IMX6SX_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun /*
203*4882a593Smuzhiyun * usbphy*_gate needs to be on after system boots up, and software
204*4882a593Smuzhiyun * never needs to control it anymore.
205*4882a593Smuzhiyun */
206*4882a593Smuzhiyun hws[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6);
207*4882a593Smuzhiyun hws[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6);
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun /* FIXME 100MHz is used for pcie ref for all imx6 pcie, excepted imx6q */
210*4882a593Smuzhiyun hws[IMX6SX_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
211*4882a593Smuzhiyun hws[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_hw_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun hws[IMX6SX_CLK_LVDS1_OUT] = imx_clk_hw_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
214*4882a593Smuzhiyun hws[IMX6SX_CLK_LVDS2_OUT] = imx_clk_hw_gate_exclusive("lvds2_out", "lvds2_sel", base + 0x160, 11, BIT(13));
215*4882a593Smuzhiyun hws[IMX6SX_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
216*4882a593Smuzhiyun hws[IMX6SX_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun hws[IMX6SX_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
219*4882a593Smuzhiyun base + 0xe0, 0, 2, 0, clk_enet_ref_table,
220*4882a593Smuzhiyun &imx_ccm_lock);
221*4882a593Smuzhiyun hws[IMX6SX_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0,
222*4882a593Smuzhiyun base + 0xe0, 2, 2, 0, clk_enet_ref_table,
223*4882a593Smuzhiyun &imx_ccm_lock);
224*4882a593Smuzhiyun hws[IMX6SX_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun hws[IMX6SX_CLK_ENET_PTP_REF] = imx_clk_hw_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
227*4882a593Smuzhiyun hws[IMX6SX_CLK_ENET_PTP] = imx_clk_hw_gate("enet_ptp_25m", "enet_ptp_ref", base + 0xe0, 21);
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun /* name parent_name reg idx */
230*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
231*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
232*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
233*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL2_PFD3] = imx_clk_hw_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3);
234*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
235*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
236*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
237*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /* name parent_name mult div */
240*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL2_198M] = imx_clk_hw_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
241*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL3_120M] = imx_clk_hw_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
242*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
243*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL3_60M] = imx_clk_hw_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
244*4882a593Smuzhiyun hws[IMX6SX_CLK_TWD] = imx_clk_hw_fixed_factor("twd", "arm", 1, 2);
245*4882a593Smuzhiyun hws[IMX6SX_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc", 1, 8);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
248*4882a593Smuzhiyun CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
249*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
250*4882a593Smuzhiyun CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
251*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video",
252*4882a593Smuzhiyun CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
253*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
254*4882a593Smuzhiyun CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun /* name reg shift width parent_names num_parents */
257*4882a593Smuzhiyun hws[IMX6SX_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
258*4882a593Smuzhiyun hws[IMX6SX_CLK_LVDS2_SEL] = imx_clk_hw_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun np = ccm_node;
261*4882a593Smuzhiyun base = of_iomap(np, 0);
262*4882a593Smuzhiyun WARN_ON(!base);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /* name reg shift width parent_names num_parents */
265*4882a593Smuzhiyun hws[IMX6SX_CLK_STEP] = imx_clk_hw_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
266*4882a593Smuzhiyun hws[IMX6SX_CLK_PLL1_SW] = imx_clk_hw_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
267*4882a593Smuzhiyun hws[IMX6SX_CLK_OCRAM_SEL] = imx_clk_hw_mux("ocram_sel", base + 0x14, 6, 2, ocram_sels, ARRAY_SIZE(ocram_sels));
268*4882a593Smuzhiyun hws[IMX6SX_CLK_PERIPH_PRE] = imx_clk_hw_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
269*4882a593Smuzhiyun hws[IMX6SX_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
270*4882a593Smuzhiyun hws[IMX6SX_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
271*4882a593Smuzhiyun hws[IMX6SX_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
272*4882a593Smuzhiyun hws[IMX6SX_CLK_PCIE_AXI_SEL] = imx_clk_hw_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
273*4882a593Smuzhiyun hws[IMX6SX_CLK_GPU_AXI_SEL] = imx_clk_hw_mux("gpu_axi_sel", base + 0x18, 8, 2, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
274*4882a593Smuzhiyun hws[IMX6SX_CLK_GPU_CORE_SEL] = imx_clk_hw_mux("gpu_core_sel", base + 0x18, 4, 2, gpu_core_sels, ARRAY_SIZE(gpu_core_sels));
275*4882a593Smuzhiyun hws[IMX6SX_CLK_EIM_SLOW_SEL] = imx_clk_hw_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
276*4882a593Smuzhiyun hws[IMX6SX_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
277*4882a593Smuzhiyun hws[IMX6SX_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
278*4882a593Smuzhiyun hws[IMX6SX_CLK_USDHC3_SEL] = imx_clk_hw_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
279*4882a593Smuzhiyun hws[IMX6SX_CLK_USDHC4_SEL] = imx_clk_hw_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
280*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI3_SEL] = imx_clk_hw_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
281*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI2_SEL] = imx_clk_hw_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
282*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI1_SEL] = imx_clk_hw_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
283*4882a593Smuzhiyun hws[IMX6SX_CLK_QSPI1_SEL] = imx_clk_hw_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels));
284*4882a593Smuzhiyun hws[IMX6SX_CLK_PERCLK_SEL] = imx_clk_hw_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
285*4882a593Smuzhiyun hws[IMX6SX_CLK_VID_SEL] = imx_clk_hw_mux("vid_sel", base + 0x20, 21, 3, vid_sels, ARRAY_SIZE(vid_sels));
286*4882a593Smuzhiyun hws[IMX6SX_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
287*4882a593Smuzhiyun hws[IMX6SX_CLK_CAN_SEL] = imx_clk_hw_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
288*4882a593Smuzhiyun hws[IMX6SX_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
289*4882a593Smuzhiyun hws[IMX6SX_CLK_QSPI2_SEL] = imx_clk_hw_mux("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels));
290*4882a593Smuzhiyun hws[IMX6SX_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
291*4882a593Smuzhiyun hws[IMX6SX_CLK_AUDIO_SEL] = imx_clk_hw_mux("audio_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
292*4882a593Smuzhiyun hws[IMX6SX_CLK_ENET_PRE_SEL] = imx_clk_hw_mux("enet_pre_sel", base + 0x34, 15, 3, enet_pre_sels, ARRAY_SIZE(enet_pre_sels));
293*4882a593Smuzhiyun hws[IMX6SX_CLK_ENET_SEL] = imx_clk_hw_mux("enet_sel", base + 0x34, 9, 3, enet_sels, ARRAY_SIZE(enet_sels));
294*4882a593Smuzhiyun hws[IMX6SX_CLK_M4_PRE_SEL] = imx_clk_hw_mux("m4_pre_sel", base + 0x34, 6, 3, m4_pre_sels, ARRAY_SIZE(m4_pre_sels));
295*4882a593Smuzhiyun hws[IMX6SX_CLK_M4_SEL] = imx_clk_hw_mux("m4_sel", base + 0x34, 0, 3, m4_sels, ARRAY_SIZE(m4_sels));
296*4882a593Smuzhiyun hws[IMX6SX_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
297*4882a593Smuzhiyun hws[IMX6SX_CLK_LCDIF2_PRE_SEL] = imx_clk_hw_mux("lcdif2_pre_sel", base + 0x38, 6, 3, lcdif2_pre_sels, ARRAY_SIZE(lcdif2_pre_sels));
298*4882a593Smuzhiyun hws[IMX6SX_CLK_LCDIF2_SEL] = imx_clk_hw_mux("lcdif2_sel", base + 0x38, 0, 3, lcdif2_sels, ARRAY_SIZE(lcdif2_sels));
299*4882a593Smuzhiyun hws[IMX6SX_CLK_DISPLAY_SEL] = imx_clk_hw_mux("display_sel", base + 0x3c, 14, 2, display_sels, ARRAY_SIZE(display_sels));
300*4882a593Smuzhiyun hws[IMX6SX_CLK_CSI_SEL] = imx_clk_hw_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
301*4882a593Smuzhiyun hws[IMX6SX_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
302*4882a593Smuzhiyun hws[IMX6SX_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
303*4882a593Smuzhiyun hws[IMX6SX_CLK_CKO] = imx_clk_hw_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun hws[IMX6SX_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
306*4882a593Smuzhiyun hws[IMX6SX_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
307*4882a593Smuzhiyun hws[IMX6SX_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels), CLK_SET_RATE_PARENT);
308*4882a593Smuzhiyun hws[IMX6SX_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels), CLK_SET_RATE_PARENT);
309*4882a593Smuzhiyun hws[IMX6SX_CLK_LCDIF1_PRE_SEL] = imx_clk_hw_mux_flags("lcdif1_pre_sel", base + 0x38, 15, 3, lcdif1_pre_sels, ARRAY_SIZE(lcdif1_pre_sels), CLK_SET_RATE_PARENT);
310*4882a593Smuzhiyun hws[IMX6SX_CLK_LCDIF1_SEL] = imx_clk_hw_mux_flags("lcdif1_sel", base + 0x38, 9, 3, lcdif1_sels, ARRAY_SIZE(lcdif1_sels), CLK_SET_RATE_PARENT);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun /* name parent_name reg shift width */
313*4882a593Smuzhiyun hws[IMX6SX_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
314*4882a593Smuzhiyun hws[IMX6SX_CLK_PERIPH2_CLK2] = imx_clk_hw_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
315*4882a593Smuzhiyun hws[IMX6SX_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2);
316*4882a593Smuzhiyun hws[IMX6SX_CLK_GPU_CORE_PODF] = imx_clk_hw_divider("gpu_core_podf", "gpu_core_sel", base + 0x18, 29, 3);
317*4882a593Smuzhiyun hws[IMX6SX_CLK_GPU_AXI_PODF] = imx_clk_hw_divider("gpu_axi_podf", "gpu_axi_sel", base + 0x18, 26, 3);
318*4882a593Smuzhiyun hws[IMX6SX_CLK_LCDIF1_PODF] = imx_clk_hw_divider("lcdif1_podf", "lcdif1_pred", base + 0x18, 23, 3);
319*4882a593Smuzhiyun hws[IMX6SX_CLK_QSPI1_PODF] = imx_clk_hw_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3);
320*4882a593Smuzhiyun hws[IMX6SX_CLK_EIM_SLOW_PODF] = imx_clk_hw_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
321*4882a593Smuzhiyun hws[IMX6SX_CLK_LCDIF2_PODF] = imx_clk_hw_divider("lcdif2_podf", "lcdif2_pred", base + 0x1c, 20, 3);
322*4882a593Smuzhiyun hws[IMX6SX_CLK_PERCLK] = imx_clk_hw_divider_flags("perclk", "perclk_sel", base + 0x1c, 0, 6, CLK_IS_CRITICAL);
323*4882a593Smuzhiyun hws[IMX6SX_CLK_VID_PODF] = imx_clk_hw_divider("vid_podf", "vid_sel", base + 0x20, 24, 2);
324*4882a593Smuzhiyun hws[IMX6SX_CLK_CAN_PODF] = imx_clk_hw_divider("can_podf", "can_sel", base + 0x20, 2, 6);
325*4882a593Smuzhiyun hws[IMX6SX_CLK_USDHC4_PODF] = imx_clk_hw_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
326*4882a593Smuzhiyun hws[IMX6SX_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
327*4882a593Smuzhiyun hws[IMX6SX_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
328*4882a593Smuzhiyun hws[IMX6SX_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
329*4882a593Smuzhiyun hws[IMX6SX_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", base + 0x24, 0, 6);
330*4882a593Smuzhiyun hws[IMX6SX_CLK_ESAI_PRED] = imx_clk_hw_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
331*4882a593Smuzhiyun hws[IMX6SX_CLK_ESAI_PODF] = imx_clk_hw_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
332*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
333*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
334*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
335*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
336*4882a593Smuzhiyun hws[IMX6SX_CLK_QSPI2_PRED] = imx_clk_hw_divider("qspi2_pred", "qspi2_sel", base + 0x2c, 18, 3);
337*4882a593Smuzhiyun hws[IMX6SX_CLK_QSPI2_PODF] = imx_clk_hw_divider("qspi2_podf", "qspi2_pred", base + 0x2c, 21, 6);
338*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
339*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
340*4882a593Smuzhiyun hws[IMX6SX_CLK_SPDIF_PRED] = imx_clk_hw_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
341*4882a593Smuzhiyun hws[IMX6SX_CLK_SPDIF_PODF] = imx_clk_hw_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
342*4882a593Smuzhiyun hws[IMX6SX_CLK_AUDIO_PRED] = imx_clk_hw_divider("audio_pred", "audio_sel", base + 0x30, 12, 3);
343*4882a593Smuzhiyun hws[IMX6SX_CLK_AUDIO_PODF] = imx_clk_hw_divider("audio_podf", "audio_pred", base + 0x30, 9, 3);
344*4882a593Smuzhiyun hws[IMX6SX_CLK_ENET_PODF] = imx_clk_hw_divider("enet_podf", "enet_pre_sel", base + 0x34, 12, 3);
345*4882a593Smuzhiyun hws[IMX6SX_CLK_M4_PODF] = imx_clk_hw_divider("m4_podf", "m4_sel", base + 0x34, 3, 3);
346*4882a593Smuzhiyun hws[IMX6SX_CLK_ECSPI_PODF] = imx_clk_hw_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
347*4882a593Smuzhiyun hws[IMX6SX_CLK_LCDIF1_PRED] = imx_clk_hw_divider("lcdif1_pred", "lcdif1_pre_sel", base + 0x38, 12, 3);
348*4882a593Smuzhiyun hws[IMX6SX_CLK_LCDIF2_PRED] = imx_clk_hw_divider("lcdif2_pred", "lcdif2_pre_sel", base + 0x38, 3, 3);
349*4882a593Smuzhiyun hws[IMX6SX_CLK_DISPLAY_PODF] = imx_clk_hw_divider("display_podf", "display_sel", base + 0x3c, 16, 3);
350*4882a593Smuzhiyun hws[IMX6SX_CLK_CSI_PODF] = imx_clk_hw_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
351*4882a593Smuzhiyun hws[IMX6SX_CLK_CKO1_PODF] = imx_clk_hw_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
352*4882a593Smuzhiyun hws[IMX6SX_CLK_CKO2_PODF] = imx_clk_hw_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun hws[IMX6SX_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
355*4882a593Smuzhiyun hws[IMX6SX_CLK_LDB_DI0_DIV_7] = imx_clk_hw_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
356*4882a593Smuzhiyun hws[IMX6SX_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
357*4882a593Smuzhiyun hws[IMX6SX_CLK_LDB_DI1_DIV_7] = imx_clk_hw_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7);
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun /* name reg shift width busy: reg, shift parent_names num_parents */
360*4882a593Smuzhiyun hws[IMX6SX_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
361*4882a593Smuzhiyun hws[IMX6SX_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
362*4882a593Smuzhiyun /* name parent_name reg shift width busy: reg, shift */
363*4882a593Smuzhiyun hws[IMX6SX_CLK_OCRAM_PODF] = imx_clk_hw_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0);
364*4882a593Smuzhiyun hws[IMX6SX_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
365*4882a593Smuzhiyun hws[IMX6SX_CLK_MMDC_PODF] = imx_clk_hw_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
366*4882a593Smuzhiyun hws[IMX6SX_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun /* name parent_name reg shift */
369*4882a593Smuzhiyun /* CCGR0 */
370*4882a593Smuzhiyun hws[IMX6SX_CLK_AIPS_TZ1] = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL);
371*4882a593Smuzhiyun hws[IMX6SX_CLK_AIPS_TZ2] = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL);
372*4882a593Smuzhiyun hws[IMX6SX_CLK_APBH_DMA] = imx_clk_hw_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
373*4882a593Smuzhiyun hws[IMX6SX_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
374*4882a593Smuzhiyun hws[IMX6SX_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
375*4882a593Smuzhiyun hws[IMX6SX_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem", "ahb", base + 0x68, 8);
376*4882a593Smuzhiyun hws[IMX6SX_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk", "ahb", base + 0x68, 10);
377*4882a593Smuzhiyun hws[IMX6SX_CLK_CAAM_IPG] = imx_clk_hw_gate2("caam_ipg", "ipg", base + 0x68, 12);
378*4882a593Smuzhiyun hws[IMX6SX_CLK_CAN1_IPG] = imx_clk_hw_gate2("can1_ipg", "ipg", base + 0x68, 14);
379*4882a593Smuzhiyun hws[IMX6SX_CLK_CAN1_SERIAL] = imx_clk_hw_gate2("can1_serial", "can_podf", base + 0x68, 16);
380*4882a593Smuzhiyun hws[IMX6SX_CLK_CAN2_IPG] = imx_clk_hw_gate2("can2_ipg", "ipg", base + 0x68, 18);
381*4882a593Smuzhiyun hws[IMX6SX_CLK_CAN2_SERIAL] = imx_clk_hw_gate2("can2_serial", "can_podf", base + 0x68, 20);
382*4882a593Smuzhiyun hws[IMX6SX_CLK_DCIC1] = imx_clk_hw_gate2("dcic1", "display_podf", base + 0x68, 24);
383*4882a593Smuzhiyun hws[IMX6SX_CLK_DCIC2] = imx_clk_hw_gate2("dcic2", "display_podf", base + 0x68, 26);
384*4882a593Smuzhiyun hws[IMX6SX_CLK_AIPS_TZ3] = imx_clk_hw_gate2_flags("aips_tz3", "ahb", base + 0x68, 30, CLK_IS_CRITICAL);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun /* CCGR1 */
387*4882a593Smuzhiyun hws[IMX6SX_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
388*4882a593Smuzhiyun hws[IMX6SX_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2);
389*4882a593Smuzhiyun hws[IMX6SX_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4);
390*4882a593Smuzhiyun hws[IMX6SX_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6);
391*4882a593Smuzhiyun hws[IMX6SX_CLK_ECSPI5] = imx_clk_hw_gate2("ecspi5", "ecspi_podf", base + 0x6c, 8);
392*4882a593Smuzhiyun hws[IMX6SX_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "perclk", base + 0x6c, 12);
393*4882a593Smuzhiyun hws[IMX6SX_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "perclk", base + 0x6c, 14);
394*4882a593Smuzhiyun hws[IMX6SX_CLK_ESAI_EXTAL] = imx_clk_hw_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
395*4882a593Smuzhiyun hws[IMX6SX_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
396*4882a593Smuzhiyun hws[IMX6SX_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
397*4882a593Smuzhiyun hws[IMX6SX_CLK_WAKEUP] = imx_clk_hw_gate2_flags("wakeup", "ipg", base + 0x6c, 18, CLK_IS_CRITICAL);
398*4882a593Smuzhiyun hws[IMX6SX_CLK_GPT_BUS] = imx_clk_hw_gate2("gpt_bus", "perclk", base + 0x6c, 20);
399*4882a593Smuzhiyun hws[IMX6SX_CLK_GPT_SERIAL] = imx_clk_hw_gate2("gpt_serial", "perclk", base + 0x6c, 22);
400*4882a593Smuzhiyun hws[IMX6SX_CLK_GPU] = imx_clk_hw_gate2("gpu", "gpu_core_podf", base + 0x6c, 26);
401*4882a593Smuzhiyun hws[IMX6SX_CLK_OCRAM_S] = imx_clk_hw_gate2("ocram_s", "ahb", base + 0x6c, 28);
402*4882a593Smuzhiyun hws[IMX6SX_CLK_CANFD] = imx_clk_hw_gate2("canfd", "can_podf", base + 0x6c, 30);
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun /* CCGR2 */
405*4882a593Smuzhiyun hws[IMX6SX_CLK_CSI] = imx_clk_hw_gate2("csi", "csi_podf", base + 0x70, 2);
406*4882a593Smuzhiyun hws[IMX6SX_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "perclk", base + 0x70, 6);
407*4882a593Smuzhiyun hws[IMX6SX_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "perclk", base + 0x70, 8);
408*4882a593Smuzhiyun hws[IMX6SX_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "perclk", base + 0x70, 10);
409*4882a593Smuzhiyun hws[IMX6SX_CLK_OCOTP] = imx_clk_hw_gate2("ocotp", "ipg", base + 0x70, 12);
410*4882a593Smuzhiyun hws[IMX6SX_CLK_IOMUXC] = imx_clk_hw_gate2("iomuxc", "lcdif1_podf", base + 0x70, 14);
411*4882a593Smuzhiyun hws[IMX6SX_CLK_IPMUX1] = imx_clk_hw_gate2_flags("ipmux1", "ahb", base + 0x70, 16, CLK_IS_CRITICAL);
412*4882a593Smuzhiyun hws[IMX6SX_CLK_IPMUX2] = imx_clk_hw_gate2_flags("ipmux2", "ahb", base + 0x70, 18, CLK_IS_CRITICAL);
413*4882a593Smuzhiyun hws[IMX6SX_CLK_IPMUX3] = imx_clk_hw_gate2_flags("ipmux3", "ahb", base + 0x70, 20, CLK_IS_CRITICAL);
414*4882a593Smuzhiyun hws[IMX6SX_CLK_TZASC1] = imx_clk_hw_gate2_flags("tzasc1", "mmdc_podf", base + 0x70, 22, CLK_IS_CRITICAL);
415*4882a593Smuzhiyun hws[IMX6SX_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif_apb", "display_podf", base + 0x70, 28);
416*4882a593Smuzhiyun hws[IMX6SX_CLK_PXP_AXI] = imx_clk_hw_gate2("pxp_axi", "display_podf", base + 0x70, 30);
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun /* CCGR3 */
419*4882a593Smuzhiyun hws[IMX6SX_CLK_M4] = imx_clk_hw_gate2("m4", "m4_podf", base + 0x74, 2);
420*4882a593Smuzhiyun hws[IMX6SX_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x74, 4);
421*4882a593Smuzhiyun hws[IMX6SX_CLK_ENET_AHB] = imx_clk_hw_gate2("enet_ahb", "enet_sel", base + 0x74, 4);
422*4882a593Smuzhiyun hws[IMX6SX_CLK_DISPLAY_AXI] = imx_clk_hw_gate2("display_axi", "display_podf", base + 0x74, 6);
423*4882a593Smuzhiyun hws[IMX6SX_CLK_LCDIF2_PIX] = imx_clk_hw_gate2("lcdif2_pix", "lcdif2_sel", base + 0x74, 8);
424*4882a593Smuzhiyun hws[IMX6SX_CLK_LCDIF1_PIX] = imx_clk_hw_gate2("lcdif1_pix", "lcdif1_sel", base + 0x74, 10);
425*4882a593Smuzhiyun hws[IMX6SX_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12);
426*4882a593Smuzhiyun hws[IMX6SX_CLK_QSPI1] = imx_clk_hw_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
427*4882a593Smuzhiyun hws[IMX6SX_CLK_MLB] = imx_clk_hw_gate2("mlb", "ahb", base + 0x74, 18);
428*4882a593Smuzhiyun hws[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_hw_gate2_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);
429*4882a593Smuzhiyun hws[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
430*4882a593Smuzhiyun hws[IMX6SX_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2_flags("mmdc_p1_ipg", "ipg", base + 0x74, 26, CLK_IS_CRITICAL);
431*4882a593Smuzhiyun hws[IMX6SX_CLK_OCRAM] = imx_clk_hw_gate2_flags("ocram", "ocram_podf", base + 0x74, 28, CLK_IS_CRITICAL);
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun /* CCGR4 */
434*4882a593Smuzhiyun hws[IMX6SX_CLK_PCIE_AXI] = imx_clk_hw_gate2("pcie_axi", "display_podf", base + 0x78, 0);
435*4882a593Smuzhiyun hws[IMX6SX_CLK_QSPI2] = imx_clk_hw_gate2("qspi2", "qspi2_podf", base + 0x78, 10);
436*4882a593Smuzhiyun hws[IMX6SX_CLK_PER1_BCH] = imx_clk_hw_gate2("per1_bch", "usdhc3", base + 0x78, 12);
437*4882a593Smuzhiyun hws[IMX6SX_CLK_PER2_MAIN] = imx_clk_hw_gate2_flags("per2_main", "ahb", base + 0x78, 14, CLK_IS_CRITICAL);
438*4882a593Smuzhiyun hws[IMX6SX_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "perclk", base + 0x78, 16);
439*4882a593Smuzhiyun hws[IMX6SX_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "perclk", base + 0x78, 18);
440*4882a593Smuzhiyun hws[IMX6SX_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "perclk", base + 0x78, 20);
441*4882a593Smuzhiyun hws[IMX6SX_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "perclk", base + 0x78, 22);
442*4882a593Smuzhiyun hws[IMX6SX_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
443*4882a593Smuzhiyun hws[IMX6SX_CLK_GPMI_BCH] = imx_clk_hw_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
444*4882a593Smuzhiyun hws[IMX6SX_CLK_GPMI_IO] = imx_clk_hw_gate2("gpmi_io", "qspi2_podf", base + 0x78, 28);
445*4882a593Smuzhiyun hws[IMX6SX_CLK_GPMI_APB] = imx_clk_hw_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun /* CCGR5 */
448*4882a593Smuzhiyun hws[IMX6SX_CLK_ROM] = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL);
449*4882a593Smuzhiyun hws[IMX6SX_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ahb", base + 0x7c, 6);
450*4882a593Smuzhiyun hws[IMX6SX_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12);
451*4882a593Smuzhiyun hws[IMX6SX_CLK_AUDIO] = imx_clk_hw_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio);
452*4882a593Smuzhiyun hws[IMX6SX_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
453*4882a593Smuzhiyun hws[IMX6SX_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio);
454*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
455*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
456*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
457*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
458*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
459*4882a593Smuzhiyun hws[IMX6SX_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
460*4882a593Smuzhiyun hws[IMX6SX_CLK_UART_IPG] = imx_clk_hw_gate2("uart_ipg", "ipg", base + 0x7c, 24);
461*4882a593Smuzhiyun hws[IMX6SX_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_podf", base + 0x7c, 26);
462*4882a593Smuzhiyun hws[IMX6SX_CLK_SAI1_IPG] = imx_clk_hw_gate2_shared("sai1_ipg", "ipg", base + 0x7c, 28, &share_count_sai1);
463*4882a593Smuzhiyun hws[IMX6SX_CLK_SAI2_IPG] = imx_clk_hw_gate2_shared("sai2_ipg", "ipg", base + 0x7c, 30, &share_count_sai2);
464*4882a593Smuzhiyun hws[IMX6SX_CLK_SAI1] = imx_clk_hw_gate2_shared("sai1", "ssi1_podf", base + 0x7c, 28, &share_count_sai1);
465*4882a593Smuzhiyun hws[IMX6SX_CLK_SAI2] = imx_clk_hw_gate2_shared("sai2", "ssi2_podf", base + 0x7c, 30, &share_count_sai2);
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun /* CCGR6 */
468*4882a593Smuzhiyun hws[IMX6SX_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0);
469*4882a593Smuzhiyun hws[IMX6SX_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
470*4882a593Smuzhiyun hws[IMX6SX_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
471*4882a593Smuzhiyun hws[IMX6SX_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
472*4882a593Smuzhiyun hws[IMX6SX_CLK_USDHC4] = imx_clk_hw_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
473*4882a593Smuzhiyun hws[IMX6SX_CLK_EIM_SLOW] = imx_clk_hw_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
474*4882a593Smuzhiyun hws[IMX6SX_CLK_PWM8] = imx_clk_hw_gate2("pwm8", "perclk", base + 0x80, 16);
475*4882a593Smuzhiyun hws[IMX6SX_CLK_VADC] = imx_clk_hw_gate2("vadc", "vid_podf", base + 0x80, 20);
476*4882a593Smuzhiyun hws[IMX6SX_CLK_GIS] = imx_clk_hw_gate2("gis", "display_podf", base + 0x80, 22);
477*4882a593Smuzhiyun hws[IMX6SX_CLK_I2C4] = imx_clk_hw_gate2("i2c4", "perclk", base + 0x80, 24);
478*4882a593Smuzhiyun hws[IMX6SX_CLK_PWM5] = imx_clk_hw_gate2("pwm5", "perclk", base + 0x80, 26);
479*4882a593Smuzhiyun hws[IMX6SX_CLK_PWM6] = imx_clk_hw_gate2("pwm6", "perclk", base + 0x80, 28);
480*4882a593Smuzhiyun hws[IMX6SX_CLK_PWM7] = imx_clk_hw_gate2("pwm7", "perclk", base + 0x80, 30);
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun hws[IMX6SX_CLK_CKO1] = imx_clk_hw_gate("cko1", "cko1_podf", base + 0x60, 7);
483*4882a593Smuzhiyun hws[IMX6SX_CLK_CKO2] = imx_clk_hw_gate("cko2", "cko2_podf", base + 0x60, 24);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun /* mask handshake of mmdc */
486*4882a593Smuzhiyun imx_mmdc_mask_handshake(base, 0);
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun imx_check_clk_hws(hws, IMX6SX_CLK_CLK_END);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
493*4882a593Smuzhiyun clk_prepare_enable(hws[IMX6SX_CLK_USBPHY1_GATE]->clk);
494*4882a593Smuzhiyun clk_prepare_enable(hws[IMX6SX_CLK_USBPHY2_GATE]->clk);
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun /* Set the default 132MHz for EIM module */
498*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk);
499*4882a593Smuzhiyun clk_set_rate(hws[IMX6SX_CLK_EIM_SLOW]->clk, 132000000);
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun /* set parent clock for LCDIF1 pixel clock */
502*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk);
503*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, hws[IMX6SX_CLK_LCDIF1_PODF]->clk);
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */
506*4882a593Smuzhiyun if (clk_set_parent(hws[IMX6SX_CLK_LVDS1_SEL]->clk, hws[IMX6SX_CLK_PCIE_REF_125M]->clk))
507*4882a593Smuzhiyun pr_err("Failed to set pcie bus parent clk.\n");
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun /*
510*4882a593Smuzhiyun * Init enet system AHB clock, set to 200MHz
511*4882a593Smuzhiyun * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
512*4882a593Smuzhiyun */
513*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_ENET_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk);
514*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_ENET_SEL]->clk, hws[IMX6SX_CLK_ENET_PODF]->clk);
515*4882a593Smuzhiyun clk_set_rate(hws[IMX6SX_CLK_ENET_PODF]->clk, 200000000);
516*4882a593Smuzhiyun clk_set_rate(hws[IMX6SX_CLK_ENET_REF]->clk, 125000000);
517*4882a593Smuzhiyun clk_set_rate(hws[IMX6SX_CLK_ENET2_REF]->clk, 125000000);
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun /* Audio clocks */
520*4882a593Smuzhiyun clk_set_rate(hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk, 393216000);
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_SPDIF_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);
523*4882a593Smuzhiyun clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 98304000);
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_AUDIO_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk);
526*4882a593Smuzhiyun clk_set_rate(hws[IMX6SX_CLK_AUDIO_PODF]->clk, 24000000);
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_SSI1_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);
529*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_SSI2_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);
530*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_SSI3_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);
531*4882a593Smuzhiyun clk_set_rate(hws[IMX6SX_CLK_SSI1_PODF]->clk, 24576000);
532*4882a593Smuzhiyun clk_set_rate(hws[IMX6SX_CLK_SSI2_PODF]->clk, 24576000);
533*4882a593Smuzhiyun clk_set_rate(hws[IMX6SX_CLK_SSI3_PODF]->clk, 24576000);
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_ESAI_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);
536*4882a593Smuzhiyun clk_set_rate(hws[IMX6SX_CLK_ESAI_PODF]->clk, 24576000);
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun /* Set parent clock for vadc */
539*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_VID_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk);
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun /* default parent of can_sel clock is invalid, manually set it here */
542*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_CAN_SEL]->clk, hws[IMX6SX_CLK_PLL3_60M]->clk);
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun /* Update gpu clock from default 528M to 720M */
545*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_GPU_CORE_SEL]->clk, hws[IMX6SX_CLK_PLL3_PFD0]->clk);
546*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_GPU_AXI_SEL]->clk, hws[IMX6SX_CLK_PLL3_PFD0]->clk);
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);
549*4882a593Smuzhiyun clk_set_parent(hws[IMX6SX_CLK_QSPI2_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun imx_register_uart_clocks(2);
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
554