1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2013-2014 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/bits.h>
7*4882a593Smuzhiyun #include <linux/clk.h>
8*4882a593Smuzhiyun #include <linux/clkdev.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/of_irq.h>
13*4882a593Smuzhiyun #include <dt-bindings/clock/imx6sl-clock.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "clk.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define CCSR 0xc
18*4882a593Smuzhiyun #define BM_CCSR_PLL1_SW_CLK_SEL BIT(2)
19*4882a593Smuzhiyun #define CACRR 0x10
20*4882a593Smuzhiyun #define CDHIPR 0x48
21*4882a593Smuzhiyun #define BM_CDHIPR_ARM_PODF_BUSY BIT(16)
22*4882a593Smuzhiyun #define ARM_WAIT_DIV_396M 2
23*4882a593Smuzhiyun #define ARM_WAIT_DIV_792M 4
24*4882a593Smuzhiyun #define ARM_WAIT_DIV_996M 6
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define PLL_ARM 0x0
27*4882a593Smuzhiyun #define BM_PLL_ARM_DIV_SELECT 0x7f
28*4882a593Smuzhiyun #define BM_PLL_ARM_POWERDOWN BIT(12)
29*4882a593Smuzhiyun #define BM_PLL_ARM_ENABLE BIT(13)
30*4882a593Smuzhiyun #define BM_PLL_ARM_LOCK BIT(31)
31*4882a593Smuzhiyun #define PLL_ARM_DIV_792M 66
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static const char *step_sels[] = { "osc", "pll2_pfd2", };
34*4882a593Smuzhiyun static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
35*4882a593Smuzhiyun static const char *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", };
36*4882a593Smuzhiyun static const char *ocram_sels[] = { "periph", "ocram_alt_sels", };
37*4882a593Smuzhiyun static const char *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
38*4882a593Smuzhiyun static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
39*4882a593Smuzhiyun static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
40*4882a593Smuzhiyun static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", };
41*4882a593Smuzhiyun static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
42*4882a593Smuzhiyun static const char *csi_sels[] = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
43*4882a593Smuzhiyun static const char *lcdif_axi_sels[] = { "pll2_bus", "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", };
44*4882a593Smuzhiyun static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
45*4882a593Smuzhiyun static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
46*4882a593Smuzhiyun static const char *perclk_sels[] = { "ipg", "osc", };
47*4882a593Smuzhiyun static const char *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", };
48*4882a593Smuzhiyun static const char *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", };
49*4882a593Smuzhiyun static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
50*4882a593Smuzhiyun static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
51*4882a593Smuzhiyun static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
52*4882a593Smuzhiyun static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
53*4882a593Smuzhiyun static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
54*4882a593Smuzhiyun static const char *ecspi_sels[] = { "pll3_60m", "osc", };
55*4882a593Smuzhiyun static const char *uart_sels[] = { "pll3_80m", "osc", };
56*4882a593Smuzhiyun static const char *lvds_sels[] = {
57*4882a593Smuzhiyun "pll1_sys", "pll2_bus", "pll2_pfd0", "pll2_pfd1", "pll2_pfd2", "dummy", "pll4_audio", "pll5_video",
58*4882a593Smuzhiyun "dummy", "enet_ref", "dummy", "dummy", "pll3_usb_otg", "pll7_usb_host", "pll3_pfd0", "pll3_pfd1",
59*4882a593Smuzhiyun "pll3_pfd2", "pll3_pfd3", "osc", "dummy", "dummy", "dummy", "dummy", "dummy",
60*4882a593Smuzhiyun "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
63*4882a593Smuzhiyun static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
64*4882a593Smuzhiyun static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
65*4882a593Smuzhiyun static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
66*4882a593Smuzhiyun static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
67*4882a593Smuzhiyun static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
68*4882a593Smuzhiyun static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
69*4882a593Smuzhiyun static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static const struct clk_div_table clk_enet_ref_table[] = {
72*4882a593Smuzhiyun { .val = 0, .div = 20, },
73*4882a593Smuzhiyun { .val = 1, .div = 10, },
74*4882a593Smuzhiyun { .val = 2, .div = 5, },
75*4882a593Smuzhiyun { .val = 3, .div = 4, },
76*4882a593Smuzhiyun { }
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static const struct clk_div_table post_div_table[] = {
80*4882a593Smuzhiyun { .val = 2, .div = 1, },
81*4882a593Smuzhiyun { .val = 1, .div = 2, },
82*4882a593Smuzhiyun { .val = 0, .div = 4, },
83*4882a593Smuzhiyun { }
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun static const struct clk_div_table video_div_table[] = {
87*4882a593Smuzhiyun { .val = 0, .div = 1, },
88*4882a593Smuzhiyun { .val = 1, .div = 2, },
89*4882a593Smuzhiyun { .val = 2, .div = 1, },
90*4882a593Smuzhiyun { .val = 3, .div = 4, },
91*4882a593Smuzhiyun { }
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static unsigned int share_count_ssi1;
95*4882a593Smuzhiyun static unsigned int share_count_ssi2;
96*4882a593Smuzhiyun static unsigned int share_count_ssi3;
97*4882a593Smuzhiyun static unsigned int share_count_spdif;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static struct clk_hw **hws;
100*4882a593Smuzhiyun static struct clk_hw_onecell_data *clk_hw_data;
101*4882a593Smuzhiyun static void __iomem *ccm_base;
102*4882a593Smuzhiyun static void __iomem *anatop_base;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /*
105*4882a593Smuzhiyun * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
106*4882a593Smuzhiyun * during WAIT mode entry process could cause cache memory
107*4882a593Smuzhiyun * corruption.
108*4882a593Smuzhiyun *
109*4882a593Smuzhiyun * Software workaround:
110*4882a593Smuzhiyun * To prevent this issue from occurring, software should ensure that the
111*4882a593Smuzhiyun * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
112*4882a593Smuzhiyun * entering WAIT mode.
113*4882a593Smuzhiyun *
114*4882a593Smuzhiyun * This function will set the ARM clk to max value within the 12:5 limit.
115*4882a593Smuzhiyun * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
116*4882a593Smuzhiyun * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since
117*4882a593Smuzhiyun * the clk APIs can NOT be called in idle thread(may cause kernel schedule
118*4882a593Smuzhiyun * as there is sleep function in PLL wait function), so here we just slow
119*4882a593Smuzhiyun * down ARM to below freq according to previous freq:
120*4882a593Smuzhiyun *
121*4882a593Smuzhiyun * run mode wait mode
122*4882a593Smuzhiyun * 396MHz -> 132MHz;
123*4882a593Smuzhiyun * 792MHz -> 158.4MHz;
124*4882a593Smuzhiyun * 996MHz -> 142.3MHz;
125*4882a593Smuzhiyun */
imx6sl_get_arm_divider_for_wait(void)126*4882a593Smuzhiyun static int imx6sl_get_arm_divider_for_wait(void)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) {
129*4882a593Smuzhiyun return ARM_WAIT_DIV_396M;
130*4882a593Smuzhiyun } else {
131*4882a593Smuzhiyun if ((readl_relaxed(anatop_base + PLL_ARM) &
132*4882a593Smuzhiyun BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M)
133*4882a593Smuzhiyun return ARM_WAIT_DIV_792M;
134*4882a593Smuzhiyun else
135*4882a593Smuzhiyun return ARM_WAIT_DIV_996M;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
imx6sl_enable_pll_arm(bool enable)139*4882a593Smuzhiyun static void imx6sl_enable_pll_arm(bool enable)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun static u32 saved_pll_arm;
142*4882a593Smuzhiyun u32 val;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun if (enable) {
145*4882a593Smuzhiyun saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM);
146*4882a593Smuzhiyun val |= BM_PLL_ARM_ENABLE;
147*4882a593Smuzhiyun val &= ~BM_PLL_ARM_POWERDOWN;
148*4882a593Smuzhiyun writel_relaxed(val, anatop_base + PLL_ARM);
149*4882a593Smuzhiyun while (!(readl_relaxed(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
150*4882a593Smuzhiyun ;
151*4882a593Smuzhiyun } else {
152*4882a593Smuzhiyun writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
imx6sl_set_wait_clk(bool enter)156*4882a593Smuzhiyun void imx6sl_set_wait_clk(bool enter)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun static unsigned long saved_arm_div;
159*4882a593Smuzhiyun int arm_div_for_wait = imx6sl_get_arm_divider_for_wait();
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun /*
162*4882a593Smuzhiyun * According to hardware design, arm podf change need
163*4882a593Smuzhiyun * PLL1 clock enabled.
164*4882a593Smuzhiyun */
165*4882a593Smuzhiyun if (arm_div_for_wait == ARM_WAIT_DIV_396M)
166*4882a593Smuzhiyun imx6sl_enable_pll_arm(true);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun if (enter) {
169*4882a593Smuzhiyun saved_arm_div = readl_relaxed(ccm_base + CACRR);
170*4882a593Smuzhiyun writel_relaxed(arm_div_for_wait, ccm_base + CACRR);
171*4882a593Smuzhiyun } else {
172*4882a593Smuzhiyun writel_relaxed(saved_arm_div, ccm_base + CACRR);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
175*4882a593Smuzhiyun ;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun if (arm_div_for_wait == ARM_WAIT_DIV_396M)
178*4882a593Smuzhiyun imx6sl_enable_pll_arm(false);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
imx6sl_clocks_init(struct device_node * ccm_node)181*4882a593Smuzhiyun static void __init imx6sl_clocks_init(struct device_node *ccm_node)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun struct device_node *np;
184*4882a593Smuzhiyun void __iomem *base;
185*4882a593Smuzhiyun int ret;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
188*4882a593Smuzhiyun IMX6SL_CLK_END), GFP_KERNEL);
189*4882a593Smuzhiyun if (WARN_ON(!clk_hw_data))
190*4882a593Smuzhiyun return;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun clk_hw_data->num = IMX6SL_CLK_END;
193*4882a593Smuzhiyun hws = clk_hw_data->hws;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun hws[IMX6SL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
196*4882a593Smuzhiyun hws[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock_hw("ckil", 0);
197*4882a593Smuzhiyun hws[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock_hw("osc", 0);
198*4882a593Smuzhiyun /* Clock source from external clock via CLK1 PAD */
199*4882a593Smuzhiyun hws[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock_hw("anaclk1", 0);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
202*4882a593Smuzhiyun base = of_iomap(np, 0);
203*4882a593Smuzhiyun WARN_ON(!base);
204*4882a593Smuzhiyun of_node_put(np);
205*4882a593Smuzhiyun anatop_base = base;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
208*4882a593Smuzhiyun hws[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
209*4882a593Smuzhiyun hws[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
210*4882a593Smuzhiyun hws[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
211*4882a593Smuzhiyun hws[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
212*4882a593Smuzhiyun hws[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
213*4882a593Smuzhiyun hws[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun /* type name parent_name base div_mask */
216*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
217*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
218*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
219*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
220*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
221*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
222*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun hws[IMX6SL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
225*4882a593Smuzhiyun hws[IMX6SL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
226*4882a593Smuzhiyun hws[IMX6SL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
227*4882a593Smuzhiyun hws[IMX6SL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
228*4882a593Smuzhiyun hws[IMX6SL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
229*4882a593Smuzhiyun hws[IMX6SL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
230*4882a593Smuzhiyun hws[IMX6SL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun /* Do not bypass PLLs initially */
233*4882a593Smuzhiyun clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk);
234*4882a593Smuzhiyun clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk);
235*4882a593Smuzhiyun clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk);
236*4882a593Smuzhiyun clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk);
237*4882a593Smuzhiyun clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk);
238*4882a593Smuzhiyun clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk);
239*4882a593Smuzhiyun clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
242*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
243*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
244*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
245*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
246*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
247*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun hws[IMX6SL_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
250*4882a593Smuzhiyun hws[IMX6SL_CLK_LVDS1_OUT] = imx_clk_hw_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
251*4882a593Smuzhiyun hws[IMX6SL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /*
254*4882a593Smuzhiyun * usbphy1 and usbphy2 are implemented as dummy gates using reserve
255*4882a593Smuzhiyun * bit 20. They are used by phy driver to keep the refcount of
256*4882a593Smuzhiyun * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be
257*4882a593Smuzhiyun * turned on during boot, and software will not need to control it
258*4882a593Smuzhiyun * anymore after that.
259*4882a593Smuzhiyun */
260*4882a593Smuzhiyun hws[IMX6SL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
261*4882a593Smuzhiyun hws[IMX6SL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
262*4882a593Smuzhiyun hws[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6);
263*4882a593Smuzhiyun hws[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun /* dev name parent_name flags reg shift width div: flags, div_table lock */
266*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
267*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
268*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
269*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
270*4882a593Smuzhiyun hws[IMX6SL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun /* name parent_name reg idx */
273*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0);
274*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1);
275*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2);
276*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0);
277*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1);
278*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2);
279*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun /* name parent_name mult div */
282*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL2_198M] = imx_clk_hw_fixed_factor("pll2_198m", "pll2_pfd2", 1, 2);
283*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL3_120M] = imx_clk_hw_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
284*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
285*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL3_60M] = imx_clk_hw_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun np = ccm_node;
288*4882a593Smuzhiyun base = of_iomap(np, 0);
289*4882a593Smuzhiyun WARN_ON(!base);
290*4882a593Smuzhiyun ccm_base = base;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun /* name reg shift width parent_names num_parents */
293*4882a593Smuzhiyun hws[IMX6SL_CLK_STEP] = imx_clk_hw_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
294*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL1_SW] = imx_clk_hw_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
295*4882a593Smuzhiyun hws[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_hw_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels));
296*4882a593Smuzhiyun hws[IMX6SL_CLK_OCRAM_SEL] = imx_clk_hw_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels));
297*4882a593Smuzhiyun hws[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_hw_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
298*4882a593Smuzhiyun hws[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_hw_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
299*4882a593Smuzhiyun hws[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
300*4882a593Smuzhiyun hws[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
301*4882a593Smuzhiyun hws[IMX6SL_CLK_CSI_SEL] = imx_clk_hw_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
302*4882a593Smuzhiyun hws[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_hw_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels));
303*4882a593Smuzhiyun hws[IMX6SL_CLK_USDHC1_SEL] = imx_clk_hw_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
304*4882a593Smuzhiyun hws[IMX6SL_CLK_USDHC2_SEL] = imx_clk_hw_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
305*4882a593Smuzhiyun hws[IMX6SL_CLK_USDHC3_SEL] = imx_clk_hw_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
306*4882a593Smuzhiyun hws[IMX6SL_CLK_USDHC4_SEL] = imx_clk_hw_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
307*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI1_SEL] = imx_clk_hw_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
308*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI2_SEL] = imx_clk_hw_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
309*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI3_SEL] = imx_clk_hw_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
310*4882a593Smuzhiyun hws[IMX6SL_CLK_PERCLK_SEL] = imx_clk_hw_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup);
311*4882a593Smuzhiyun hws[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_hw_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels));
312*4882a593Smuzhiyun hws[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_hw_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels));
313*4882a593Smuzhiyun hws[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_hw_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels));
314*4882a593Smuzhiyun hws[IMX6SL_CLK_GPU2D_SEL] = imx_clk_hw_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels));
315*4882a593Smuzhiyun hws[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_hw_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels));
316*4882a593Smuzhiyun hws[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_hw_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels));
317*4882a593Smuzhiyun hws[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_hw_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
318*4882a593Smuzhiyun hws[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_hw_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
319*4882a593Smuzhiyun hws[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_hw_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
320*4882a593Smuzhiyun hws[IMX6SL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
321*4882a593Smuzhiyun hws[IMX6SL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun /* name reg shift width busy: reg, shift parent_names num_parents */
324*4882a593Smuzhiyun hws[IMX6SL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
325*4882a593Smuzhiyun hws[IMX6SL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun /* name parent_name reg shift width */
328*4882a593Smuzhiyun hws[IMX6SL_CLK_OCRAM_PODF] = imx_clk_hw_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0);
329*4882a593Smuzhiyun hws[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_hw_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3);
330*4882a593Smuzhiyun hws[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_hw_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3);
331*4882a593Smuzhiyun hws[IMX6SL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2);
332*4882a593Smuzhiyun hws[IMX6SL_CLK_CSI_PODF] = imx_clk_hw_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
333*4882a593Smuzhiyun hws[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_hw_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3);
334*4882a593Smuzhiyun hws[IMX6SL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
335*4882a593Smuzhiyun hws[IMX6SL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
336*4882a593Smuzhiyun hws[IMX6SL_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
337*4882a593Smuzhiyun hws[IMX6SL_CLK_USDHC4_PODF] = imx_clk_hw_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
338*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
339*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
340*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
341*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
342*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
343*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
344*4882a593Smuzhiyun hws[IMX6SL_CLK_PERCLK] = imx_clk_hw_fixup_divider("perclk", "perclk_sel", base + 0x1c, 0, 6, imx_cscmr1_fixup);
345*4882a593Smuzhiyun hws[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_hw_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3);
346*4882a593Smuzhiyun hws[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_hw_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3);
347*4882a593Smuzhiyun hws[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_hw_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3);
348*4882a593Smuzhiyun hws[IMX6SL_CLK_GPU2D_PODF] = imx_clk_hw_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3);
349*4882a593Smuzhiyun hws[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_hw_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3);
350*4882a593Smuzhiyun hws[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_hw_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3);
351*4882a593Smuzhiyun hws[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_hw_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup);
352*4882a593Smuzhiyun hws[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_hw_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3);
353*4882a593Smuzhiyun hws[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_hw_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3);
354*4882a593Smuzhiyun hws[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_hw_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3);
355*4882a593Smuzhiyun hws[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_hw_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3);
356*4882a593Smuzhiyun hws[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_hw_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3);
357*4882a593Smuzhiyun hws[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_hw_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3);
358*4882a593Smuzhiyun hws[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_hw_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3);
359*4882a593Smuzhiyun hws[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6);
360*4882a593Smuzhiyun hws[IMX6SL_CLK_UART_ROOT] = imx_clk_hw_divider("uart_root", "uart_sel", base + 0x24, 0, 6);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun /* name parent_name reg shift width busy: reg, shift */
363*4882a593Smuzhiyun hws[IMX6SL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
364*4882a593Smuzhiyun hws[IMX6SL_CLK_MMDC_ROOT] = imx_clk_hw_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
365*4882a593Smuzhiyun hws[IMX6SL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /* name parent_name reg shift */
368*4882a593Smuzhiyun hws[IMX6SL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
369*4882a593Smuzhiyun hws[IMX6SL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
370*4882a593Smuzhiyun hws[IMX6SL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
371*4882a593Smuzhiyun hws[IMX6SL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
372*4882a593Smuzhiyun hws[IMX6SL_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x6c, 10);
373*4882a593Smuzhiyun hws[IMX6SL_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "perclk", base + 0x6c, 12);
374*4882a593Smuzhiyun hws[IMX6SL_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "perclk", base + 0x6c, 14);
375*4882a593Smuzhiyun hws[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_hw_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
376*4882a593Smuzhiyun hws[IMX6SL_CLK_GPT] = imx_clk_hw_gate2("gpt", "perclk", base + 0x6c, 20);
377*4882a593Smuzhiyun hws[IMX6SL_CLK_GPT_SERIAL] = imx_clk_hw_gate2("gpt_serial", "perclk", base + 0x6c, 22);
378*4882a593Smuzhiyun hws[IMX6SL_CLK_GPU2D_OVG] = imx_clk_hw_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26);
379*4882a593Smuzhiyun hws[IMX6SL_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "perclk", base + 0x70, 6);
380*4882a593Smuzhiyun hws[IMX6SL_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "perclk", base + 0x70, 8);
381*4882a593Smuzhiyun hws[IMX6SL_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "perclk", base + 0x70, 10);
382*4882a593Smuzhiyun hws[IMX6SL_CLK_OCOTP] = imx_clk_hw_gate2("ocotp", "ipg", base + 0x70, 12);
383*4882a593Smuzhiyun hws[IMX6SL_CLK_CSI] = imx_clk_hw_gate2("csi", "csi_podf", base + 0x74, 0);
384*4882a593Smuzhiyun hws[IMX6SL_CLK_PXP_AXI] = imx_clk_hw_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2);
385*4882a593Smuzhiyun hws[IMX6SL_CLK_EPDC_AXI] = imx_clk_hw_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4);
386*4882a593Smuzhiyun hws[IMX6SL_CLK_LCDIF_AXI] = imx_clk_hw_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6);
387*4882a593Smuzhiyun hws[IMX6SL_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8);
388*4882a593Smuzhiyun hws[IMX6SL_CLK_EPDC_PIX] = imx_clk_hw_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10);
389*4882a593Smuzhiyun hws[IMX6SL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
390*4882a593Smuzhiyun hws[IMX6SL_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2("mmdc_p1_ipg", "ipg", base + 0x74, 26);
391*4882a593Smuzhiyun hws[IMX6SL_CLK_OCRAM] = imx_clk_hw_gate2("ocram", "ocram_podf", base + 0x74, 28);
392*4882a593Smuzhiyun hws[IMX6SL_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "perclk", base + 0x78, 16);
393*4882a593Smuzhiyun hws[IMX6SL_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "perclk", base + 0x78, 18);
394*4882a593Smuzhiyun hws[IMX6SL_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "perclk", base + 0x78, 20);
395*4882a593Smuzhiyun hws[IMX6SL_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "perclk", base + 0x78, 22);
396*4882a593Smuzhiyun hws[IMX6SL_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ipg", base + 0x7c, 6);
397*4882a593Smuzhiyun hws[IMX6SL_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12);
398*4882a593Smuzhiyun hws[IMX6SL_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif);
399*4882a593Smuzhiyun hws[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
400*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
401*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
402*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
403*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
404*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
405*4882a593Smuzhiyun hws[IMX6SL_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
406*4882a593Smuzhiyun hws[IMX6SL_CLK_UART] = imx_clk_hw_gate2("uart", "ipg", base + 0x7c, 24);
407*4882a593Smuzhiyun hws[IMX6SL_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_root", base + 0x7c, 26);
408*4882a593Smuzhiyun hws[IMX6SL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0);
409*4882a593Smuzhiyun hws[IMX6SL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
410*4882a593Smuzhiyun hws[IMX6SL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
411*4882a593Smuzhiyun hws[IMX6SL_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
412*4882a593Smuzhiyun hws[IMX6SL_CLK_USDHC4] = imx_clk_hw_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun /* Ensure the MMDC CH0 handshake is bypassed */
415*4882a593Smuzhiyun imx_mmdc_mask_handshake(base, 0);
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun imx_check_clk_hws(hws, IMX6SL_CLK_END);
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun /* Ensure the AHB clk is at 132MHz. */
422*4882a593Smuzhiyun ret = clk_set_rate(hws[IMX6SL_CLK_AHB]->clk, 132000000);
423*4882a593Smuzhiyun if (ret)
424*4882a593Smuzhiyun pr_warn("%s: failed to set AHB clock rate %d!\n",
425*4882a593Smuzhiyun __func__, ret);
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
428*4882a593Smuzhiyun clk_prepare_enable(hws[IMX6SL_CLK_USBPHY1_GATE]->clk);
429*4882a593Smuzhiyun clk_prepare_enable(hws[IMX6SL_CLK_USBPHY2_GATE]->clk);
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun /* Audio-related clocks configuration */
433*4882a593Smuzhiyun clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk);
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun /* set PLL5 video as lcdif pix parent clock */
436*4882a593Smuzhiyun clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk,
437*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk);
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk,
440*4882a593Smuzhiyun hws[IMX6SL_CLK_PLL2_PFD2]->clk);
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun imx_register_uart_clocks(2);
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
445