Home
last modified time | relevance | path

Searched full:pll3 (Results 1 – 25 of 94) sorted by relevance

1234

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-pll3-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml#
20 const: allwinner,sun4i-a10-pll3-clk
44 compatible = "allwinner,sun4i-a10-pll3-clk";
47 clock-output-names = "pll3";
H A Dallwinner,sun4i-a10-tcon-ch0-clk.yaml64 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
73 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun4i-a10.dtsi224 pll3: clk@01c20010 { label
226 compatible = "allwinner,sun4i-a10-pll3-clk";
229 clock-output-names = "pll3";
237 clocks = <&pll3>;
238 clock-output-names = "pll3-2x";
267 compatible = "allwinner,sun4i-a10-pll3-clk";
586 clocks = <&pll3>, <&pll7>, <&pll5 1>;
595 clocks = <&pll3>, <&pll7>, <&pll5 1>;
604 clocks = <&pll3>, <&pll7>, <&pll5 1>;
613 clocks = <&pll3>, <&pll7>, <&pll5 1>;
[all …]
H A Dsun5i-gr8.dtsi124 pll3: clk@01c20010 { label
126 compatible = "allwinner,sun4i-a10-pll3-clk";
129 clock-output-names = "pll3";
133 compatible = "allwinner,sun4i-a10-pll3-2x-clk";
137 clocks = <&pll3>;
138 clock-output-names = "pll3-2x";
167 compatible = "allwinner,sun4i-a10-pll3-clk";
174 compatible = "allwinner,sun4i-a10-pll3-2x-clk";
439 clocks = <&pll3>, <&pll7>, <&pll5 1>;
448 clocks = <&pll3>, <&pll7>, <&pll5 1>;
[all …]
H A Dsun5i.dtsi124 pll3: clk@01c20010 { label
126 compatible = "allwinner,sun4i-a10-pll3-clk";
129 clock-output-names = "pll3";
133 compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
137 clocks = <&pll3>;
138 clock-output-names = "pll3-2x";
167 compatible = "allwinner,sun4i-a10-pll3-clk";
H A Dsun5i-a13.dtsi179 clocks = <&pll3>, <&pll7>, <&pll5 1>;
188 clocks = <&pll3>, <&pll7>, <&pll5 1>;
197 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
205 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
H A Dsun7i-a20.dtsi226 pll3: clk@01c20010 { label
228 compatible = "allwinner,sun4i-a10-pll3-clk";
231 clock-output-names = "pll3";
237 clocks = <&pll3>;
240 clock-output-names = "pll3-2x";
270 compatible = "allwinner,sun4i-a10-pll3-clk";
637 clocks = <&pll3>, <&pll7>, <&pll5 1>;
646 clocks = <&pll3>, <&pll7>, <&pll5 1>;
655 clocks = <&pll3>, <&pll7>, <&pll5 1>;
664 clocks = <&pll3>, <&pll7>, <&pll5 1>;
[all …]
H A Dsun5i-a10s.dtsi68 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
77 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
86 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dak4642.c113 #define PLL3 (1 << 7) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
363 pll = PLL3; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun8i_a83t.h21 u32 pll3_cfg; /* 0x10 pll3 video0 control */
97 u32 pll3_bias_cfg; /* 0x228 PLL3 video Bias config */
111 u32 pll3_pattern_cfg0; /* 0x288 PLL3 Pattern register 0 */
116 u32 pll3_pattern_cfg1; /* 0x2a8 PLL3 Pattern register 1 */
/OK3568_Linux_fs/kernel/drivers/clk/renesas/
H A Dr8a77995-cpg-mssr.c59 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
196 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
204 /* EXTAL div PLL1 mult/div PLL3 mult/div */
H A Dr8a77470-cpg-mssr.c46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
173 * MD EXTAL PLL0 PLL1 PLL3
188 /* EXTAL div PLL1 mult x2 PLL3 mult */
H A Dr8a77980-cpg-mssr.c60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
192 * MD EXTAL PLL2 PLL1 PLL3 OSC
204 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
H A Dr8a77970-cpg-mssr.c73 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
177 * MD EXTAL PLL0 PLL1 PLL3
194 /* EXTAL div PLL1 mult/div PLL3 mult/div */
H A Dr8a7745-cpg-mssr.c46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
190 * MD EXTAL PLL0 PLL1 PLL3
205 /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
H A Dr8a7743-cpg-mssr.c47 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
206 * MD EXTAL PLL0 PLL1 PLL3
225 /* EXTAL div PLL1 mult PLL3 mult */
H A Dr8a774c0-cpg-mssr.c61 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
250 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
258 /* EXTAL div PLL1 mult/div PLL3 mult/div */
H A Dr8a7742-cpg-mssr.c46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
212 * MD EXTAL PLL0 PLL1 PLL3
231 /* EXTAL div PLL1 mult PLL3 mult */
H A Dr8a77990-cpg-mssr.c61 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
257 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
265 /* EXTAL div PLL1 mult/div PLL3 mult/div */
H A Dr8a774b1-cpg-mssr.c58 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
245 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
271 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
H A Dr8a77965-cpg-mssr.c62 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
275 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
301 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
H A Dr8a774a1-cpg-mssr.c60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
249 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
275 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
H A Dr8a7796-cpg-mssr.c66 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
274 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
300 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
H A Dr8a774e1-cpg-mssr.c61 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
266 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
292 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
/OK3568_Linux_fs/kernel/drivers/clk/sirf/
H A Dclk-common.c21 * - 3 standard configurable plls: pll1, pll2 & pll3
26 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
211 .name = "pll3",
293 "pll3",
302 /* parent of io domain can only be pll3 */ in dmn_clk_get_parent()
317 /* parent of io domain can only be pll3 */ in dmn_clk_set_parent()

1234