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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Dst,stpmic1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - pascal Paillet <p.paillet@st.com>
24 "#interrupt-cells":
27 interrupt-controller: true
36 const: st,stpmic1-onkey
40 - description: onkey-falling, happens when onkey is pressed. IT_PONKEY_F of pmic
41 - description: onkey-rising, happens when onkey is released. IT_PONKEY_R of pmic
43 interrupt-names:
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/OK3568_Linux_fs/kernel/drivers/reset/
H A Dreset-ti-syscon.c2 * TI SYSCON regmap reset driver
4 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/reset/ti-syscon.h>
28 * struct ti_syscon_reset_control - reset control structure
29 * @assert_offset: reset assert control register offset from syscon base
30 * @assert_bit: reset assert bit in the reset assert control register
31 * @deassert_offset: reset deassert control register offset from syscon base
32 * @deassert_bit: reset deassert bit in the reset deassert control register
33 * @status_offset: reset status register offset from syscon base
[all …]
H A Dreset-pistachio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pistachio SoC Reset Controller driver
14 #include <linux/reset-controller.h>
18 #include <dt-bindings/reset/pistachio-resets.h>
59 return -EINVAL; in pistachio_reset_shift()
67 u32 mask; in pistachio_reset_assert() local
74 mask = BIT(shift); in pistachio_reset_assert()
76 return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET, in pistachio_reset_assert()
77 mask, mask); in pistachio_reset_assert()
84 u32 mask; in pistachio_reset_deassert() local
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H A Dreset-a10sr.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Reset driver for Altera Arria10 MAX5 System Resource Chip
7 * Adapted from reset-socfpga.c
11 #include <linux/mfd/altera-a10sr.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/reset/altr,rst-mgr-a10sr.h>
40 return -EINVAL; in a10sr_reset_shift()
49 u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); in a10sr_reset_update() local
52 return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask); in a10sr_reset_update()
73 u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); in a10sr_reset_status() local
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/OK3568_Linux_fs/u-boot/drivers/phy/marvell/
H A Dcomphy_cp110.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
32 * For CP-110 we have 2 Selector registers "PHY Selectors",
72 u32 mask, unsigned long usec_timout) in polling_with_timeout() argument
78 data = readl(addr) & mask; in polling_with_timeout()
79 } while (data != val && --usec_timout > 0); in polling_with_timeout()
91 u32 mask, data, ret = 1; in comphy_pcie_power_up() local
101 * Add SAR (Sample-At-Reset) configuration for the PCIe clock in comphy_pcie_power_up()
103 * U-Boot to mainline version. in comphy_pcie_power_up()
105 * SerDes Lane 4/5 got the PCIe ref-clock #1, in comphy_pcie_power_up()
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dwdt.h4 * SPDX-License-Identifier: GPL-2.0+
27 /* Values for Reset Mode */
33 /* Reset Mask register */
70 /* On pre-ast2500 SoCs this register is reserved. */
76 * gets Reset Mode value from it.
79 * @return Reset Mode value
85 * gets Reset Mask value from it. Reset Mask is only supported on ast2500
88 * @return Reset Mask value
93 * Given Reset Mask and Reset Mode values, converts them to flags,
96 * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they
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/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Dprminst44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "prcm-common.h"
23 #include "prm-regbits-44xx.h"
34 * omap_prm_base_init - Populates the prm partitions
75 /* Read-modify-write a register in PRM. Caller must lock */
76 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, in omap4_prminst_rmw_inst_reg_bits() argument
82 v &= ~mask; in omap4_prminst_rmw_inst_reg_bits()
90 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
93 * @shift: register bit shift corresponding to the reset line to check
97 * -EINVAL upon parameter error.
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H A Dprm2xxx_3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Texas Instruments, Inc.
18 #include "prm-regbits-24xx.h"
22 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
24 * @shift: register bit shift corresponding to the reset line to check
31 * -EINVAL if called while running on a non-OMAP2/3 chip.
40 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
41 * @shift: register bit shift corresponding to the reset line to assert
47 * reset line to be asserted / deasserted in order to fully enable the
48 * IP. These modules may have multiple hard-reset lines that reset
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H A Dprm33xx.c4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
24 #include "prm-regbits-33xx.h"
42 /* Read-modify-write a register in PRM. Caller must lock */
43 static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) in am33xx_prm_rmw_reg_bits() argument
48 v &= ~mask; in am33xx_prm_rmw_reg_bits()
56 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
58 * @shift: register bit shift corresponding to the reset line to check
65 * -EINVAL upon parameter error.
80 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
81 * @shift: register bit shift corresponding to the reset line to assert
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/OK3568_Linux_fs/kernel/drivers/media/pci/cx18/
H A Dcx18-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Derived from ivtv-gpio.c
11 #include "cx18-driver.h"
12 #include "cx18-io.h"
13 #include "cx18-cards.h"
14 #include "cx18-gpio.h"
15 #include "tuner-xc2028.h"
27 * HVR-1600 GPIO pins, courtesy of Hauppauge:
29 * gpio0: zilog ir process reset pin
31 * gpio12: cx24227 reset pin
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/reset/
H A Dsyscon-reboot.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/reset/syscon-reboot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic SYSCON mapped register reset driver
10 - Sebastian Reichel <sre@kernel.org>
13 This is a generic reset driver using syscon to map the reset register.
14 The reset is generally performed with a write to the reset register
16 mask defined in the reboot node. Default will be little endian mode, 32 bit
18 parental dt-node. So the SYSCON reboot node should be represented as a
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/OK3568_Linux_fs/kernel/drivers/input/misc/
H A Dpmic8xxx-pwrkey.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
33 /* Regulator control registers for shutdown/reset */
53 /* Buck TEST2 registers for shutdown/reset */
72 * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
108 enable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_suspend()
118 disable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_resume()
130 u8 mask, val; in pmic8xxx_pwrkey_shutdown() local
131 bool reset = system_state == SYSTEM_RESTART; in pmic8xxx_pwrkey_shutdown() local
133 if (pwrkey->shutdown_fn) { in pmic8xxx_pwrkey_shutdown()
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/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Dkona_sdhci.c4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/kona-common/clk.h>
25 unsigned int mask; in init_kona_mmc_core() local
29 printf("%s: sd host controller reset error\n", __func__); in init_kona_mmc_core()
30 return -EBUSY; in init_kona_mmc_core()
33 /* For kona a hardware reset before anything else. */ in init_kona_mmc_core()
34 mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET; in init_kona_mmc_core()
35 sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
41 printf("%s: reset timeout error\n", __func__); in init_kona_mmc_core()
42 return -ETIMEDOUT; in init_kona_mmc_core()
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/OK3568_Linux_fs/kernel/include/linux/input/
H A Dadp5589.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright 2010-2011 Analog Devices Inc.
47 #define ADP5589_GPIMAPSIZE_MAX (ADP5589_GPI_PIN_END - ADP5589_GPI_PIN_BASE + 1)
76 #define ADP5585_GPIMAPSIZE_MAX (ADP5585_GPI_PIN_END - ADP5585_GPI_PIN_BASE + 1)
110 /* ADP5589 Mask Bits:
114 * ---------------- BIT ------------------
127 /* ADP5585 Mask Bits:
131 * ---- BIT -- -----------
149 unsigned keypad_en_mask; /* Keypad (Rows/Columns) enable mask */
158 unsigned char reset_cfg; /* Reset config */
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/OK3568_Linux_fs/kernel/drivers/staging/octeon-usb/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
140 * @glblintrmsk: Global Interrupt Mask (GlblIntrMsk)
142 * The application uses this bit to mask or unmask the interrupt
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/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/reset-controller.h>
12 #include "reset.h"
16 rcdev->ops->assert(rcdev, id); in qcom_reset()
18 rcdev->ops->deassert(rcdev, id); in qcom_reset()
27 u32 mask; in qcom_reset_assert() local
30 map = &rst->reset_map[id]; in qcom_reset_assert()
31 mask = BIT(map->bit); in qcom_reset_assert()
33 return regmap_update_bits(rst->regmap, map->reg, mask, mask); in qcom_reset_assert()
41 u32 mask; in qcom_reset_deassert() local
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/OK3568_Linux_fs/kernel/arch/mips/include/asm/sn/sn0/
H A Dhubni.h8 * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
28 #define NI_PORT_RESET 0x600008 /* Reset the network interface */
70 * NI_STATUS_REV_ID mask and shift definitions
79 #define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */
102 /* NI_PORT_RESET mask definitions */
104 #define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */
105 #define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */
106 #define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */
108 /* NI_PROTECTION mask and shift definitions */
112 /* NI_GLOBAL_PARMS mask and shift definitions */
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/OK3568_Linux_fs/kernel/drivers/mfd/
H A Ducb1x00-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mfd/ucb1x00-core.c
11 * to be used on other non-MCP-enabled hardware platforms.
35 * ucb1x00_io_set_dir - set IO direction
54 spin_lock_irqsave(&ucb->io_lock, flags); in ucb1x00_io_set_dir()
55 ucb->io_dir |= out; in ucb1x00_io_set_dir()
56 ucb->io_dir &= ~in; in ucb1x00_io_set_dir()
58 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); in ucb1x00_io_set_dir()
59 spin_unlock_irqrestore(&ucb->io_lock, flags); in ucb1x00_io_set_dir()
63 * ucb1x00_io_write - set or clear IO outputs
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H A Drk808.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2018, Fuzhou Rockchip Electronics Co., Ltd
7 * Author: Chris Zhong <zyw@rock-chips.com>
8 * Author: Zhang Qing <zhangqing@rock-chips.com>
29 int mask; member
37 * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but in rk808_is_volatile_reg()
39 * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since in rk808_is_volatile_reg()
65 * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but in rk817_is_volatile_reg()
90 * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but in rk818_is_volatile_reg()
92 * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since in rk818_is_volatile_reg()
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/cavium/liquidio/
H A Dcn66xx_device.c7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
33 dev_dbg(&oct->pci_dev->dev, "BIST enabled for soft reset\n"); in lio_cn6xxx_soft_reset()
45 dev_err(&oct->pci_dev->dev, "Soft reset failed\n"); in lio_cn6xxx_soft_reset()
49 dev_dbg(&oct->pci_dev->dev, "Reset completed\n"); in lio_cn6xxx_soft_reset()
59 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_enable_error_reporting()
61 dev_err(&oct->pci_dev->dev, "PCI-E Link error detected: 0x%08x\n", in lio_cn6xxx_enable_error_reporting()
67 dev_dbg(&oct->pci_dev->dev, "Enabling PCI-E error reporting..\n"); in lio_cn6xxx_enable_error_reporting()
68 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); in lio_cn6xxx_enable_error_reporting()
78 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_setup_pcie_mps()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dintel_reset.c2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008-2018 Intel Corporation
44 struct intel_engine_cs *engine = rq->engine; in engine_skip_context()
45 struct intel_context *hung_ctx = rq->context; in engine_skip_context()
50 lockdep_assert_held(&engine->active.lock); in engine_skip_context()
51 list_for_each_entry_continue(rq, &engine->active.requests, sched.link) in engine_skip_context()
52 if (rq->context == hung_ctx) { in engine_skip_context()
53 i915_request_set_error_once(rq, -EIO); in engine_skip_context()
60 struct drm_i915_file_private *file_priv = ctx->file_priv; in client_mark_guilty()
71 prev_hang = xchg(&file_priv->hang_timestamp, jiffies); in client_mark_guilty()
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H A Dselftest_reset.c1 // SPDX-License-Identifier: MIT
18 intel_engine_mask_t mask, in __igt_reset_stolen() argument
21 struct i915_ggtt *ggtt = &gt->i915->ggtt; in __igt_reset_stolen()
22 const struct resource *dsm = &gt->i915->dsm; in __igt_reset_stolen()
33 if (!drm_mm_node_allocated(&ggtt->error_capture)) in __igt_reset_stolen()
42 return -ENOMEM; in __igt_reset_stolen()
46 err = -ENOMEM; in __igt_reset_stolen()
51 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in __igt_reset_stolen()
61 if (!(mask & engine->mask)) in __igt_reset_stolen()
82 dma_addr_t dma = (dma_addr_t)dsm->start + (page << PAGE_SHIFT); in __igt_reset_stolen()
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/OK3568_Linux_fs/u-boot/arch/x86/cpu/quark/
H A Dquark.c4 * SPDX-License-Identifier: GPL-2.0+
21 u32 base, mask; in quark_setup_mtrr() local
46 mask = ~(CONFIG_SYS_MONITOR_LEN - 1); in quark_setup_mtrr()
47 base = CONFIG_SYS_TEXT_BASE & mask; in quark_setup_mtrr()
51 mask | MTRR_PHYS_MASK_VALID); in quark_setup_mtrr()
54 mask = ~(ESRAM_SIZE - 1); in quark_setup_mtrr()
55 base = CONFIG_ESRAM_BASE & mask; in quark_setup_mtrr()
59 mask | MTRR_PHYS_MASK_VALID); in quark_setup_mtrr()
70 /* GPIO - D31:F0:R44h */ in quark_setup_bars()
74 /* ACPI PM1 Block - D31:F0:R48h */ in quark_setup_bars()
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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/include/
H A Dspid.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 1999-2017, Broadcom Corporation
26 * <<Broadcom-WL-IPTag/Open:>>
28 * $Id: spid.h 514727 2014-11-12 03:02:48Z $
42 uint8 status_enable; /* 0x02, status-enable, intr with status, response_delay
45 uint8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */
47 uint16 intr_en_reg; /* 0x06, Intr mask register */
65 #define SPID_INTR_REG 0x04 /* 16 bits - Interrupt status */
66 #define SPID_INTR_EN_REG 0x06 /* 16 bits - Interrupt mask */
85 #define WAKE_UP 0x80 /* 0/1 Wake-up command from Host to WLAN */
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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/include/
H A Dspid.h21 * <<Broadcom-WL-IPTag/Dual:>>
35 uint8 status_enable; /* 0x02, status-enable, intr with status, response_delay
38 uint8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */
40 uint16 intr_en_reg; /* 0x06, Intr mask register */
58 #define SPID_INTR_REG 0x04 /* 16 bits - Interrupt status */
59 #define SPID_INTR_EN_REG 0x06 /* 16 bits - Interrupt mask */
78 #define WAKE_UP 0x80 /* 0/1 Wake-up command from Host to WLAN */
80 /* Bit mask for SPID_RESPONSE_DELAY device register */
83 /* Bit mask for SPID_STATUS_ENABLE device register */
85 #define INTR_WITH_STATUS 0x2 /* 0/1 Do-not / do-interrupt if status is sent */
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