1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Analog Devices ADP5589/ADP5585 I/O Expander and QWERTY Keypad Controller 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2010-2011 Analog Devices Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ADP5589_H 9*4882a593Smuzhiyun #define _ADP5589_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * ADP5589 specific GPI and Keymap defines 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define ADP5589_KEYMAPSIZE 88 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define ADP5589_GPI_PIN_ROW0 97 18*4882a593Smuzhiyun #define ADP5589_GPI_PIN_ROW1 98 19*4882a593Smuzhiyun #define ADP5589_GPI_PIN_ROW2 99 20*4882a593Smuzhiyun #define ADP5589_GPI_PIN_ROW3 100 21*4882a593Smuzhiyun #define ADP5589_GPI_PIN_ROW4 101 22*4882a593Smuzhiyun #define ADP5589_GPI_PIN_ROW5 102 23*4882a593Smuzhiyun #define ADP5589_GPI_PIN_ROW6 103 24*4882a593Smuzhiyun #define ADP5589_GPI_PIN_ROW7 104 25*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL0 105 26*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL1 106 27*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL2 107 28*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL3 108 29*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL4 109 30*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL5 110 31*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL6 111 32*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL7 112 33*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL8 113 34*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL9 114 35*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL10 115 36*4882a593Smuzhiyun #define GPI_LOGIC1 116 37*4882a593Smuzhiyun #define GPI_LOGIC2 117 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define ADP5589_GPI_PIN_ROW_BASE ADP5589_GPI_PIN_ROW0 40*4882a593Smuzhiyun #define ADP5589_GPI_PIN_ROW_END ADP5589_GPI_PIN_ROW7 41*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL_BASE ADP5589_GPI_PIN_COL0 42*4882a593Smuzhiyun #define ADP5589_GPI_PIN_COL_END ADP5589_GPI_PIN_COL10 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define ADP5589_GPI_PIN_BASE ADP5589_GPI_PIN_ROW_BASE 45*4882a593Smuzhiyun #define ADP5589_GPI_PIN_END ADP5589_GPI_PIN_COL_END 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define ADP5589_GPIMAPSIZE_MAX (ADP5589_GPI_PIN_END - ADP5589_GPI_PIN_BASE + 1) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * ADP5585 specific GPI and Keymap defines 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define ADP5585_KEYMAPSIZE 30 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define ADP5585_GPI_PIN_ROW0 37 56*4882a593Smuzhiyun #define ADP5585_GPI_PIN_ROW1 38 57*4882a593Smuzhiyun #define ADP5585_GPI_PIN_ROW2 39 58*4882a593Smuzhiyun #define ADP5585_GPI_PIN_ROW3 40 59*4882a593Smuzhiyun #define ADP5585_GPI_PIN_ROW4 41 60*4882a593Smuzhiyun #define ADP5585_GPI_PIN_ROW5 42 61*4882a593Smuzhiyun #define ADP5585_GPI_PIN_COL0 43 62*4882a593Smuzhiyun #define ADP5585_GPI_PIN_COL1 44 63*4882a593Smuzhiyun #define ADP5585_GPI_PIN_COL2 45 64*4882a593Smuzhiyun #define ADP5585_GPI_PIN_COL3 46 65*4882a593Smuzhiyun #define ADP5585_GPI_PIN_COL4 47 66*4882a593Smuzhiyun #define GPI_LOGIC 48 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define ADP5585_GPI_PIN_ROW_BASE ADP5585_GPI_PIN_ROW0 69*4882a593Smuzhiyun #define ADP5585_GPI_PIN_ROW_END ADP5585_GPI_PIN_ROW5 70*4882a593Smuzhiyun #define ADP5585_GPI_PIN_COL_BASE ADP5585_GPI_PIN_COL0 71*4882a593Smuzhiyun #define ADP5585_GPI_PIN_COL_END ADP5585_GPI_PIN_COL4 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define ADP5585_GPI_PIN_BASE ADP5585_GPI_PIN_ROW_BASE 74*4882a593Smuzhiyun #define ADP5585_GPI_PIN_END ADP5585_GPI_PIN_COL_END 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define ADP5585_GPIMAPSIZE_MAX (ADP5585_GPI_PIN_END - ADP5585_GPI_PIN_BASE + 1) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct adp5589_gpi_map { 79*4882a593Smuzhiyun unsigned short pin; 80*4882a593Smuzhiyun unsigned short sw_evt; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* scan_cycle_time */ 84*4882a593Smuzhiyun #define ADP5589_SCAN_CYCLE_10ms 0 85*4882a593Smuzhiyun #define ADP5589_SCAN_CYCLE_20ms 1 86*4882a593Smuzhiyun #define ADP5589_SCAN_CYCLE_30ms 2 87*4882a593Smuzhiyun #define ADP5589_SCAN_CYCLE_40ms 3 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* RESET_CFG */ 90*4882a593Smuzhiyun #define RESET_PULSE_WIDTH_500us 0 91*4882a593Smuzhiyun #define RESET_PULSE_WIDTH_1ms 1 92*4882a593Smuzhiyun #define RESET_PULSE_WIDTH_2ms 2 93*4882a593Smuzhiyun #define RESET_PULSE_WIDTH_10ms 3 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define RESET_TRIG_TIME_0ms (0 << 2) 96*4882a593Smuzhiyun #define RESET_TRIG_TIME_1000ms (1 << 2) 97*4882a593Smuzhiyun #define RESET_TRIG_TIME_1500ms (2 << 2) 98*4882a593Smuzhiyun #define RESET_TRIG_TIME_2000ms (3 << 2) 99*4882a593Smuzhiyun #define RESET_TRIG_TIME_2500ms (4 << 2) 100*4882a593Smuzhiyun #define RESET_TRIG_TIME_3000ms (5 << 2) 101*4882a593Smuzhiyun #define RESET_TRIG_TIME_3500ms (6 << 2) 102*4882a593Smuzhiyun #define RESET_TRIG_TIME_4000ms (7 << 2) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define RESET_PASSTHRU_EN (1 << 5) 105*4882a593Smuzhiyun #define RESET1_POL_HIGH (1 << 6) 106*4882a593Smuzhiyun #define RESET1_POL_LOW (0 << 6) 107*4882a593Smuzhiyun #define RESET2_POL_HIGH (1 << 7) 108*4882a593Smuzhiyun #define RESET2_POL_LOW (0 << 7) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* ADP5589 Mask Bits: 111*4882a593Smuzhiyun * C C C C C C C C C C C | R R R R R R R R 112*4882a593Smuzhiyun * 1 9 8 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0 113*4882a593Smuzhiyun * 0 114*4882a593Smuzhiyun * ---------------- BIT ------------------ 115*4882a593Smuzhiyun * 1 1 1 1 1 1 1 1 1 0 0 | 0 0 0 0 0 0 0 0 116*4882a593Smuzhiyun * 8 7 6 5 4 3 2 1 0 9 8 | 7 6 5 4 3 2 1 0 117*4882a593Smuzhiyun */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define ADP_ROW(x) (1 << (x)) 120*4882a593Smuzhiyun #define ADP_COL(x) (1 << (x + 8)) 121*4882a593Smuzhiyun #define ADP5589_ROW_MASK 0xFF 122*4882a593Smuzhiyun #define ADP5589_COL_MASK 0xFF 123*4882a593Smuzhiyun #define ADP5589_COL_SHIFT 8 124*4882a593Smuzhiyun #define ADP5589_MAX_ROW_NUM 7 125*4882a593Smuzhiyun #define ADP5589_MAX_COL_NUM 10 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* ADP5585 Mask Bits: 128*4882a593Smuzhiyun * C C C C C | R R R R R R 129*4882a593Smuzhiyun * 4 3 2 1 0 | 5 4 3 2 1 0 130*4882a593Smuzhiyun * 131*4882a593Smuzhiyun * ---- BIT -- ----------- 132*4882a593Smuzhiyun * 1 0 0 0 0 | 0 0 0 0 0 0 133*4882a593Smuzhiyun * 0 9 8 7 6 | 5 4 3 2 1 0 134*4882a593Smuzhiyun */ 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define ADP5585_ROW_MASK 0x3F 137*4882a593Smuzhiyun #define ADP5585_COL_MASK 0x1F 138*4882a593Smuzhiyun #define ADP5585_ROW_SHIFT 0 139*4882a593Smuzhiyun #define ADP5585_COL_SHIFT 6 140*4882a593Smuzhiyun #define ADP5585_MAX_ROW_NUM 5 141*4882a593Smuzhiyun #define ADP5585_MAX_COL_NUM 4 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define ADP5585_ROW(x) (1 << ((x) & ADP5585_ROW_MASK)) 144*4882a593Smuzhiyun #define ADP5585_COL(x) (1 << (((x) & ADP5585_COL_MASK) + ADP5585_COL_SHIFT)) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* Put one of these structures in i2c_board_info platform_data */ 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun struct adp5589_kpad_platform_data { 149*4882a593Smuzhiyun unsigned keypad_en_mask; /* Keypad (Rows/Columns) enable mask */ 150*4882a593Smuzhiyun const unsigned short *keymap; /* Pointer to keymap */ 151*4882a593Smuzhiyun unsigned short keymapsize; /* Keymap size */ 152*4882a593Smuzhiyun bool repeat; /* Enable key repeat */ 153*4882a593Smuzhiyun bool en_keylock; /* Enable key lock feature (ADP5589 only)*/ 154*4882a593Smuzhiyun unsigned char unlock_key1; /* Unlock Key 1 (ADP5589 only) */ 155*4882a593Smuzhiyun unsigned char unlock_key2; /* Unlock Key 2 (ADP5589 only) */ 156*4882a593Smuzhiyun unsigned char unlock_timer; /* Time in seconds [0..7] between the two unlock keys 0=disable (ADP5589 only) */ 157*4882a593Smuzhiyun unsigned char scan_cycle_time; /* Time between consecutive scan cycles */ 158*4882a593Smuzhiyun unsigned char reset_cfg; /* Reset config */ 159*4882a593Smuzhiyun unsigned short reset1_key_1; /* Reset Key 1 */ 160*4882a593Smuzhiyun unsigned short reset1_key_2; /* Reset Key 2 */ 161*4882a593Smuzhiyun unsigned short reset1_key_3; /* Reset Key 3 */ 162*4882a593Smuzhiyun unsigned short reset2_key_1; /* Reset Key 1 */ 163*4882a593Smuzhiyun unsigned short reset2_key_2; /* Reset Key 2 */ 164*4882a593Smuzhiyun unsigned debounce_dis_mask; /* Disable debounce mask */ 165*4882a593Smuzhiyun unsigned pull_dis_mask; /* Disable all pull resistors mask */ 166*4882a593Smuzhiyun unsigned pullup_en_100k; /* Pull-Up 100k Enable Mask */ 167*4882a593Smuzhiyun unsigned pullup_en_300k; /* Pull-Up 300k Enable Mask */ 168*4882a593Smuzhiyun unsigned pulldown_en_300k; /* Pull-Down 300k Enable Mask */ 169*4882a593Smuzhiyun const struct adp5589_gpi_map *gpimap; 170*4882a593Smuzhiyun unsigned short gpimapsize; 171*4882a593Smuzhiyun const struct adp5589_gpio_platform_data *gpio_data; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun struct i2c_client; /* forward declaration */ 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun struct adp5589_gpio_platform_data { 177*4882a593Smuzhiyun int gpio_start; /* GPIO Chip base # */ 178*4882a593Smuzhiyun int (*setup)(struct i2c_client *client, 179*4882a593Smuzhiyun int gpio, unsigned ngpio, 180*4882a593Smuzhiyun void *context); 181*4882a593Smuzhiyun int (*teardown)(struct i2c_client *client, 182*4882a593Smuzhiyun int gpio, unsigned ngpio, 183*4882a593Smuzhiyun void *context); 184*4882a593Smuzhiyun void *context; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #endif 188