1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3*4882a593Smuzhiyun */
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/module.h>
6*4882a593Smuzhiyun #include <linux/kernel.h>
7*4882a593Smuzhiyun #include <linux/errno.h>
8*4882a593Smuzhiyun #include <linux/slab.h>
9*4882a593Smuzhiyun #include <linux/input.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/log2.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define PON_CNTL_1 0x1C
18*4882a593Smuzhiyun #define PON_CNTL_PULL_UP BIT(7)
19*4882a593Smuzhiyun #define PON_CNTL_TRIG_DELAY_MASK (0x7)
20*4882a593Smuzhiyun #define PON_CNTL_1_PULL_UP_EN 0xe0
21*4882a593Smuzhiyun #define PON_CNTL_1_USB_PWR_EN 0x10
22*4882a593Smuzhiyun #define PON_CNTL_1_WD_EN_RESET 0x08
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define PM8058_SLEEP_CTRL 0x02b
25*4882a593Smuzhiyun #define PM8921_SLEEP_CTRL 0x10a
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define SLEEP_CTRL_SMPL_EN_RESET 0x04
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* Regulator master enable addresses */
30*4882a593Smuzhiyun #define REG_PM8058_VREG_EN_MSM 0x018
31*4882a593Smuzhiyun #define REG_PM8058_VREG_EN_GRP_5_4 0x1c8
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Regulator control registers for shutdown/reset */
34*4882a593Smuzhiyun #define PM8058_S0_CTRL 0x004
35*4882a593Smuzhiyun #define PM8058_S1_CTRL 0x005
36*4882a593Smuzhiyun #define PM8058_S3_CTRL 0x111
37*4882a593Smuzhiyun #define PM8058_L21_CTRL 0x120
38*4882a593Smuzhiyun #define PM8058_L22_CTRL 0x121
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define PM8058_REGULATOR_ENABLE_MASK 0x80
41*4882a593Smuzhiyun #define PM8058_REGULATOR_ENABLE 0x80
42*4882a593Smuzhiyun #define PM8058_REGULATOR_DISABLE 0x00
43*4882a593Smuzhiyun #define PM8058_REGULATOR_PULL_DOWN_MASK 0x40
44*4882a593Smuzhiyun #define PM8058_REGULATOR_PULL_DOWN_EN 0x40
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Buck CTRL register */
47*4882a593Smuzhiyun #define PM8058_SMPS_LEGACY_VREF_SEL 0x20
48*4882a593Smuzhiyun #define PM8058_SMPS_LEGACY_VPROG_MASK 0x1f
49*4882a593Smuzhiyun #define PM8058_SMPS_ADVANCED_BAND_MASK 0xC0
50*4882a593Smuzhiyun #define PM8058_SMPS_ADVANCED_BAND_SHIFT 6
51*4882a593Smuzhiyun #define PM8058_SMPS_ADVANCED_VPROG_MASK 0x3f
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Buck TEST2 registers for shutdown/reset */
54*4882a593Smuzhiyun #define PM8058_S0_TEST2 0x084
55*4882a593Smuzhiyun #define PM8058_S1_TEST2 0x085
56*4882a593Smuzhiyun #define PM8058_S3_TEST2 0x11a
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define PM8058_REGULATOR_BANK_WRITE 0x80
59*4882a593Smuzhiyun #define PM8058_REGULATOR_BANK_MASK 0x70
60*4882a593Smuzhiyun #define PM8058_REGULATOR_BANK_SHIFT 4
61*4882a593Smuzhiyun #define PM8058_REGULATOR_BANK_SEL(n) ((n) << PM8058_REGULATOR_BANK_SHIFT)
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Buck TEST2 register bank 1 */
64*4882a593Smuzhiyun #define PM8058_SMPS_LEGACY_VLOW_SEL 0x01
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Buck TEST2 register bank 7 */
67*4882a593Smuzhiyun #define PM8058_SMPS_ADVANCED_MODE_MASK 0x02
68*4882a593Smuzhiyun #define PM8058_SMPS_ADVANCED_MODE 0x02
69*4882a593Smuzhiyun #define PM8058_SMPS_LEGACY_MODE 0x00
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /**
72*4882a593Smuzhiyun * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
73*4882a593Smuzhiyun * @key_press_irq: key press irq number
74*4882a593Smuzhiyun * @regmap: device regmap
75*4882a593Smuzhiyun * @shutdown_fn: shutdown configuration function
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun struct pmic8xxx_pwrkey {
78*4882a593Smuzhiyun int key_press_irq;
79*4882a593Smuzhiyun struct regmap *regmap;
80*4882a593Smuzhiyun int (*shutdown_fn)(struct pmic8xxx_pwrkey *, bool);
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
pwrkey_press_irq(int irq,void * _pwr)83*4882a593Smuzhiyun static irqreturn_t pwrkey_press_irq(int irq, void *_pwr)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun struct input_dev *pwr = _pwr;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun input_report_key(pwr, KEY_POWER, 1);
88*4882a593Smuzhiyun input_sync(pwr);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun return IRQ_HANDLED;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
pwrkey_release_irq(int irq,void * _pwr)93*4882a593Smuzhiyun static irqreturn_t pwrkey_release_irq(int irq, void *_pwr)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun struct input_dev *pwr = _pwr;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun input_report_key(pwr, KEY_POWER, 0);
98*4882a593Smuzhiyun input_sync(pwr);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return IRQ_HANDLED;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
pmic8xxx_pwrkey_suspend(struct device * dev)103*4882a593Smuzhiyun static int __maybe_unused pmic8xxx_pwrkey_suspend(struct device *dev)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun struct pmic8xxx_pwrkey *pwrkey = dev_get_drvdata(dev);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun if (device_may_wakeup(dev))
108*4882a593Smuzhiyun enable_irq_wake(pwrkey->key_press_irq);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun return 0;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
pmic8xxx_pwrkey_resume(struct device * dev)113*4882a593Smuzhiyun static int __maybe_unused pmic8xxx_pwrkey_resume(struct device *dev)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct pmic8xxx_pwrkey *pwrkey = dev_get_drvdata(dev);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun if (device_may_wakeup(dev))
118*4882a593Smuzhiyun disable_irq_wake(pwrkey->key_press_irq);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun return 0;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(pm8xxx_pwr_key_pm_ops,
124*4882a593Smuzhiyun pmic8xxx_pwrkey_suspend, pmic8xxx_pwrkey_resume);
125*4882a593Smuzhiyun
pmic8xxx_pwrkey_shutdown(struct platform_device * pdev)126*4882a593Smuzhiyun static void pmic8xxx_pwrkey_shutdown(struct platform_device *pdev)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun struct pmic8xxx_pwrkey *pwrkey = platform_get_drvdata(pdev);
129*4882a593Smuzhiyun int error;
130*4882a593Smuzhiyun u8 mask, val;
131*4882a593Smuzhiyun bool reset = system_state == SYSTEM_RESTART;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun if (pwrkey->shutdown_fn) {
134*4882a593Smuzhiyun error = pwrkey->shutdown_fn(pwrkey, reset);
135*4882a593Smuzhiyun if (error)
136*4882a593Smuzhiyun return;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /*
140*4882a593Smuzhiyun * Select action to perform (reset or shutdown) when PS_HOLD goes low.
141*4882a593Smuzhiyun * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that
142*4882a593Smuzhiyun * USB charging is enabled.
143*4882a593Smuzhiyun */
144*4882a593Smuzhiyun mask = PON_CNTL_1_PULL_UP_EN | PON_CNTL_1_USB_PWR_EN;
145*4882a593Smuzhiyun mask |= PON_CNTL_1_WD_EN_RESET;
146*4882a593Smuzhiyun val = mask;
147*4882a593Smuzhiyun if (!reset)
148*4882a593Smuzhiyun val &= ~PON_CNTL_1_WD_EN_RESET;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun regmap_update_bits(pwrkey->regmap, PON_CNTL_1, mask, val);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /*
154*4882a593Smuzhiyun * Set an SMPS regulator to be disabled in its CTRL register, but enabled
155*4882a593Smuzhiyun * in the master enable register. Also set it's pull down enable bit.
156*4882a593Smuzhiyun * Take care to make sure that the output voltage doesn't change if switching
157*4882a593Smuzhiyun * from advanced mode to legacy mode.
158*4882a593Smuzhiyun */
pm8058_disable_smps_locally_set_pull_down(struct regmap * regmap,u16 ctrl_addr,u16 test2_addr,u16 master_enable_addr,u8 master_enable_bit)159*4882a593Smuzhiyun static int pm8058_disable_smps_locally_set_pull_down(struct regmap *regmap,
160*4882a593Smuzhiyun u16 ctrl_addr, u16 test2_addr, u16 master_enable_addr,
161*4882a593Smuzhiyun u8 master_enable_bit)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun int error;
164*4882a593Smuzhiyun u8 vref_sel, vlow_sel, band, vprog, bank;
165*4882a593Smuzhiyun unsigned int reg;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun bank = PM8058_REGULATOR_BANK_SEL(7);
168*4882a593Smuzhiyun error = regmap_write(regmap, test2_addr, bank);
169*4882a593Smuzhiyun if (error)
170*4882a593Smuzhiyun return error;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun error = regmap_read(regmap, test2_addr, ®);
173*4882a593Smuzhiyun if (error)
174*4882a593Smuzhiyun return error;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun reg &= PM8058_SMPS_ADVANCED_MODE_MASK;
177*4882a593Smuzhiyun /* Check if in advanced mode. */
178*4882a593Smuzhiyun if (reg == PM8058_SMPS_ADVANCED_MODE) {
179*4882a593Smuzhiyun /* Determine current output voltage. */
180*4882a593Smuzhiyun error = regmap_read(regmap, ctrl_addr, ®);
181*4882a593Smuzhiyun if (error)
182*4882a593Smuzhiyun return error;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun band = reg & PM8058_SMPS_ADVANCED_BAND_MASK;
185*4882a593Smuzhiyun band >>= PM8058_SMPS_ADVANCED_BAND_SHIFT;
186*4882a593Smuzhiyun switch (band) {
187*4882a593Smuzhiyun case 3:
188*4882a593Smuzhiyun vref_sel = 0;
189*4882a593Smuzhiyun vlow_sel = 0;
190*4882a593Smuzhiyun break;
191*4882a593Smuzhiyun case 2:
192*4882a593Smuzhiyun vref_sel = PM8058_SMPS_LEGACY_VREF_SEL;
193*4882a593Smuzhiyun vlow_sel = 0;
194*4882a593Smuzhiyun break;
195*4882a593Smuzhiyun case 1:
196*4882a593Smuzhiyun vref_sel = PM8058_SMPS_LEGACY_VREF_SEL;
197*4882a593Smuzhiyun vlow_sel = PM8058_SMPS_LEGACY_VLOW_SEL;
198*4882a593Smuzhiyun break;
199*4882a593Smuzhiyun default:
200*4882a593Smuzhiyun pr_err("%s: regulator already disabled\n", __func__);
201*4882a593Smuzhiyun return -EPERM;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun vprog = reg & PM8058_SMPS_ADVANCED_VPROG_MASK;
204*4882a593Smuzhiyun /* Round up if fine step is in use. */
205*4882a593Smuzhiyun vprog = (vprog + 1) >> 1;
206*4882a593Smuzhiyun if (vprog > PM8058_SMPS_LEGACY_VPROG_MASK)
207*4882a593Smuzhiyun vprog = PM8058_SMPS_LEGACY_VPROG_MASK;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun /* Set VLOW_SEL bit. */
210*4882a593Smuzhiyun bank = PM8058_REGULATOR_BANK_SEL(1);
211*4882a593Smuzhiyun error = regmap_write(regmap, test2_addr, bank);
212*4882a593Smuzhiyun if (error)
213*4882a593Smuzhiyun return error;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun error = regmap_update_bits(regmap, test2_addr,
216*4882a593Smuzhiyun PM8058_REGULATOR_BANK_WRITE | PM8058_REGULATOR_BANK_MASK
217*4882a593Smuzhiyun | PM8058_SMPS_LEGACY_VLOW_SEL,
218*4882a593Smuzhiyun PM8058_REGULATOR_BANK_WRITE |
219*4882a593Smuzhiyun PM8058_REGULATOR_BANK_SEL(1) | vlow_sel);
220*4882a593Smuzhiyun if (error)
221*4882a593Smuzhiyun return error;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* Switch to legacy mode */
224*4882a593Smuzhiyun bank = PM8058_REGULATOR_BANK_SEL(7);
225*4882a593Smuzhiyun error = regmap_write(regmap, test2_addr, bank);
226*4882a593Smuzhiyun if (error)
227*4882a593Smuzhiyun return error;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun error = regmap_update_bits(regmap, test2_addr,
230*4882a593Smuzhiyun PM8058_REGULATOR_BANK_WRITE |
231*4882a593Smuzhiyun PM8058_REGULATOR_BANK_MASK |
232*4882a593Smuzhiyun PM8058_SMPS_ADVANCED_MODE_MASK,
233*4882a593Smuzhiyun PM8058_REGULATOR_BANK_WRITE |
234*4882a593Smuzhiyun PM8058_REGULATOR_BANK_SEL(7) |
235*4882a593Smuzhiyun PM8058_SMPS_LEGACY_MODE);
236*4882a593Smuzhiyun if (error)
237*4882a593Smuzhiyun return error;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /* Enable locally, enable pull down, keep voltage the same. */
240*4882a593Smuzhiyun error = regmap_update_bits(regmap, ctrl_addr,
241*4882a593Smuzhiyun PM8058_REGULATOR_ENABLE_MASK |
242*4882a593Smuzhiyun PM8058_REGULATOR_PULL_DOWN_MASK |
243*4882a593Smuzhiyun PM8058_SMPS_LEGACY_VREF_SEL |
244*4882a593Smuzhiyun PM8058_SMPS_LEGACY_VPROG_MASK,
245*4882a593Smuzhiyun PM8058_REGULATOR_ENABLE | PM8058_REGULATOR_PULL_DOWN_EN
246*4882a593Smuzhiyun | vref_sel | vprog);
247*4882a593Smuzhiyun if (error)
248*4882a593Smuzhiyun return error;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /* Enable in master control register. */
252*4882a593Smuzhiyun error = regmap_update_bits(regmap, master_enable_addr,
253*4882a593Smuzhiyun master_enable_bit, master_enable_bit);
254*4882a593Smuzhiyun if (error)
255*4882a593Smuzhiyun return error;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun /* Disable locally and enable pull down. */
258*4882a593Smuzhiyun return regmap_update_bits(regmap, ctrl_addr,
259*4882a593Smuzhiyun PM8058_REGULATOR_ENABLE_MASK | PM8058_REGULATOR_PULL_DOWN_MASK,
260*4882a593Smuzhiyun PM8058_REGULATOR_DISABLE | PM8058_REGULATOR_PULL_DOWN_EN);
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
pm8058_disable_ldo_locally_set_pull_down(struct regmap * regmap,u16 ctrl_addr,u16 master_enable_addr,u8 master_enable_bit)263*4882a593Smuzhiyun static int pm8058_disable_ldo_locally_set_pull_down(struct regmap *regmap,
264*4882a593Smuzhiyun u16 ctrl_addr, u16 master_enable_addr, u8 master_enable_bit)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun int error;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun /* Enable LDO in master control register. */
269*4882a593Smuzhiyun error = regmap_update_bits(regmap, master_enable_addr,
270*4882a593Smuzhiyun master_enable_bit, master_enable_bit);
271*4882a593Smuzhiyun if (error)
272*4882a593Smuzhiyun return error;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun /* Disable LDO in CTRL register and set pull down */
275*4882a593Smuzhiyun return regmap_update_bits(regmap, ctrl_addr,
276*4882a593Smuzhiyun PM8058_REGULATOR_ENABLE_MASK | PM8058_REGULATOR_PULL_DOWN_MASK,
277*4882a593Smuzhiyun PM8058_REGULATOR_DISABLE | PM8058_REGULATOR_PULL_DOWN_EN);
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
pm8058_pwrkey_shutdown(struct pmic8xxx_pwrkey * pwrkey,bool reset)280*4882a593Smuzhiyun static int pm8058_pwrkey_shutdown(struct pmic8xxx_pwrkey *pwrkey, bool reset)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun int error;
283*4882a593Smuzhiyun struct regmap *regmap = pwrkey->regmap;
284*4882a593Smuzhiyun u8 mask, val;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun /* When shutting down, enable active pulldowns on important rails. */
287*4882a593Smuzhiyun if (!reset) {
288*4882a593Smuzhiyun /* Disable SMPS's 0,1,3 locally and set pulldown enable bits. */
289*4882a593Smuzhiyun pm8058_disable_smps_locally_set_pull_down(regmap,
290*4882a593Smuzhiyun PM8058_S0_CTRL, PM8058_S0_TEST2,
291*4882a593Smuzhiyun REG_PM8058_VREG_EN_MSM, BIT(7));
292*4882a593Smuzhiyun pm8058_disable_smps_locally_set_pull_down(regmap,
293*4882a593Smuzhiyun PM8058_S1_CTRL, PM8058_S1_TEST2,
294*4882a593Smuzhiyun REG_PM8058_VREG_EN_MSM, BIT(6));
295*4882a593Smuzhiyun pm8058_disable_smps_locally_set_pull_down(regmap,
296*4882a593Smuzhiyun PM8058_S3_CTRL, PM8058_S3_TEST2,
297*4882a593Smuzhiyun REG_PM8058_VREG_EN_GRP_5_4, BIT(7) | BIT(4));
298*4882a593Smuzhiyun /* Disable LDO 21 locally and set pulldown enable bit. */
299*4882a593Smuzhiyun pm8058_disable_ldo_locally_set_pull_down(regmap,
300*4882a593Smuzhiyun PM8058_L21_CTRL, REG_PM8058_VREG_EN_GRP_5_4,
301*4882a593Smuzhiyun BIT(1));
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /*
305*4882a593Smuzhiyun * Fix-up: Set regulator LDO22 to 1.225 V in high power mode. Leave its
306*4882a593Smuzhiyun * pull-down state intact. This ensures a safe shutdown.
307*4882a593Smuzhiyun */
308*4882a593Smuzhiyun error = regmap_update_bits(regmap, PM8058_L22_CTRL, 0xbf, 0x93);
309*4882a593Smuzhiyun if (error)
310*4882a593Smuzhiyun return error;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun /* Enable SMPL if resetting is desired */
313*4882a593Smuzhiyun mask = SLEEP_CTRL_SMPL_EN_RESET;
314*4882a593Smuzhiyun val = 0;
315*4882a593Smuzhiyun if (reset)
316*4882a593Smuzhiyun val = mask;
317*4882a593Smuzhiyun return regmap_update_bits(regmap, PM8058_SLEEP_CTRL, mask, val);
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
pm8921_pwrkey_shutdown(struct pmic8xxx_pwrkey * pwrkey,bool reset)320*4882a593Smuzhiyun static int pm8921_pwrkey_shutdown(struct pmic8xxx_pwrkey *pwrkey, bool reset)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun struct regmap *regmap = pwrkey->regmap;
323*4882a593Smuzhiyun u8 mask = SLEEP_CTRL_SMPL_EN_RESET;
324*4882a593Smuzhiyun u8 val = 0;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun /* Enable SMPL if resetting is desired */
327*4882a593Smuzhiyun if (reset)
328*4882a593Smuzhiyun val = mask;
329*4882a593Smuzhiyun return regmap_update_bits(regmap, PM8921_SLEEP_CTRL, mask, val);
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun
pmic8xxx_pwrkey_probe(struct platform_device * pdev)332*4882a593Smuzhiyun static int pmic8xxx_pwrkey_probe(struct platform_device *pdev)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun struct input_dev *pwr;
335*4882a593Smuzhiyun int key_release_irq = platform_get_irq(pdev, 0);
336*4882a593Smuzhiyun int key_press_irq = platform_get_irq(pdev, 1);
337*4882a593Smuzhiyun int err;
338*4882a593Smuzhiyun unsigned int delay;
339*4882a593Smuzhiyun unsigned int pon_cntl;
340*4882a593Smuzhiyun struct regmap *regmap;
341*4882a593Smuzhiyun struct pmic8xxx_pwrkey *pwrkey;
342*4882a593Smuzhiyun u32 kpd_delay;
343*4882a593Smuzhiyun bool pull_up;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun if (of_property_read_u32(pdev->dev.of_node, "debounce", &kpd_delay))
346*4882a593Smuzhiyun kpd_delay = 15625;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun /* Valid range of pwr key trigger delay is 1/64 sec to 2 seconds. */
349*4882a593Smuzhiyun if (kpd_delay > USEC_PER_SEC * 2 || kpd_delay < USEC_PER_SEC / 64) {
350*4882a593Smuzhiyun dev_err(&pdev->dev, "invalid power key trigger delay\n");
351*4882a593Smuzhiyun return -EINVAL;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun pull_up = of_property_read_bool(pdev->dev.of_node, "pull-up");
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun regmap = dev_get_regmap(pdev->dev.parent, NULL);
357*4882a593Smuzhiyun if (!regmap) {
358*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to locate regmap for the device\n");
359*4882a593Smuzhiyun return -ENODEV;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun pwrkey = devm_kzalloc(&pdev->dev, sizeof(*pwrkey), GFP_KERNEL);
363*4882a593Smuzhiyun if (!pwrkey)
364*4882a593Smuzhiyun return -ENOMEM;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun pwrkey->shutdown_fn = of_device_get_match_data(&pdev->dev);
367*4882a593Smuzhiyun pwrkey->regmap = regmap;
368*4882a593Smuzhiyun pwrkey->key_press_irq = key_press_irq;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun pwr = devm_input_allocate_device(&pdev->dev);
371*4882a593Smuzhiyun if (!pwr) {
372*4882a593Smuzhiyun dev_dbg(&pdev->dev, "Can't allocate power button\n");
373*4882a593Smuzhiyun return -ENOMEM;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun input_set_capability(pwr, EV_KEY, KEY_POWER);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun pwr->name = "pmic8xxx_pwrkey";
379*4882a593Smuzhiyun pwr->phys = "pmic8xxx_pwrkey/input0";
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun delay = (kpd_delay << 6) / USEC_PER_SEC;
382*4882a593Smuzhiyun delay = ilog2(delay);
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun err = regmap_read(regmap, PON_CNTL_1, &pon_cntl);
385*4882a593Smuzhiyun if (err < 0) {
386*4882a593Smuzhiyun dev_err(&pdev->dev, "failed reading PON_CNTL_1 err=%d\n", err);
387*4882a593Smuzhiyun return err;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun pon_cntl &= ~PON_CNTL_TRIG_DELAY_MASK;
391*4882a593Smuzhiyun pon_cntl |= (delay & PON_CNTL_TRIG_DELAY_MASK);
392*4882a593Smuzhiyun if (pull_up)
393*4882a593Smuzhiyun pon_cntl |= PON_CNTL_PULL_UP;
394*4882a593Smuzhiyun else
395*4882a593Smuzhiyun pon_cntl &= ~PON_CNTL_PULL_UP;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun err = regmap_write(regmap, PON_CNTL_1, pon_cntl);
398*4882a593Smuzhiyun if (err < 0) {
399*4882a593Smuzhiyun dev_err(&pdev->dev, "failed writing PON_CNTL_1 err=%d\n", err);
400*4882a593Smuzhiyun return err;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun err = devm_request_irq(&pdev->dev, key_press_irq, pwrkey_press_irq,
404*4882a593Smuzhiyun IRQF_TRIGGER_RISING,
405*4882a593Smuzhiyun "pmic8xxx_pwrkey_press", pwr);
406*4882a593Smuzhiyun if (err) {
407*4882a593Smuzhiyun dev_err(&pdev->dev, "Can't get %d IRQ for pwrkey: %d\n",
408*4882a593Smuzhiyun key_press_irq, err);
409*4882a593Smuzhiyun return err;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun err = devm_request_irq(&pdev->dev, key_release_irq, pwrkey_release_irq,
413*4882a593Smuzhiyun IRQF_TRIGGER_RISING,
414*4882a593Smuzhiyun "pmic8xxx_pwrkey_release", pwr);
415*4882a593Smuzhiyun if (err) {
416*4882a593Smuzhiyun dev_err(&pdev->dev, "Can't get %d IRQ for pwrkey: %d\n",
417*4882a593Smuzhiyun key_release_irq, err);
418*4882a593Smuzhiyun return err;
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun err = input_register_device(pwr);
422*4882a593Smuzhiyun if (err) {
423*4882a593Smuzhiyun dev_err(&pdev->dev, "Can't register power key: %d\n", err);
424*4882a593Smuzhiyun return err;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun platform_set_drvdata(pdev, pwrkey);
428*4882a593Smuzhiyun device_init_wakeup(&pdev->dev, 1);
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun return 0;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun static const struct of_device_id pm8xxx_pwr_key_id_table[] = {
434*4882a593Smuzhiyun { .compatible = "qcom,pm8058-pwrkey", .data = &pm8058_pwrkey_shutdown },
435*4882a593Smuzhiyun { .compatible = "qcom,pm8921-pwrkey", .data = &pm8921_pwrkey_shutdown },
436*4882a593Smuzhiyun { }
437*4882a593Smuzhiyun };
438*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, pm8xxx_pwr_key_id_table);
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun static struct platform_driver pmic8xxx_pwrkey_driver = {
441*4882a593Smuzhiyun .probe = pmic8xxx_pwrkey_probe,
442*4882a593Smuzhiyun .shutdown = pmic8xxx_pwrkey_shutdown,
443*4882a593Smuzhiyun .driver = {
444*4882a593Smuzhiyun .name = "pm8xxx-pwrkey",
445*4882a593Smuzhiyun .pm = &pm8xxx_pwr_key_pm_ops,
446*4882a593Smuzhiyun .of_match_table = pm8xxx_pwr_key_id_table,
447*4882a593Smuzhiyun },
448*4882a593Smuzhiyun };
449*4882a593Smuzhiyun module_platform_driver(pmic8xxx_pwrkey_driver);
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun MODULE_ALIAS("platform:pmic8xxx_pwrkey");
452*4882a593Smuzhiyun MODULE_DESCRIPTION("PMIC8XXX Power Key driver");
453*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
454*4882a593Smuzhiyun MODULE_AUTHOR("Trilok Soni <tsoni@codeaurora.org>");
455