1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Pistachio SoC Reset Controller driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2015 Imagination Technologies Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Damien Horsley <Damien.Horsley@imgtec.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun #include <linux/reset-controller.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <dt-bindings/reset/pistachio-resets.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define PISTACHIO_SOFT_RESET 0
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct pistachio_reset_data {
23*4882a593Smuzhiyun struct reset_controller_dev rcdev;
24*4882a593Smuzhiyun struct regmap *periph_regs;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
pistachio_reset_shift(unsigned long id)27*4882a593Smuzhiyun static inline int pistachio_reset_shift(unsigned long id)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun switch (id) {
30*4882a593Smuzhiyun case PISTACHIO_RESET_I2C0:
31*4882a593Smuzhiyun case PISTACHIO_RESET_I2C1:
32*4882a593Smuzhiyun case PISTACHIO_RESET_I2C2:
33*4882a593Smuzhiyun case PISTACHIO_RESET_I2C3:
34*4882a593Smuzhiyun case PISTACHIO_RESET_I2S_IN:
35*4882a593Smuzhiyun case PISTACHIO_RESET_PRL_OUT:
36*4882a593Smuzhiyun case PISTACHIO_RESET_SPDIF_OUT:
37*4882a593Smuzhiyun case PISTACHIO_RESET_SPI:
38*4882a593Smuzhiyun case PISTACHIO_RESET_PWM_PDM:
39*4882a593Smuzhiyun case PISTACHIO_RESET_UART0:
40*4882a593Smuzhiyun case PISTACHIO_RESET_UART1:
41*4882a593Smuzhiyun case PISTACHIO_RESET_QSPI:
42*4882a593Smuzhiyun case PISTACHIO_RESET_MDC:
43*4882a593Smuzhiyun case PISTACHIO_RESET_SDHOST:
44*4882a593Smuzhiyun case PISTACHIO_RESET_ETHERNET:
45*4882a593Smuzhiyun case PISTACHIO_RESET_IR:
46*4882a593Smuzhiyun case PISTACHIO_RESET_HASH:
47*4882a593Smuzhiyun case PISTACHIO_RESET_TIMER:
48*4882a593Smuzhiyun return id;
49*4882a593Smuzhiyun case PISTACHIO_RESET_I2S_OUT:
50*4882a593Smuzhiyun case PISTACHIO_RESET_SPDIF_IN:
51*4882a593Smuzhiyun case PISTACHIO_RESET_EVT:
52*4882a593Smuzhiyun return id + 6;
53*4882a593Smuzhiyun case PISTACHIO_RESET_USB_H:
54*4882a593Smuzhiyun case PISTACHIO_RESET_USB_PR:
55*4882a593Smuzhiyun case PISTACHIO_RESET_USB_PHY_PR:
56*4882a593Smuzhiyun case PISTACHIO_RESET_USB_PHY_PON:
57*4882a593Smuzhiyun return id + 7;
58*4882a593Smuzhiyun default:
59*4882a593Smuzhiyun return -EINVAL;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
pistachio_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)63*4882a593Smuzhiyun static int pistachio_reset_assert(struct reset_controller_dev *rcdev,
64*4882a593Smuzhiyun unsigned long id)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct pistachio_reset_data *rd;
67*4882a593Smuzhiyun u32 mask;
68*4882a593Smuzhiyun int shift;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun rd = container_of(rcdev, struct pistachio_reset_data, rcdev);
71*4882a593Smuzhiyun shift = pistachio_reset_shift(id);
72*4882a593Smuzhiyun if (shift < 0)
73*4882a593Smuzhiyun return shift;
74*4882a593Smuzhiyun mask = BIT(shift);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET,
77*4882a593Smuzhiyun mask, mask);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
pistachio_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)80*4882a593Smuzhiyun static int pistachio_reset_deassert(struct reset_controller_dev *rcdev,
81*4882a593Smuzhiyun unsigned long id)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct pistachio_reset_data *rd;
84*4882a593Smuzhiyun u32 mask;
85*4882a593Smuzhiyun int shift;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun rd = container_of(rcdev, struct pistachio_reset_data, rcdev);
88*4882a593Smuzhiyun shift = pistachio_reset_shift(id);
89*4882a593Smuzhiyun if (shift < 0)
90*4882a593Smuzhiyun return shift;
91*4882a593Smuzhiyun mask = BIT(shift);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET,
94*4882a593Smuzhiyun mask, 0);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static const struct reset_control_ops pistachio_reset_ops = {
98*4882a593Smuzhiyun .assert = pistachio_reset_assert,
99*4882a593Smuzhiyun .deassert = pistachio_reset_deassert,
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
pistachio_reset_probe(struct platform_device * pdev)102*4882a593Smuzhiyun static int pistachio_reset_probe(struct platform_device *pdev)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct pistachio_reset_data *rd;
105*4882a593Smuzhiyun struct device *dev = &pdev->dev;
106*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun rd = devm_kzalloc(dev, sizeof(*rd), GFP_KERNEL);
109*4882a593Smuzhiyun if (!rd)
110*4882a593Smuzhiyun return -ENOMEM;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun rd->periph_regs = syscon_node_to_regmap(np->parent);
113*4882a593Smuzhiyun if (IS_ERR(rd->periph_regs))
114*4882a593Smuzhiyun return PTR_ERR(rd->periph_regs);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun rd->rcdev.owner = THIS_MODULE;
117*4882a593Smuzhiyun rd->rcdev.nr_resets = PISTACHIO_RESET_MAX + 1;
118*4882a593Smuzhiyun rd->rcdev.ops = &pistachio_reset_ops;
119*4882a593Smuzhiyun rd->rcdev.of_node = np;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return devm_reset_controller_register(dev, &rd->rcdev);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun static const struct of_device_id pistachio_reset_dt_ids[] = {
125*4882a593Smuzhiyun { .compatible = "img,pistachio-reset", },
126*4882a593Smuzhiyun { /* sentinel */ },
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static struct platform_driver pistachio_reset_driver = {
130*4882a593Smuzhiyun .probe = pistachio_reset_probe,
131*4882a593Smuzhiyun .driver = {
132*4882a593Smuzhiyun .name = "pistachio-reset",
133*4882a593Smuzhiyun .of_match_table = pistachio_reset_dt_ids,
134*4882a593Smuzhiyun },
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun builtin_platform_driver(pistachio_reset_driver);
137